Holger Vogt
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c2fb32f98a
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really run a dc simulation
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3 years ago |
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Holger Vogt
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d36c4b8772
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Remove bulk simulation netlist from files
needing a .control section.
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3 years ago |
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Holger Vogt
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8c98b70e45
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Add input file dedicated to batch mode,
to be run with
ngspice -b -r inv.out bsimbulk_inverter_bach.sp
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3 years ago |
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Holger Vogt
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512bcf6095
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Remove unused folder
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3 years ago |
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Holger Vogt
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dbdbcf95c2
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BSIMBULK example with locally adding osdi models
by using the 'pre_osdi' command in a .control section
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3 years ago |
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Holger Vogt
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b9eef23eed
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Update the example structure for OSDI/OpenVAF:
all compiled models into lib/ngspice
spinit updated to load the models via command 'osdi'
local calls with 'pre_osdi' commanted out.
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3 years ago |
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Holger Vogt
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5bd45eeb87
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The Roessler Attractor examples has been provided by
Giles Atkinson, of course
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3 years ago |
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Holger Vogt
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16c7c407d4
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Nice looking Roessler Attractor
provided by A. Gillespie
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3 years ago |
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Holger Vogt
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cb5f9e9bdc
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MOS example files updated and moved to its own directory
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3 years ago |
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Holger Vogt
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af9f25e985
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Various filter examples using Laplace expression x_fer
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3 years ago |
Giles Atkinson
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bf580abf69
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Add a simple example of using string-valued parameters.
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3 years ago |
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Holger Vogt
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01c211339c
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Rename example file
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3 years ago |
Brian Taylor
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4936fa2b1d
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Add serial load to 74f524 example.
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3 years ago |
dwarning
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0cae4f0b6c
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special ngbehavior needed
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3 years ago |
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Brian Taylor
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c7fd3bcaee
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Add example for 74f524.
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3 years ago |
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Holger Vogt
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4bcd4daf55
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Rename projetc to OR (OR-gate)
Add new path (absolute, so has to be modified by any user)
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3 years ago |
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Holger Vogt
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b639ebae44
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Rename examples for ECL OR gate
Simulate OR gate faster TSTEP 0.1n -> 0.3n
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3 years ago |
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Holger Vogt
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3e27e640b5
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Missing renaming: osdi_win --> osdi_libs
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3 years ago |
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Holger Vogt
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4f73f18f6d
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Remove
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3 years ago |
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Holger Vogt
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69660ad387
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Move adder_common.inc to be available for all test files.
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3 years ago |
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Holger Vogt
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bb9469a03a
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Rename test_osdi_libs to osdi_libs
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3 years ago |
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Holger Vogt
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96608abbe2
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Update with Semimod download page
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3 years ago |
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Holger Vogt
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157200aa86
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Rename test_osdi_win to test_osdi_libs
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3 years ago |
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Holger Vogt
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a211a90e5a
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Mextram models: plotting with thicker lines
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3 years ago |
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Holger Vogt
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ac73e6f7b7
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Update to the examples for osdi
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3 years ago |
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Holger Vogt
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d7bdfe1a20
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Re-add optional selection of Berkeley model parameters.
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3 years ago |
h_vogt
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5ec6543dbb
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Add log plots
Add sim vs. Temp.
Add y-labels
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3 years ago |
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Holger Vogt
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e28d3feee0
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Remove unused variable debarr.
Add another example.
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3 years ago |
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Holger Vogt
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45574cecb2
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derivative inside of .func
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3 years ago |
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Holger Vogt
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89a48e7d73
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simple example for derivative in B source
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3 years ago |
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Holger Vogt
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082ae1603e
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add linewidth for graphs
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3 years ago |
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Holger Vogt
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058e7a34f8
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tiny update, typos, font size
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3 years ago |
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Brian Taylor
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7ff8f3773f
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Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
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3 years ago |
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Brian Taylor
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cd883d23d6
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Examples for 74*568 behavioral subckts.
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3 years ago |
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Holger Vogt
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5324319edb
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Move digital examples to new locations
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3 years ago |
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Holger Vogt
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925dc55a73
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rename example file
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3 years ago |
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Holger Vogt
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ca1974ff37
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Examples moved to folder /various
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3 years ago |
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Holger Vogt
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751019b447
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Examples for d_pwm and d_osc
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3 years ago |
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Brian Taylor
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4294f49968
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Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
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3 years ago |
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Brian Taylor
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d425beb557
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Typo, 2 x1 subcircuits.
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3 years ago |
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Brian Taylor
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d54c1fc091
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Add pindly tristate example. Cleanup error handling.
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3 years ago |
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Brian Taylor
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b142be7fde
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Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
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3 years ago |
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Brian Taylor
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4e76586b6b
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Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
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3 years ago |
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Holger Vogt
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43de22ec24
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Update to the examples: enable plotting with option digitop
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3 years ago |
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Holger Vogt
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0aff89dc28
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Example for URC distributed RC transmission line
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3 years ago |
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Holger Vogt
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ec6a902fb9
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Fix a bug in simple diode, when ilimit is set, but not epsilon.
Make model more similar to LTSPICE
Add an example
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4 years ago |
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Giles Atkinson
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b212a49982
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Add some automatic bridge examples, mostly using the bidirectional bridge.
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4 years ago |
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Holger Vogt
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cb42895dad
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example for pwlts source code model
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4 years ago |
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Holger Vogt
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d39c60542d
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Enable power measurement for W switch
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4 years ago |
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Holger Vogt
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fe8eb26aaf
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Replace end-of-line comment delimiter $ by ;
So to make it independent from compatibility switch selection.
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4 years ago |
