Examples for d_pwm and d_osc

examples/xspice/pwm-osc/fmcw-dosc.cir

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+Emulate FMCW RADAR
+* with two controlled digital oscillators
+* signal delay between Vin1 and Vin2 --> frequency shift
+* delay 20m --> shift 900 Hz, 10m --> 450 Hz
+
+.param rdelay = 20m
+
+* emitted signal (repeated frequency ramp)
+Vin1 ain1 0 pulse (-1 1 0 200m 200m 1n 200m)
+aosc1 ain1 dout1 var_clock
+* emulate backscattered signal with delay (due to distant target)
+Vin2 ain2 0 pulse (-1 1 {rdelay} 200m 200m 1n 200m)
+aosc2 ain2 dout2 var_clock
+
+.model var_clock d_osc(cntl_array = [-2 -1 1 2]
++ freq_array = [1e3 1e3 10e3 10e3]
++ duty_cycle = 0.4 init_phase = 180.0
++ rise_delay = 10e-9 fall_delay=8e-9)
+
+** generate the beat frequency
+* AND gate as analog multiplier with i/o amplitude 1
+aand1 [dout1 dout2] mout and1
+.model and1 d_and(rise_delay = 0.5e-9 fall_delay = 0.3e-9
++ input_load = 0.5e-12)
+
+* low pass filter
+Rf1 mout afout 1k
+Cf1 afout 0 1u
+
+.tran 10u 1
+
+.control
+run
+rusage
+plot ain1 ain2 dout1 dout2
+plot mout afout
+plot afout
+* measure the beat frequency (aka instantaneous frequency shift)
+linearize afout
+fft afout
+let mafout = mag(afout)
+plot mafout xlimit 0 1k ylimit 0 0.2
+meas sp maxout max mafout from=10 to=1k
+.endc
+
+.end

examples/xspice/pwm-osc/pwm-sin.cir

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+*** XSPICE_PWM for audio demo *****************************
+* sin in --> pwm --> filter --> sin out to load
+
+* PWM with input frequency 1200k, variable duty cycle
+apwm in dout pwm
+.model pwm d_pwm(
++ frequency = 1.2Meg
++ cntl_array = [-1 -0.99 0.99 1]
++ dc_array = [0.01 0.01 0.99 0.99]
++ init_phase = 90)
+
+* D to A including inverted output
+aout [~dout dout] [outn outp] dac1
+
+.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0
++ input_load = 5.0e-12 t_rise = 2e-9
++ t_fall = 2e-9)
+
+* LC filter *********************
+L1 outn outflcn 33u
+CLfiltern outflcn 0 0.1u
+
+Cboth outflcn outflcp 0.47u
+
+L2 outp outflcp 33u
+CLfilterp outflcp 0 0.1u
+*********************************
+
+* load
+RLooad  outflcp  outflcn 8
+
+* input voltage
+Vin in 0 dc 0 sin (0 0.95 1.01k)
+* reference for comparison (input shifted by 3.05 degrees for compensating latency)
+Vref ref 0 dc 0 sin (0 0.95 1.01k 0 0 -3.05)
+
+.control
+tran 0.5u 20m uic
+rusage
+plot v(outn) v(outp) v(in)+2 xlimit 11.65m 12.15m ylabel 'digital output versus vin'
+plot 0.99 * v(ref) - v(outflcp) + v(outflcn) ylimit -2m 2m ylabel 'Difference between input and output'
+plot 0.99 * v(ref) v(outflcp)-v(outflcn)  ylabel 'Input and output'
+.endc
+
+.end