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Brian Taylor
0e50efc1fa
Add missing value in the last line.
FIXME: we need to check the input for having adequate columns
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7 months ago |
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d_lut
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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d_process
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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d_source
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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delay
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Obtain memory and simulation time
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4 years ago |
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delta-sigma
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add y-axis label
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4 years ago |
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filesource
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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ghdl
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Add co-simulation with VHDL, using the GHDL compiler and d_cosim.
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10 months ago |
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icarus_verilog
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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original-examples
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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pll
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Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,
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10 months ago |
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pwm-osc
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Examples for d_pwm and d_osc
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3 years ago |
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see
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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state
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Fix d_process named pipes example. Use the correct gtkwave command for MacOS.
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10 months ago |
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table
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New tables for MOS devices
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4 years ago |
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transmission_lines
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Fix the xspice transmission_line examples.
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8 months ago |
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various
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
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verilator
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Exxx n1 n2 nc1 nc2 TABLE = (x0, y0, x1, y1, x2, y2)
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6 months ago |
