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377 Commits (c7fd3bcaee7487790f70375f2c1be3987c93255d)

Author SHA1 Message Date
Brian Taylor c7fd3bcaee Add example for 74f524.
3 years ago
Holger Vogt 4bcd4daf55 Rename projetc to OR (OR-gate)
3 years ago
Holger Vogt b639ebae44 Rename examples for ECL OR gate
3 years ago
Holger Vogt 3e27e640b5 Missing renaming: osdi_win --> osdi_libs
3 years ago
Holger Vogt 4f73f18f6d Remove
3 years ago
Holger Vogt 69660ad387 Move adder_common.inc to be available for all test files.
3 years ago
Holger Vogt bb9469a03a Rename test_osdi_libs to osdi_libs
3 years ago
Holger Vogt 96608abbe2 Update with Semimod download page
3 years ago
Holger Vogt 157200aa86 Rename test_osdi_win to test_osdi_libs
3 years ago
Holger Vogt a211a90e5a Mextram models: plotting with thicker lines
3 years ago
Holger Vogt ac73e6f7b7 Update to the examples for osdi
3 years ago
Holger Vogt d7bdfe1a20 Re-add optional selection of Berkeley model parameters.
3 years ago
h_vogt 5ec6543dbb Add log plots
3 years ago
Holger Vogt e28d3feee0 Remove unused variable debarr.
3 years ago
Holger Vogt 45574cecb2 derivative inside of .func
3 years ago
Holger Vogt 89a48e7d73 simple example for derivative in B source
3 years ago
Holger Vogt 082ae1603e add linewidth for graphs
3 years ago
Holger Vogt 058e7a34f8 tiny update, typos, font size
3 years ago
Brian Taylor 7ff8f3773f Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.
3 years ago
Brian Taylor cd883d23d6 Examples for 74*568 behavioral subckts.
3 years ago
Holger Vogt 5324319edb Move digital examples to new locations
3 years ago
Holger Vogt 925dc55a73 rename example file
3 years ago
Holger Vogt ca1974ff37 Examples moved to folder /various
3 years ago
Holger Vogt 751019b447 Examples for d_pwm and d_osc
3 years ago
Brian Taylor 4294f49968 Add more vectors to behavioral 283 circuit. Add tristate buffer circuit which shows glitches until inertial delays are implemented.
3 years ago
Brian Taylor d425beb557 Typo, 2 x1 subcircuits.
3 years ago
Brian Taylor d54c1fc091 Add pindly tristate example. Cleanup error handling.
3 years ago
Brian Taylor b142be7fde Add behavioral (LOGICEXP, PINDLY) test for 283 circuit. There are glitches in the simulation for some of the s* outputs. Probably due to not having inertial delays. And why not set 'zero' delays as close to zero as permitted by XSPICE.
3 years ago
Brian Taylor 4e76586b6b Reduce the delays of 'zero' delay gates to 1.0e-11. Add decoder test for logicexpr and pindly.
3 years ago
Holger Vogt 43de22ec24 Update to the examples: enable plotting with option digitop
3 years ago
Holger Vogt 0aff89dc28 Example for URC distributed RC transmission line
3 years ago
Holger Vogt ec6a902fb9 Fix a bug in simple diode, when ilimit is set, but not epsilon.
4 years ago
Giles Atkinson b212a49982 Add some automatic bridge examples, mostly using the bidirectional bridge.
4 years ago
Holger Vogt cb42895dad example for pwlts source code model
4 years ago
Holger Vogt d39c60542d Enable power measurement for W switch
4 years ago
Holger Vogt fe8eb26aaf Replace end-of-line comment delimiter $ by ;
4 years ago
Holger Vogt f1eb8d3955 examples for .probe alli or .probe i(xx)
4 years ago
Holger Vogt 3dbfc934bb set colors for grids and data
4 years ago
Brian Taylor 4706c3dea5 Add 74xx283 4-bit adder example from the Micro Cap digital example circuits. Pspice primitives are translated to Xspice and a waveform is displayed using GTKWave. This is a digital-only test.
4 years ago
Holger Vogt e9b5a9a957 aswitch needs two input nodes because gd has been selected for input.
4 years ago
Holger Vogt c8ed9590b7 Handle the case when control voltages on and off are equal.
4 years ago
Holger Vogt 5b0b328186 If a node name to be plotted ends by ':power', its type is set to POWER.
4 years ago
Holger Vogt 2deefe1fbc New tables for MOS devices
4 years ago
Holger Vogt 765d2e8a0e Return data to input directory.
4 years ago
Holger Vogt a69dd1bcde Simplify the NMOS or PMOS selection by setting only one parameter
4 years ago
Brian Taylor 7f38ce4ebb Remove debug code.
4 years ago
Brian Taylor 112e47d0d3 This test is equivalent to examples/xspice/xspice_c3.cir and uses Pspice subckts for the divider and nand gate.
4 years ago
Brian Taylor e8dfd16cb2 Add counter test. Check for usage of $d_lo, $d_hi, $d_nc usage with dff, jkff, dltch which will not translate to Xspice.
4 years ago
Brian Taylor f7c519f149 All-digital U* device examples. No a/d or d/a interfaces on the subcircuits.
4 years ago
Holger Vogt c4efe2e3ac Update, link on device models (public domain or TI)
4 years ago