0e50efc1fa
Add missing value in the last line.
FIXME: we need to check the input for having adequate columns
7 months ago
481e3e567b
Update to filesource
Move tprev out of the loop to enable storing the previous time value.
Add some general warning message that an error might have occurred during
reading the time or data values from the data input file.
Allow empty lines in the data input file.
Guard early data values (TIME < time offset) against false reading.
Add some simple examples.
8 months ago
cc101495a5
Fix the xspice transmission_line examples.
Also, cherry pick:
commit 87d09def9c
8 months ago
70ee0f8ef5
Add examples
10 months ago
d2ded9fa2c
Tiny modifications of SEE examples
9 months ago
3fb1ea1c39
Unix line endings
rusage added
10 months ago
9d7db2166a
New example for seegen: CMOS comparator
10 months ago
07f8c3558b
Add a monitoring output the the seegen instance
10 months ago
b628032d7d
Add a generator for SEE (single event effects) pulses as a code model.
To be used like
aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1
.model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d')
see README.SEEgenerator for details
10 months ago
bba4046d55
Re-make pll-xspice.cir as a wrapper around shared-pll-xspice.cir,
behaviour as before. Add similar pll-digital-iplot.cir as a
demonstration of iplot with analogue and digital nodes.
12 months ago
592b99d0ef
Rename pll-xspice.cir to shared-pll-xspice.cir to prepare for split.
12 months ago
c7c85ecadc
Add co-simulation with VHDL, using the GHDL compiler and d_cosim.
1 year ago
00ad25fbc9
Fix d_process named pipes example. Use the correct gtkwave command for MacOS.
The following is also required:
commit 527b8378e8
1 year ago
fd3827af40
Fix ordering of parameter definition and use.
Icarus Verilog no longer accepts use-before-definition.
Also slightly expand the README for Icarus Verilog examples.
1 year ago
fdbb62844c
Example for sending a text string over the subcircuit boundary.
1 year ago
35968d1da6
Add additional examples of Verilog co-simulation and share the Verilog
source and large parts of the example circuits between Verilator and
Icarus Verilog. Verilog source file adc.v has improved style:
all assignments in the always block are now non-blocking.
2 years ago
c18447f9f5
Add the support files for co-simulation with Verilog code
compiled by Verilator. Also add script files to Visual Studio builds
that are already installed by the Makefile builds.
2 years ago
f6f7319792
Add null-pointer checks to some code that crashed when trying
to .print results from a non-existent analysis. Also remove the
troublesome .plot and .print lines from two examples.
2 years ago
864ef7925c
Add notes on the structure and organization of an external d_process program.
2 years ago
5c6b9f03b5
Fix the zero count.
2 years ago
1f5f7ae439
Update d_process examples.
2 years ago
09f070f582
Error handling improvements in cfunc.mod. Ensure that d_process.h wiil always respond to version and interface checks sent from sendheader. This is needed so that the pipe reads in sendheader do not cause Windows to hang when the interface version and in/out counts do not match. This hang was the cause of errors not being reported and the Windows gui hanging. Startup and header checks are now detected in cm_d_process, and the simulator will run but with runtime errors since a d_process model cannot be completely instantiated after initial errors. It would be good to find a means of gracefully halting the simulation run.
2 years ago
4530cde8e2
Use Xspice cm_message_send to report errors rathen than printing to stderr and calling exit. When a d_process model has errors found in start(), sendheader(), and dprocess_exchangedata() these are reported, but if the model is run a SIGINT is raised. There must be a better way of stopping the simulator.
2 years ago
182764a894
Add examples/xspice/d_process.
2 years ago
5114d6c2f4
Add an option to the iplot command: -d sets the number of simulation
steps before the window is shown. The value can be chosen to
limit rapid resizing when starting and that is used in the PLL examples.
3 years ago
a48cc44c7f
Example input file for 'iplot -w' option
3 years ago
af9f25e985
Various filter examples using Laplace expression x_fer
3 years ago
925dc55a73
rename example file
3 years ago
ca1974ff37
Examples moved to folder /various
3 years ago
751019b447
Examples for d_pwm and d_osc
3 years ago
ec6a902fb9
Fix a bug in simple diode, when ilimit is set, but not epsilon.
Make model more similar to LTSPICE
Add an example
4 years ago
cb42895dad
example for pwlts source code model
4 years ago
c8ed9590b7
Handle the case when control voltages on and off are equal.
Update the linear switch: add the limits to resistance ron, roff
Update the log switch: correct the resistance calculation for
von < voff
Add some examples for the pswitch.
4 years ago
2deefe1fbc
New tables for MOS devices
4 years ago
765d2e8a0e
Return data to input directory.
4 years ago
a69dd1bcde
Simplify the NMOS or PMOS selection by setting only one parameter
'mostype'
ngspice-37+ is required.
4 years ago
afde37c35d
add y-axis label
4 years ago
2981d0f56d
Use 'esave none' to reduce memory consumption.
Only analg nodes are to be saved.
4 years ago
738ac4863c
Obtain memory and simulation time
Add rusage information command
4 years ago
70e4d2157e
New names for the (experimental) ramp-time capacitor and inductor code models
5 years ago
05624bedd3
move examples file to prpoer xspice folder
5 years ago
6c3b14e396
make simulation faster, allow batch mode
6 years ago
9dec5f5f1e
An example for non-convergence of the pll if the stepszelimit is removed.
Adding a somewhat relaxed limit by TMAX in the tran command will speed
up the simulation by a factor of 1.5 without compromising the result.
7 years ago
f46135cc03
script to start GTKWave
8 years ago
bd5379d760
one tran analysis is sufficient
8 years ago
3138811acd
README for the table model and its table directory
8 years ago
925cb49ff2
Add some description, correct minor bugs.
8 years ago
800c9711f2
add a flag 'type of the union' to safely free model->param[i]->element,
if it contain a malloced string
8 years ago
f988dfad93
add plotting to the example
8 years ago
9becf1313a
complex model: a script loads two circuits with MOS and
bipolar table models, and run a sequence of dc simulations
with switching the circuit.
8 years ago
Brian Taylor
Holger Vogt
Brian Taylor
Vadim Kuznetsov
Giles Atkinson
dwarning