MOS example files updated and moved to its own directory

examples/various/nmos_out_BSIM330_plainwrite.sp → examples/mos/nmos_out_BSIM330_plainwrite.sp

@@ -31,7 +31,7 @@ set nolegend
 *set plainplot
 plot v(+22) plainplot
 set plainwrite
-write test.out v(+22) vss#branch dc1.v(/22) dc1.vss#branch
+*write test.out v(+22) vss#branch dc1.v(/22) dc1.vss#branch
 unset nolegend
 set color0=white
 *unset plainplot ; required if 'set plainplot'

examples/mos/nmos_pmos_BSIM482.sp

@@ -0,0 +1,48 @@
+***  Single NMOS and PMOS Transistor BSIM4 (Id-Vgs, Vbs) (Id-Vds, Vgs) (Id-Vgs, T)  ***
+
+M1 2 1 3 4 n1 W=1u L=0.35u Pd=1.5u Ps=1.5u ad=1.5p as=1.5p
+vgsn 1 0 3.5
+vdsn 2 0 0.1
+vssn 3 0 0
+vbsn 4 0 0
+
+M2 22 11 33 44 p1 W=2.5u L=0.35u Pd=3u Ps=3u ad=2.5p as=2.5p
+vgsp 11 0 -3.5
+vdsp 22 0 -0.1
+vssp 33 0 0
+vbsp 44 0 0
+
+* modified parameters
+*.model n1 nmos level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16
+*.model p1 pmos level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16
+
+* BSIM3v3.3.0 model with internal parameters only
+.model n1 nmos level=54 version=4.8.2
+.model p1 pmos level=54 version=4.8.2
+
+.control
+set xgridwidth=2
+set xbrushwidth=3
+
+* NMOS
+dc vgsn 0 1.5 0.05 vbsn 0 -2.5 -0.5
+plot vssn#branch ylabel 'Id vs. Vgs, Vbs 0 ... -2.5'
+plot abs(vssn#branch) ylog ylabel 'Id vs. Vgs, Vbs 0 ... -2.5'
+dc vdsn 0 2 0.05 vgsn 0 2 0.4
+plot vssn#branch ylabel 'Id vs. Vds, Vgs 0 ... 2'
+dc vgsn 0 1.5 0.05 temp -40 160 40
+plot vssn#branch ylabel 'Id vs. Vds, Temp. -40 ... 160'
+plot abs(vssn#branch) ylog ylabel 'Id vs. Vds, Temp. -40 ... 160'
+
+* PMOS
+dc vgsp 0 -1.5 -0.05 vbsp 0 2.5 0.5
+plot vssp#branch ylabel 'Id vs. Vgs, Vbs 0 ... 2.5'
+plot abs(vssp#branch) ylog ylabel 'Id vs. Vgs, Vbs 0 ... 2.5'
+dc vdsp 0 -2 -0.05 vgsp 0 -2 -0.4
+plot vssp#branch ylabel 'Id vs. Vds, Vgs 0 ... -2'
+dc vgsp 0 -1.5 -0.05 temp -40 160 40
+plot vssp#branch ylabel 'Id vs. Vds, Temp. -40 ... 160'
+plot abs(vssp#branch) ylog ylabel 'Id vs. Vds, Temp. -40 ... 160'
+.endc
+
+.end

examples/mos/nmos_pmos_drainresistor.sp

@@ -0,0 +1,51 @@
+** Single NMOS and PMOS, BSIM3, (Id-Vgs) (Id-Vds) **
+
+M1 2 1 3 4 n1 W=1u L=0.35u Pd=1.5u Ps=1.5u ad=1.5p as=1.5p
+vgsn 1 0 3.5 
+vdsn 102 0 0.1
+Rdn 102 2 1k
+vssn 3 0 0
+vbsn 4 0 0
+
+M2 22 11 33 44 p1 W=2.5u L=0.35u Pd=3u Ps=3u ad=2.5p as=2.5p
+vgsp 11 0 -3.5 
+vdsp 222 0 -0.1
+Rdp 222 22 1k
+vssp 33 0 0
+vbsp 44 0 0
+
+.options Temp=27.0
+
+* BSIM3v3.3.0 model with modified default parameters 0.18µm
+.model n1 nmos level=49 version=3.3.0 tox=3.5n nch=2.4e17 nsub=5e16 vth0=0.15
+.model p1 pmos level=49 version=3.3.0 tox=3.5n nch=2.5e17 nsub=5e16 vth0=-0.15
+
+*.include ./Modelcards/modelcard.nmos $ Berkeley model cards limited to L >= 0.35µm
+*.include ./Modelcards/modelcard.pmos $ Berkeley model cards limited to L >= 0.35µm
+
+* update of the default parameters required
+*.model n1 NMOS level=49 version=3.3.0 $ nearly no current due to VT > 2 V ?
+*.model p1 PMOS level=49 version=3.3.0
+
+.control
+* various plot font sizes
+dc vgsn 0 1.5 0.05 vbsn 0 -2.5 -0.5
+plot vssn#branch ylabel 'output current'
+set wfont_size=16
+dc vdsn 0 2 0.05 vgsn 0 2 0.4
+plot vssn#branch vs v(2) ylabel 'output current'
+set wfont_size=24
+dc vgsp 0 -1.5 -0.05 vbsp 0 2.5 0.5
+plot vssp#branch ylabel 'output current'
+set wfont=Times
+set wfont_size=22
+dc vdsp 0 -2 -0.05 vgsp 0 -2 -0.4
+plot vssp#branch vs v(22) ylabel 'output current'
+.endc
+
+.end
+
+
+
+
+

examples/various/nmos_out_BSIM330.sp

@@ -1,37 +0,0 @@
-*****  NMOS Transistor BSIM3 (Id-Vds) with Rd ***
-
-M1 2 1 3 4 n1 W=1u L=0.35u Pd=1.5u Ps=1.5u ad=1.5p as=1.5p
-vgs 1 0 3.5 
-vds 2 0 0.1 
-vss 3 0 0
-vbs 4 0 0
-
-* drain series resistor
-R2 2 22 1k
-M2 22 1 32 4 n1 W=1u L=0.35u Pd=1.5u Ps=1.5u ad=1.5p as=1.5p
-vss2 32 0 0
-
-
-.options Temp=27.0
-
-* BSIM3v3.3.0 model with modified default parameters 0.18µm
-.model n1 nmos level=49 version=3.3.0 tox=3.5n nch=2.4e17 nsub=5e16 vth0=0.15
-.model p1 pmos level=49 version=3.3.0 tox=3.5n nch=2.5e17 nsub=5e16 vth0=-0.15
-
-.control
-set xgridwidth=2
-set xbrushwidth=3
-dc vds 0 2 0.05 vgs 0 2 0.4
-set nolegend
-plot vss#branch title 'Drain current versus drain voltage' xlabel 'Drain voltage' ylabel 'Drain current'
-unset nolegend
-set color0=white
-plot vss2#branch vs v(22) title 'Series resistor: Drain current versus drain voltage' xlabel 'Drain voltage' ylabel 'Drain current'
-.endc
-
-.end
-
-
-
-
-