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      DEVICES

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DEVICES
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@ -1,17 +1,81 @@
DEVICES
---------------------------------------------------------------------------
=======
Table of contents
1. Introduction
2. Linear Devices
2.1 CAP - Linear capacitor
2.2 IND - Linear inductor
2.3 RES - Linear resistor
3. Distributed Elements
3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
3.2 LTRA - Lossy Transmission line
3.3 TRA - Transmission line
3.4 TXL - Simple Lossy Transmission Line (Kspice)
3.5 URC - Uniform distributed RC line
4. Voltage and current sources
4.1 ASRC - Arbitrary Source
4.2 CCCS - Current Controlled Current Source
4.3 CCVS - Current Controlled Voltage Source
4.4 ISRC - Independent Current Source
4.5 VCCS - Voltage Controlled Current Source
4.6 VCVS - Voltage Controlled Voltage Source
4.7 VSRC - Independent Voltage Source
5. Switches
5.1 CSW - Current controlled switch
5.2 SW - Voltage controlled switch
6. Diodes
6.1 DIO - Junction Diode
7. Bipolar devices
7.1 BJT - Bipolar Junction Transistor
7.2 BJT2 - Bipolar Junction Transistor
7.3 VBIC - Bipolar Junction Transistor
8. FET devices
8.1 JFET - Junction Field Effect transistor
9. HFET Devices
9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
10. MES devices
10.1 MES - MESFET model
10.2 MESA - MESFET model (MacSpice3f4)
11. MOS devices
11.1 MOS1 - Level 1 MOS model
11.2 MOS2 - Level 2 MOS model
11.3 MOS3 - Level 3 MOS model
11.4 MOS6 - Level 6 MOS model
11.5 MOS9 - Level 9 MOS model
11.6 BSIM1 - BSIM model level 1
11.7 BSIM2 - BSIM model level 2
11.8 BSIM3v0 - BSIM model level 3
11.9 BSIM3v1 - BSIM model level 3
11.10 BSIM3v1 - BSIM model level 3
11.11 BSIM3v1 - BSIM model level 3
11.12 BSIM3 - BSIM model level 3
11.13 BSIM4 - BSIM model level 4 (0.18 um)
11.14 HiSIM - Hiroshima-university STARC IGFET Model
12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
12.4 BSIM3SOI - SOI model (partially/full depleted devices)
12.5 SOI3 - STAG SOI3 Model
13. Other devices
13.1 EKV - EKV model
------------------
1. Introduction
This file contains the status of devices available in ngspice. This file
will be updated every time the device specific code is altered or changed.
This file is useful in writing ngspice documentation.
will be updated every time the device specific code is altered or changed to reflect the current status of this important part of the simulator
***************************************************************************
************************* Linear devices ********************************
***************************************************************************
2. Linear Devices
2.1 CAP - Linear capacitor
CAP - Capacitor
Initial Release.
Ver: N/A
Class: C
Level: 1 (and only)
@ -19,7 +83,6 @@ CAP - Capacitor
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Preliminary technology scaling support
@ -27,8 +90,9 @@ CAP - Capacitor
- Cj calculation based on relative dielectric constant
and insulator thickness
IND - Inductor
Initial Release.
2.2 IND - Linear Inductor
Ver: N/A
Class: L
Level: 1 (and only)
@ -36,7 +100,6 @@ IND - Inductor
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Preliminary technology scaling support
@ -44,8 +107,8 @@ IND - Inductor
- Inductance calculation for toroids or solenoids
on the model line.
RES - Simple linear resistor
Initial Release.
2.3 RES - Linear resistor
Ver: N/A
Class: R
Level: 1 (and only)
@ -53,7 +116,6 @@ RES - Simple linear resistor
Status:
Enhancements over the original model:
- Parallel Multiplier
- Different value for ac analysis
- Temperature difference from circuit temperature
@ -62,12 +124,11 @@ RES - Simple linear resistor
- Preliminary technology scaling support
***************************************************************************
********************* Distributed elements ********************************
***************************************************************************
3. Distributed elements
3.1 CPL - Simple Coupled Multiconductor Lines (Kspice)
CPL - Simple Coupled Multiconductor Lines (Kspice)
Initial Release.
Ver: N/A
Class: P
Level: 1 (and only)
@ -86,33 +147,30 @@ CPL - Simple Coupled Multiconductor Lines (Kspice)
- Better integrated into ngspice adding CPLask, CPLmAsk and
CPLunsetup functions
3.2 LTRA - Lossy Transmission line
LTRA - Lossy Transmission line
Initial Release.
Ver: N/A
Class: O
Level: 1 (and only)
Dir: devices/ltra
Status:
Original spice model.
- Original spice model.
- Does not implement parallel code switches.
- Does not implement parallel code switches
3.3 TRA - Transmission line
TRA - Transmission line
Initial Release.
Ver: N/A
Class: T
Level: 1 (and only)
Dir: devices/tra
Status:
Original spice model.
- Original spice model.
- Does not implement parallel code switches.
- Does not implement parallel code switches
3.4 TXL - Simple Lossy Transmission Line (Kspice)
TXL - Simple Lossy Transmission Line (Kspice)
Initial Release.
Ver: N/A
Class: Y
Level: 1 (and only)
@ -129,25 +187,22 @@ TXL - Simple Lossy Transmission Line (Kspice)
- Does not implement parallel code switches
URC - Uniform distributed RC line
Initial Release.
3.5 URC - Uniform distributed RC line
Ver: N/A
Class: U
Level: 1 (and only)
Dir: devices/urc
Status:
Original spice model.
- Original spice model.
- Does not implement parallel code switches.
- Does not implement parallel code switches
4. Voltage and current sources
***************************************************************************
**************************** V/I Sources *****************************
***************************************************************************
4.1 ASRC - Arbitrary Source
ASRC - Arbitrary Source
Initial Release.
Ver: N/A
Class: B
Level: 1 (and only)
@ -158,28 +213,29 @@ ASRC - Arbitrary Source
available on the Internet. There is still an issue to fix, the
current of current-controlled generators.
CCCS - Current Controlled Current Source
Initial Release.
4.2 CCCS - Current Controlled Current Source
Ver: N/A
Class: F
Level: 1 (and only)
Dir: devices/cccs
Status:
Original spice model.
- Original spice model.
4.3 CCVS - Current Controlled Voltage Source
CCVS - Current Controlled Voltage Source
Initial Release.
Ver: N/A
Class: H
Level: 1 (and only)
Dir: devices/ccvs
Status:
Original spice model.
- Original spice model.
4.4 ISRC - Independent Current Source
ISRC - Independent Current Source
Initial Release.
Ver: N/A
Class: I
Level: 1 (and only)
@ -193,28 +249,29 @@ ISRC - Independent Current Source
- Check for non-monotonic series in PWL
VCCS - Voltage Controlled Current Source
Initial Release.
4.5 VCCS - Voltage Controlled Current Source
Ver: N/A
Class: G
Level: 1 (and only)
Dir: devices/vccs
Status:
Original spice model.
- Original spice model.
4.6 VCVS - Voltage Controlled Voltage Source
VCVS - Voltage Controlled Voltage Source
Initial Release.
Ver: N/A
Class: E
Level: 1 (and only)
Dir: devices/vcvs
Status:
Original spice model.
- Original spice model.
4.7 VSRC - Independent Voltage Source
VSRC - Independent Voltage Source
Initial Release.
Ver: N/A
Class: V
Level: 1 (and only)
@ -228,38 +285,34 @@ VSRC - Independent Voltage Source
- Check for non-monotonic series in PWL
***************************************************************************
**************************** Switches ****************************
***************************************************************************
5. Switches
5.1 CSW - Current controlled switch
CSW - Current controlled switch
Initial Release.
Ver: N/A
Class: W
Level: 1 (and only)
Dir: devices/csw
Status:
This model comes from Jon Engelbert
- This model comes from Jon Engelbert.
5.2 SW - Voltage controlled switch
SW - Voltage controlled switch
Initial release
Ver: N/A
Class: S
Level: 1 (and only)
Dir: devices/sw
Status:
This model comes from Jon Engelbert
- This model comes from Jon Engelbert.
***************************************************************************
**************************** Diodes ****************************
***************************************************************************
6. Diodes
6.1 DIO - Junction Diode
DIO - Junction Diode
Initial Release.
Ver: N/A
Class: D
Level: 1 (and only)
@ -267,7 +320,6 @@ DIO - Junction Diode
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Forward and reverse knee currents
@ -275,12 +327,10 @@ DIO - Junction Diode
- Temperature correction of some parameters
***************************************************************************
************************* Bipolar Devices *************************
***************************************************************************
7. Bipolar devices
7.1 BJT - Bipolar Junction Transistor
BJT - Bipolar Junction Transistor
Initial Release.
Ver: N/A
Class: Q
Level: 1
@ -288,13 +338,12 @@ BJT - Bipolar Junction Transistor
Status:
Enhancements over the original model:
- Parallel Multiplier
- Temperature difference from circuit temperature
- Different area parameters for collector, base and emitter
BJT2 - Bipolar Junction Transistor
Initial Release.
7.2 BJT2 - Bipolar Junction Transistor
Ver: N/A
Class: Q
Level: 2
@ -306,37 +355,32 @@ BJT2 - Bipolar Junction Transistor
and adding some features (temp. correction on resistors).
Enhancements over the original model:
- Temperature correction on rc,rb,re
- Parallel Multiplier
- Temperature difference from circuit temperature
- Different area parameters for collector, base and emitter
VBIC - Bipolar Junction Transistor
Initial Release.
7.3 VBIC - Bipolar Junction Transistor
Ver: N/A
Class: Q
Level: 4
Dir: devices/vbic
Status:
This is the Vertical Bipolar InterCompany model.
The author of VBIC is Colin McAndrew mcandrew@ieee.org
This is the Vertical Bipolar InterCompany model. The author of VBIC is
Colin McAndrew mcandrew@ieee.org
Spice3 Implementation: Dietmar Warning DAnalyse GmbH
warning@danalyse.de
Web Site:
http://www.designers-guide.com/VBIC/index.html
Web Site: http://www.designers-guide.com/VBIC/index.html
Notes: This is the 4 terminals model, without excess phase
and thermal network.
Notes: This is the 4 terminals model, without excess phase and thermal
network.
***************************************************************************
***************************** FET Devices ***************************
***************************************************************************
8. FET devices
8.1 JFET - Junction Field Effect transistor
JFET - Junction Field Effect transistor
Initial Release.
Ver: N/A
Class: J
Level: 1
@ -346,13 +390,12 @@ JFET - Junction Field Effect transistor
This is the original spice JFET model.
Enhancements over the original model:
- Alan Gillespie's modified diode model
- Parallel multiplier
- Instance temperature as difference for circuit temperature
JFET2 - Junction Field Effect Transistor (PS model)
Initial Release.
8.2 JFET2 - Junction Field Effect Transistor (PS model)
Ver: N/A
Class: J
Level: 2
@ -361,26 +404,22 @@ JFET2 - Junction Field Effect Transistor (PS model)
This is the Parker Skellern model for MESFETs.
Web Site:
http://www.elec.mq.edu.au/cnerf/models/psmodel/
Web Site: http://www.elec.mq.edu.au/cnerf/psmodel.htm
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
***************************************************************************
*************************** HFET devices ***************************
***************************************************************************
9. HFET Devices
Added code from macspice3f4 HFET1&2 and MESA model
Original note:
Added device calls for Mesfet models and HFET models
provided by Trond Ytterdal as of Nov 98
HFET1 - Heterostructure Field Effect Transistor Level 1
Initial Release.
9.1 HFET1 - Heterostructure Field Effect Transistor Level 1
Ver: N/A
Class: Z
Level: 5
@ -393,14 +432,13 @@ HFET1 - Heterostructure Field Effect Transistor Level 1
1993, Prentice Hall, New Jersey
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
- Added pole-zero analysis
HFET2 - Heterostructure Field Effect Transistor Level 2
Initial Release.
9.2 HFET2 - Heterostructure Field Effect Transistor Level 2
Ver: N/A
Class: Z
Level: 6
@ -410,18 +448,15 @@ HFET2 - Heterostructure Field Effect Transistor Level 2
Simplified version of hfet1
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference for circuit temperature
- Added pole-zero analysis
***************************************************************************
*************************** MES devices ***************************
***************************************************************************
10. MES devices
10.1 MES - MESFET model
MES - MESFET model
Initial Release.
Ver: N/A
Class: Z
Level: 1
@ -431,7 +466,6 @@ MES - MESFET model
This is the original spice3 MESFET model (Statz).
Enhancements over the original model:
- Parallel multiplier
- Alan Gillespie junction diodes implementation
@ -441,8 +475,8 @@ MES - MESFET model
Added device calls for Mesfet models and HFET models
provided by Trond Ytterdal as of Nov 98
MESA - MESFET model (MacSpice3f4)
Initial Release.
10.2 MESA - MESFET model (MacSpice3f4)
Ver: N/A
Class: Z
Level: 2,3,4
@ -453,18 +487,16 @@ MESA - MESFET model (MacSpice3f4)
2,3 and 4
Enhancements over the original model:
- Parallel multiplier
- Instance temperature as difference from circuit temperature
- Added pole-zero analysis
***************************************************************************
**************************** MOS devices ****************************
***************************************************************************
MOS1 - Level 1 MOS model
Initial Release.
11. MOS devices
11.1 MOS1 - Level 1 MOS model
Ver: N/A
Class: M
Level: 1
@ -474,13 +506,11 @@ MOS1 - Level 1 MOS model
This is the so-called Schichman-Hodges model.
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
11.2 MOS2 - Level 2 MOS model
MOS2 - Level 2 MOS model
Initial Release.
Ver: N/A
Class: M
Level: 2
@ -490,13 +520,12 @@ MOS2 - Level 2 MOS model
This is the so-called Grove-Frohman model.
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
MOS3 - Level 3 MOS model
Initial Release.
11.3 MOS3 - Level 3 MOS model
Ver: N/A
Class: M
Level: 3
@ -504,13 +533,12 @@ MOS3 - Level 3 MOS model
Status:
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
MOS6 - Level 6 MOS model
Initial Release.
11.4 MOS6 - Level 6 MOS model
Ver: N/A
Class: M
Level: 6
@ -518,13 +546,12 @@ MOS6 - Level 6 MOS model
Status:
Enhancements over the original model:
- Parallel multiplier
- Temperature difference from circuit temperature
MOS9 - Level 9 MOS model
Initial Release.
11.5 MOS9 - Level 9 MOS model
Ver: N/A
Class: M
Level: 9
@ -532,12 +559,11 @@ MOS9 - Level 9 MOS model
Status:
Enhancements over the original model:
- Temperature difference from circuit temperature
BSIM1 - BSIM model level 1
Initial Release.
11.6 BSIM1 - BSIM model level 1
Ver: N/A
Class: M
Level: 4
@ -545,7 +571,6 @@ BSIM1 - BSIM model level 1
Status:
Enhancements over the original model:
- Parallel multiplier
- Noise analysis
@ -556,8 +581,8 @@ BSIM1 - BSIM model level 1
has ideas on the subject ?
BSIM2 - BSIM model level 2
Initial Release.
11.7 BSIM2 - BSIM model level 2
Ver: N/A
Class: M
Level: 5
@ -565,22 +590,20 @@ BSIM2 - BSIM model level 2
Status:
Enhancements over the original model:
- Parallel multiplier
- Noise analysis
BSIM3v0 - BSIM model level 3
Initial Release.
11.8 BSIM3v0 - BSIM model level 3
Ver: 3.0
Class: M
Level: 8 & 49, version = 3.0
Dir: devices/bsim3v0
Status: TO BE TESTED AND IMPROVED
11.9 BSIM3v1 - BSIM model level 3
BSIM3v1 - BSIM model level 3
Initial Release.
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1
@ -588,8 +611,8 @@ BSIM3v1 - BSIM model level 3
Status: TO BE TESTED
BSIM3v1 - BSIM model level 3
Initial Release.
11.10 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1a
@ -599,8 +622,8 @@ BSIM3v1 - BSIM model level 3
This is the BSIM3v3.1 model modified by Alan Gillespie.
BSIM3v1 - BSIM model level 3
Initial Release.
11.11 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1s
@ -612,8 +635,8 @@ BSIM3v1 - BSIM model level 3
"HDIF" and "M" parameters.
BSIM3 - BSIM model level 3
Initial Release.
11.12 BSIM3 - BSIM model level 3
Ver: 3.2.4 - 3.3.0
Class: M
Level: 8 & 49, version = 3.2.2, 3.2.3, 3.2.4, 3.3.0
@ -624,36 +647,31 @@ BSIM3 - BSIM model level 3
You can find some test netlists with results for this model
on its web site.
Web site:
http://www-device.eecs.berkeley.edu/~bsim3
Web site: http://www-device.eecs.berkeley.edu/~bsim3
Enhancements over the original model:
- Parallel Multiplier
- ACM Area Calculation Method
- Multirevision code (supports all 3v3.2 minor revisions)
- NodesetFix
BSIM4 - BSIM model level 4 (0.18 um)
Initial Release.
11.13 BSIM4 - BSIM model level 4 (0.18 um)
Ver: 4.2.0 - 4.6.1
Class: M
Level: 14 & 54, version = 4.2, 4.3, 4.4, 4.5, 4.6.1
Dir: devices/bsim4
Status: TO BE TESTED
Status:
This is the BSIM4 device model from Berkeley Device Group.
Test are available on its web site.
Web site:
http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
Web site: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
Updated to 4.5.0 YET UNTESTED.
11.14 HiSIM - Hiroshima-university STARC IGFET Model
HiSIM - Hiroshima-university STARC IGFET Model
Initial Release.
Ver: 1.2.0
Class: M
Level: 64
@ -663,22 +681,17 @@ HiSIM - Hiroshima-university STARC IGFET Model
This is the HiSIM model available from Hiroshima University
(Ultra-Small Device Engineering Laboratory)
Web site:
http://home.hiroshima-u.ac.jp/usdl/HiSIM.shtml
http://www.starc.or.jp/kaihatu/pdgr/hisim/index.html
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
Enhancements over the original model:
- Parallel Multiplier
- NodesetFix
***************************************************************************
***************************** SOI Devices ****************************
***************************************************************************
12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
BSIM3SOI_FD - SOI model (fully depleted devices)
Initial Release.
Ver: 2.1
Class: M
Level: 55
@ -689,14 +702,13 @@ BSIM3SOI_FD - SOI model (fully depleted devices)
There is a bsim3soifd directory under the test
hierarchy. Test circuits come from the bsim3soi
Web site at:
http://www-device.eecs.berkeley.edu/~bsimsoi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
*) rework-14: removed #ifndef NEWCONV code.
BSIM3SOI_DD - SOI Model (dynamic depletion model)
Initial Release.
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
Ver: 2.1
Class: M
Level: 56
@ -706,32 +718,29 @@ BSIM3SOI_DD - SOI Model (dynamic depletion model)
There is a bsim3soidd directory under the
test hierarchy. Test circuits come from bsim3soi
Web site at:
http://www-device.eecs.berkeley.edu/~bsimsoi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
*) rework-14: removed #ifndef NEWCONV code.
BSIM3SOI_PD - SOI model (partially depleted devices)
Initial Release.
12.3 BSIM3SOI_PD - SOI model (partially depleted devices)
Ver: 2.2.1
Class: M
Level: 57
Dir: devices/bsim3soi_pd
Status: TO BE TESTED.
PD model has been integrated.
There is a bsim3soipd directory under the test
hierarchy. Test circuits come from the bsim3soi
PD model has been integrated. There is a bsim3soipd directory
under the test hierarchy. Test circuits come from the bsim3soi
Web site at:
http://www-device.eecs.berkeley.edu/~bsimsoi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
*) rework-14: removed #ifndef NEWCONV code.
BSIM3SOI - SOI model (partially/full depleted devices)
Initial Release.
12.4 BSIM3SOI - SOI model (partially/full depleted devices)
Ver: 4.0
Class: M
Level: 58
@ -741,28 +750,23 @@ BSIM3SOI - SOI model (partially/full depleted devices)
This is the newer version from Berkeley.
Usable for partially/full depleted devices.
Web site at:
http://www-device.eecs.berkeley.edu/~bsimsoi
Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi
12.5 SOI3 - STAG SOI3 Model
SOI3 - STAG SOI3 Model
Initial Release.
Ver: 2.6
Class: M
Level: 62
Dir: devices/soi3
Status: TO BE TESTED
Status: OBSOLETE
Web site at:
http://www.micro.ecs.soton.ac.uk/stag/
13. Other devices
***************************************************************************
**************** Other devices not released as source code ****************
***************************************************************************
13.1 EKV - EKV model
EKV - EKV model
Initial Release.
Ver: 2.6
Class: M
Level: 44
@ -772,5 +776,4 @@ EKV - EKV model
Note: This model is not released in source code.
You have to obtain the source code from the address below.
Web site at:
http://legwww.epfl.ch/ekv/
Web site at: http://legwww.epfl.ch/ekv/
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