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@ -54,6 +54,7 @@ Table of contents |
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11.12 BSIM4 - BSIM model level 4 |
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11.13 HiSIM2 - Hiroshima-University STARC IGFET Model |
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11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model |
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11.15 VDMOS - A simple PowerMOS transistor model derived from MOS1 |
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12. SOI devices |
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12.1 BSIM3SOI_FD - SOI model (fully depleted devices) |
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12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model) |
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@ -718,6 +719,17 @@ will be updated every time the device specific code is altered or changed to ref |
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Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html |
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11.15 VDMOS - Simple PowerMOS model |
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Ver: 1 |
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Class: M |
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Level: - |
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Dir: devices/vdmos |
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Status: TO BE TESTED. |
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This is a simplified Power MOS model, derived from MOS1 and |
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diode, similar to LTSPICE and SuperSpice VDMOS |
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12. SOI devices |
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12.1 BSIM3SOI_FD - SOI model (fully depleted devices) |
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