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Add some automatic bridge examples, mostly using the bidirectional bridge.
pre-master-46
Add some automatic bridge examples, mostly using the bidirectional bridge.
pre-master-46
Giles Atkinson
4 years ago
committed by
Holger Vogt
Holger Vogt
8 changed files with 211 additions and 60 deletions
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61examples/digital/adder_behav.cir
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62examples/digital/adder_common.inc
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35examples/digital/auto_bridge/74HCng_auto.lib
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11examples/digital/auto_bridge/adder_auto.cir
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20examples/digital/auto_bridge/adder_bidi.cir
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23examples/digital/auto_bridge/adder_bidi2.cir
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28examples/digital/auto_bridge/adder_bidi3.cir
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31examples/digital/auto_bridge/shared_line.cir
@ -0,0 +1,62 @@ |
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* Shared netlist for several example circuits using XSPICE-based 74HC00 model |
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.SUBCKT ONEBIT 1 2 3 4 5 6 |
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* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC |
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X1 1 2 7 6 0 74HC00 |
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X2 1 7 8 6 0 74HC00 |
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X3 2 7 9 6 0 74HC00 |
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X4 8 9 10 6 0 74HC00 |
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X5 3 10 11 6 0 74HC00 |
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X6 3 11 12 6 0 74HC00 |
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X7 10 11 13 6 0 74HC00 |
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X8 12 13 4 6 0 74HC00 |
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X9 11 7 5 6 0 74HC00 |
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.ENDS ONEBIT |
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.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 |
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* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, |
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* CARRY-IN, CARRY-OUT, VCC |
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X1 1 2 7 5 10 9 ONEBIT |
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X2 3 4 10 6 8 9 ONEBIT |
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.ENDS TWOBIT |
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.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
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* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), |
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* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC |
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X1 1 2 3 4 9 10 13 16 15 TWOBIT |
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X2 5 6 7 8 11 12 16 14 15 TWOBIT |
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.ENDS FOURBIT |
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*** POWER |
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VCC 99 0 DC 3.3V |
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*** ALL INPUTS |
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VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) |
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VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) |
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VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) |
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VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) |
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VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) |
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VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) |
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VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) |
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VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) |
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*** DEFINE NOMINAL CIRCUIT |
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X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT |
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.option noinit acct |
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.TRAN 500p 6400NS |
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* save inputs |
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.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) |
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.control |
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pre_set strict_errorhandling |
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unset ngdebug |
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*save outputs and specials |
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save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) |
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run |
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rusage |
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* plot the inputs, use offset to plot on top of each other |
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plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 |
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* plot the outputs, use offset to plot on top of each other |
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plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 |
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.endc |
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@ -0,0 +1,35 @@ |
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* 74hcng_auto.lib - simplified wrapper for XSPICE NAND gate |
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* |
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* derived from 74HCng_short_2.lib but using automatic D<->A bridges. |
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* derived from 74HCxxx Model libraray for LTSPICE from www.linear.com/software |
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* |
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* XSPICE gate models are used, with output to an analogue node. |
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* |
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* Delays are given for Vcc = 2V/4.5V/6V (HC) from the |
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* Philips data sheets. http://www.philipslogic.com |
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* |
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* Delays are given for Vcc = 2V/4.5V/6V . |
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* Used delay: Td = (Tpd-Tr/2)*(4.5-0.5)/(Vcc-0.5) |
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* The gate delay has to be set to tpd minus 3ns for the input filter |
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* and another minus 3ns for Trise/2 |
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* td1 = tpd - 3ns - 3ns |
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* |
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.param vcc=5 tripdt=6n |
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* |
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* 2-input NAND gate |
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* vcc 2 /4.5/5 /6 |
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* tpd 25n/9n/7n/7n |
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* tr 19n/7n / /6n |
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.SUBCKT 74HC00 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} |
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.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} |
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.param Rout={60*4.0/(vcc1-0.5)} ; standard output driver |
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.param Rload=10k ; The bidi bridge analogue port is type 'g' and needs load |
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a6 [in1 in2] dout nand1 |
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.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1} |
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+ input_load = 0.5e-12) |
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Rout dout out {Rout} |
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Rload dout 0 {Rload} |
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.ends |
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@ -0,0 +1,11 @@ |
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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING |
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* behavioral gate description |
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* Automatic A/D insertion |
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*** SUBCIRCUIT DEFINITIONS |
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.include 74HCng_auto.lib |
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.param vcc=3 tripdt=6n |
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.include ../adder_common.inc |
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.END |
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@ -0,0 +1,20 @@ |
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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH BIDIRECTIONAL BRIDGES |
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* behavioral gate description |
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* Automatic A/D insertion using bi-directional bridges |
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* Override the default bridges and force use of the bidi_bridge. |
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.control |
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pre_set auto_bridge_d_out = |
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+ ( ".model auto_bridge bidi_bridge(out_high=%g in_low='%g/2' in_high='%g/2' )" |
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+ "auto_bridge%d [ %s ] [ %s ] null auto_bridge" 1000 ) |
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pre_set auto_bridge_d_in = ( $auto_bridge_d_out ) |
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.endc |
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*** SUBCIRCUIT DEFINITIONS |
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.include 74HCng_auto.lib |
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.param vcc=3 tripdt=6n |
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.include ../adder_common.inc |
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.END |
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@ -0,0 +1,23 @@ |
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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING |
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* behavioral gate description |
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* Automatic A/D insertion using bi-directional bridges |
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* Override the default bridges and force use of the bidi_bridges with |
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* directions pre-set. |
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.control |
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pre_set auto_bridge_d_out = |
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+ ( ".model auto_bridge_out bidi_bridge(direction=0 out_high=%g)" |
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+ "auto_bridge_out%d [ %s ] [ %s ] null auto_bridge_out" ) |
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pre_set auto_bridge_d_in = |
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+ ( ".model auto_bridge_in bidi_bridge(direction=1 in_low='%g/2' in_high='%g/2')" |
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+ "auto_bridge_in%d [ %s ] [ %s ] null auto_bridge_in" ) |
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.endc |
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*** SUBCIRCUIT DEFINITIONS |
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.include 74HCng_auto.lib |
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.param vcc=3 tripdt=6n |
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.include ../adder_common.inc |
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.END |
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@ -0,0 +1,28 @@ |
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ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING |
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* behavioral gate description |
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* Automatic A/D insertion using bi-directional bridges |
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* Override the default bridges and force use of the bidi_bridges with |
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* directions controlled by inputs. |
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.control |
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pre_set auto_bridge_d_out = |
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+ ( ".model auto_bridge_out bidi_bridge(out_high=%g)" |
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+ "auto_bridge_out%d [ %s ] [ %s ] [ force_out ] auto_bridge_out" 1 ) |
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pre_set auto_bridge_d_in = |
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+ ( ".model auto_bridge_in bidi_bridge(in_low='%g/2' in_high='%g/2')" |
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+ "auto_bridge_in%d [ %s ] [ %s ] [ force_in ] auto_bridge_in" 1 ) |
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.endc |
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*** SUBCIRCUIT DEFINITIONS |
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.include 74HCng_auto.lib |
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.param vcc=3 tripdt=6n |
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aup force_in pullup |
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.model pullup d_pullup |
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adown force_out pulldown |
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.model pulldown d_pulldown |
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.include ../adder_common.inc |
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.END |
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@ -0,0 +1,31 @@ |
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Test bidi_bridge direction changes and automatic bridging |
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Va a 0 pulse 0 3 0 1u 1.2u 500u 1m |
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Vb b 0 pulse 0 3 0 1u 1.2u 100u 200u |
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Vctl ctl 0 pulse 0 3 10m 1u 1u 10m 20m |
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Ainv ctl not_ctl invert |
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.model invert d_inverter |
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* Transmitter/receiver for an analogue bus line |
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.subckt driver in enable out bus |
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Atran in enable int tristate |
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Arec int out buffer |
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Rout int bus 20 // Make bus an analogue node, with bridge |
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.ends |
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.model buffer d_buffer |
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.model tristate d_tristate |
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Xa a ctl out_a bus driver |
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Xb b not_ctl out_b bus driver |
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Rload bus 0 1k |
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.control |
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save a out_a b out_b |
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tran 1m 40m |
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plot out_a |
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listing e |
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.endc |
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.end |
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