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code merge for bsim3 version 0 and 1

pre-master-46
dwarning 15 years ago
parent
commit
4b74852dce
  1. 6
      ChangeLog
  2. 42
      DEVICES
  3. 2
      configure.ac
  4. 2
      src/Makefile.am
  5. 6
      src/spicelib/devices/bsim3v0/b3v0.c
  6. 4
      src/spicelib/devices/bsim3v0/b3v0ld.c
  7. 6
      src/spicelib/devices/bsim3v0/b3v0pzld.c
  8. 6
      src/spicelib/devices/bsim3v0/b3v0temp.c
  9. 6
      src/spicelib/devices/bsim3v1/b3v1.c
  10. 114
      src/spicelib/devices/bsim3v1/b3v1ask.c
  11. 42
      src/spicelib/devices/bsim3v1/b3v1ld.c
  12. 41
      src/spicelib/devices/bsim3v1/b3v1mpar.c
  13. 34
      src/spicelib/devices/bsim3v1/b3v1noi.c
  14. 6
      src/spicelib/devices/bsim3v1/b3v1par.c
  15. 75
      src/spicelib/devices/bsim3v1/b3v1set.c
  16. 5
      src/spicelib/devices/bsim3v1/bsim3v1def.h
  17. 4
      src/spicelib/devices/bsim3v1/bsim3v1init.c
  18. 4
      src/spicelib/devices/dev.c
  19. 10
      src/spicelib/parser/inp2m.c
  20. 6
      src/spicelib/parser/inpdomod.c

6
ChangeLog

@ -1,3 +1,9 @@
2011-04-12 Dietmar Warning
* devices: merged bsim3v1a code with bsim3v0
* devices: merged bsim3v1s code with bsim3v1
* update this situation to DEVICES, configure.ac, src/Makefile.am,
spicelib/parser/inpdomod.c, inp2m.c, devices/dev.c
2011-04-09 Robert Larice 2011-04-09 Robert Larice
* src/frontend/plotting/x11.c : * src/frontend/plotting/x11.c :
bugfix, segfault when closing a plot window bugfix, segfault when closing a plot window

42
DEVICES

@ -47,13 +47,12 @@ Table of contents
11.5 MOS9 - Level 9 MOS model 11.5 MOS9 - Level 9 MOS model
11.6 BSIM1 - BSIM model level 1 11.6 BSIM1 - BSIM model level 1
11.7 BSIM2 - BSIM model level 2 11.7 BSIM2 - BSIM model level 2
11.8 BSIM3v0 - BSIM model level 3
11.9 BSIM3v1 - BSIM model level 3
11.10 BSIM3v1 - BSIM model level 3
11.11 BSIM3v1 - BSIM model level 3
11.12 BSIM3 - BSIM model level 3
11.13 BSIM4 - BSIM model level 4
11.14 HiSIM - Hiroshima-university STARC IGFET Model
11.8 BSIM3 - BSIM model level 3 vers. 0
11.9 BSIM3 - BSIM model level 3 vers. 1
11.10 BSIM3 - BSIM model level 3 vers. 2
11.11 BSIM3 - BSIM model level 3 vers. 3
11.12 BSIM4 - BSIM model level 4
11.13 HiSIM - Hiroshima-University STARC IGFET Model
12. SOI devices 12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices) 12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model) 12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
@ -609,40 +608,21 @@ will be updated every time the device specific code is altered or changed to ref
Dir: devices/bsim3v0 Dir: devices/bsim3v0
Status: TO BE TESTED AND IMPROVED Status: TO BE TESTED AND IMPROVED
11.9 BSIM3v1 - BSIM model level 3 11.9 BSIM3v1 - BSIM model level 3
Ver: 3.1 Ver: 3.1
Class: M Class: M
Level: 8 & 49, version = 3.1 Level: 8 & 49, version = 3.1
Dir: devices/bsim3v1 Dir: devices/bsim3v1
Status: TO BE TESTED
11.10 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1a
Dir: devices/bsim3v1a
Status: TO BE TESTED AND IMPROVED Status: TO BE TESTED AND IMPROVED
This is the BSIM3v3.1 model modified by Alan Gillespie.
11.11 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1s
Dir: devices/bsim3v1s
Status: TO BE TESTED AND IMPROVED
This is the BSIM3v3.1 model modified by Serban Popescu. This is the BSIM3v3.1 model modified by Serban Popescu.
This is level 49 model. It is an implementation that supports This is level 49 model. It is an implementation that supports
"HDIF" and "M" parameters. "HDIF" and "M" parameters.
11.12 BSIM3 - BSIM model level 3
11.10 BSIM3 - BSIM model level 3
Ver: 3.2.4 Ver: 3.2.4
Class: M Class: M
@ -663,7 +643,7 @@ will be updated every time the device specific code is altered or changed to ref
- NodesetFix - NodesetFix
11.12 BSIM3 - BSIM model level 3
11.11 BSIM3 - BSIM model level 3
Ver: 3.3.0 Ver: 3.3.0
Class: M Class: M
@ -685,7 +665,7 @@ will be updated every time the device specific code is altered or changed to ref
- Support for Multi-core processors using OpenMP - Support for Multi-core processors using OpenMP
11.13 BSIM4 - BSIM model level 4
11.12 BSIM4 - BSIM model level 4
Ver: 4.2.0 - 4.6.5 Ver: 4.2.0 - 4.6.5
Class: M Class: M
@ -704,7 +684,7 @@ will be updated every time the device specific code is altered or changed to ref
- Support for Multi-core processors using OpenMP - Support for Multi-core processors using OpenMP
11.14 HiSIM - Hiroshima-university STARC IGFET Model
11.13 HiSIM - Hiroshima-university STARC IGFET Model
Ver: 1.2.0 Ver: 1.2.0
Class: M Class: M

2
configure.ac

@ -1013,8 +1013,6 @@ AC_CONFIG_FILES([Makefile
src/spicelib/devices/bsim3/Makefile src/spicelib/devices/bsim3/Makefile
src/spicelib/devices/bsim3v0/Makefile src/spicelib/devices/bsim3v0/Makefile
src/spicelib/devices/bsim3v1/Makefile src/spicelib/devices/bsim3v1/Makefile
src/spicelib/devices/bsim3v1a/Makefile
src/spicelib/devices/bsim3v1s/Makefile
src/spicelib/devices/bsim3v32/Makefile src/spicelib/devices/bsim3v32/Makefile
src/spicelib/devices/bsim4/Makefile src/spicelib/devices/bsim4/Makefile
src/spicelib/devices/bsim4v2/Makefile src/spicelib/devices/bsim4v2/Makefile

2
src/Makefile.am

@ -46,8 +46,6 @@ DYNAMIC_DEVICELIBS = \
spicelib/devices/bsim3/libbsim3.la \ spicelib/devices/bsim3/libbsim3.la \
spicelib/devices/bsim3v0/libbsim3v0.la \ spicelib/devices/bsim3v0/libbsim3v0.la \
spicelib/devices/bsim3v1/libbsim3v1.la \ spicelib/devices/bsim3v1/libbsim3v1.la \
spicelib/devices/bsim3v1s/libbsim3v1s.la \
spicelib/devices/bsim3v1a/libbsim3v1a.la \
spicelib/devices/bsim3v32/libbsim3v32.la \ spicelib/devices/bsim3v32/libbsim3v32.la \
spicelib/devices/bsim4/libbsim4.la \ spicelib/devices/bsim4/libbsim4.la \
spicelib/devices/bsim4v2/libbsim4v2.la \ spicelib/devices/bsim4v2/libbsim4v2.la \

6
src/spicelib/devices/bsim3v0/b3v0.c

@ -1,7 +1,7 @@
/********** /**********
Copyright 1990 Regents of the University of California. All rights reserved. Copyright 1990 Regents of the University of California. All rights reserved.
Author: 1995 Min-Chie Jeng and Mansun Chan. Author: 1995 Min-Chie Jeng and Mansun Chan.
File: b3v0.c
File: b3.c
**********/ **********/
#include "ngspice.h" #include "ngspice.h"
@ -31,6 +31,10 @@ OP( "id", BSIM3v0_CD, IF_REAL, "Ids"),
OP( "vbs", BSIM3v0_VBS, IF_REAL, "Vbs"), OP( "vbs", BSIM3v0_VBS, IF_REAL, "Vbs"),
OP( "vgs", BSIM3v0_VGS, IF_REAL, "Vgs"), OP( "vgs", BSIM3v0_VGS, IF_REAL, "Vgs"),
OP( "vds", BSIM3v0_VDS, IF_REAL, "Vds"), OP( "vds", BSIM3v0_VDS, IF_REAL, "Vds"),
OP( "gbd", BSIM3v0_GBD, IF_REAL, "Gbd"),
OP( "gbs", BSIM3v0_GBS, IF_REAL, "Gbs"),
OP( "ibd", BSIM3v0_CBD, IF_REAL, "Ibd"),
OP( "ibs", BSIM3v0_CBS, IF_REAL, "Ibs"),
}; };
IFparm BSIM3v0mPTable[] = { /* model parameters */ IFparm BSIM3v0mPTable[] = { /* model parameters */

4
src/spicelib/devices/bsim3v0/b3v0ld.c

@ -1,7 +1,7 @@
/********** /**********
Copyright 1990 Regents of the University of California. All rights reserved. Copyright 1990 Regents of the University of California. All rights reserved.
Author: 1991 JianHui Huang and Min-Chie Jeng. Author: 1991 JianHui Huang and Min-Chie Jeng.
File: b3v0ld.c 1/3/92
File: b3ld.c 1/3/92
Modified by Mansun Chan (1995) Modified by Mansun Chan (1995)
**********/ **********/
@ -117,7 +117,7 @@ double dQac0_dVg, dQac0_dVd, dQac0_dVb, dQsub0_dVg, dQsub0_dVd, dQsub0_dVb;
struct bsim3v0SizeDependParam *pParam; struct bsim3v0SizeDependParam *pParam;
int ByPass, Check, ChargeComputationNeeded = 0, error; int ByPass, Check, ChargeComputationNeeded = 0, error;
double m = 0.0;
double m = 1.0;
for (; model != NULL; model = model->BSIM3v0nextModel) for (; model != NULL; model = model->BSIM3v0nextModel)
{ for (here = model->BSIM3v0instances; here != NULL; { for (here = model->BSIM3v0instances; here != NULL;

6
src/spicelib/devices/bsim3v0/b3v0pzld.c

@ -1,7 +1,7 @@
/********** /**********
Copyright 1990 Regents of the University of California. All rights reserved. Copyright 1990 Regents of the University of California. All rights reserved.
Author: 1995 Min-Chie Jeng and Mansun Chan. Author: 1995 Min-Chie Jeng and Mansun Chan.
File: b3v0pzld.c
File: b3pzld.c
**********/ **********/
#include "ngspice.h" #include "ngspice.h"
@ -14,8 +14,8 @@ File: b3v0pzld.c
int int
BSIM3v0pzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s) BSIM3v0pzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s)
{ {
register BSIM3v0model *model = (BSIM3v0model*)inModel;
register BSIM3v0instance *here;
BSIM3v0model *model = (BSIM3v0model*)inModel;
BSIM3v0instance *here;
double xcggb, xcgdb, xcgsb, xcbgb, xcbdb, xcbsb, xcddb, xcssb, xcdgb; double xcggb, xcgdb, xcgsb, xcbgb, xcbdb, xcbsb, xcddb, xcssb, xcdgb;
double gdpr, gspr, gds, gbd, gbs, capbd, capbs, xcsgb, xcdsb, xcsdb; double gdpr, gspr, gds, gbd, gbs, capbd, capbs, xcsgb, xcdsb, xcsdb;
double cggb, cgdb, cgsb, cbgb, cbdb, cbsb, cddb, cdgb, cdsb; double cggb, cgdb, cgsb, cbgb, cbdb, cbsb, cddb, cdgb, cdsb;

6
src/spicelib/devices/bsim3v0/b3v0temp.c

@ -1,7 +1,7 @@
/*********** /***********
Copyright 1990 Regents of the University of California. All rights reserved. Copyright 1990 Regents of the University of California. All rights reserved.
Author: 1995 Min-Chie Jeng and Mansun Chan. Author: 1995 Min-Chie Jeng and Mansun Chan.
File: b3v0temp.c
File: b3temp.c
**********/ **********/
/* Lmin, Lmax, Wmin, Wmax */ /* Lmin, Lmax, Wmin, Wmax */
@ -28,8 +28,8 @@ File: b3v0temp.c
int int
BSIM3v0temp(GENmodel *inModel, CKTcircuit *ckt) BSIM3v0temp(GENmodel *inModel, CKTcircuit *ckt)
{ {
register BSIM3v0model *model = (BSIM3v0model*) inModel;
register BSIM3v0instance *here;
BSIM3v0model *model = (BSIM3v0model*) inModel;
BSIM3v0instance *here;
struct bsim3v0SizeDependParam *pSizeDependParamKnot, *pLastKnot, *pParam = NULL; struct bsim3v0SizeDependParam *pSizeDependParamKnot, *pLastKnot, *pParam = NULL;
double tmp1, tmp2, Eg, ni, T0, T1, T2, T3, Ldrn, Wdrn; double tmp1, tmp2, Eg, ni, T0, T1, T2, T3, Ldrn, Wdrn;
double Temp, TRatio, Inv_L, Inv_W, Inv_LW, Vtm0, Tnom; double Temp, TRatio, Inv_L, Inv_W, Inv_LW, Vtm0, Tnom;

6
src/spicelib/devices/bsim3v1/b3v1.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1.c
* File: b3.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
@ -427,6 +427,8 @@ IOP( "kf", BSIM3v1_MOD_KF, IF_REAL, "Flicker noise coefficient"),
IP( "nmos", BSIM3v1_MOD_NMOS, IF_FLAG, "Flag to indicate NMOS"), IP( "nmos", BSIM3v1_MOD_NMOS, IF_FLAG, "Flag to indicate NMOS"),
IP( "pmos", BSIM3v1_MOD_PMOS, IF_FLAG, "Flag to indicate PMOS"), IP( "pmos", BSIM3v1_MOD_PMOS, IF_FLAG, "Flag to indicate PMOS"),
/* serban */
IOP( "hdif", BSIM3v1_MOD_HDIF, IF_REAL, "S/D junction extension (HSPICE style)"),
}; };
char *BSIM3v1names[] = { char *BSIM3v1names[] = {

114
src/spicelib/devices/bsim3v1/b3v1ask.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1ask.c
* File: b3ask.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -30,198 +30,198 @@ BSIM3v1ask (CKTcircuit * ckt, GENinstance * inst, int which, IFvalue * value,
{ {
case BSIM3v1_L: case BSIM3v1_L:
value->rValue = here->BSIM3v1l; value->rValue = here->BSIM3v1l;
return (OK);
return(OK);
case BSIM3v1_W: case BSIM3v1_W:
value->rValue = here->BSIM3v1w; value->rValue = here->BSIM3v1w;
return (OK);
return(OK);
case BSIM3v1_M: case BSIM3v1_M:
value->rValue = here->BSIM3v1m; value->rValue = here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_AS: case BSIM3v1_AS:
value->rValue = here->BSIM3v1sourceArea; value->rValue = here->BSIM3v1sourceArea;
return (OK);
return(OK);
case BSIM3v1_AD: case BSIM3v1_AD:
value->rValue = here->BSIM3v1drainArea; value->rValue = here->BSIM3v1drainArea;
return (OK);
return(OK);
case BSIM3v1_PS: case BSIM3v1_PS:
value->rValue = here->BSIM3v1sourcePerimeter; value->rValue = here->BSIM3v1sourcePerimeter;
return (OK);
return(OK);
case BSIM3v1_PD: case BSIM3v1_PD:
value->rValue = here->BSIM3v1drainPerimeter; value->rValue = here->BSIM3v1drainPerimeter;
return (OK);
return(OK);
case BSIM3v1_NRS: case BSIM3v1_NRS:
value->rValue = here->BSIM3v1sourceSquares; value->rValue = here->BSIM3v1sourceSquares;
return (OK);
return(OK);
case BSIM3v1_NRD: case BSIM3v1_NRD:
value->rValue = here->BSIM3v1drainSquares; value->rValue = here->BSIM3v1drainSquares;
return (OK);
return(OK);
case BSIM3v1_OFF: case BSIM3v1_OFF:
value->rValue = here->BSIM3v1off; value->rValue = here->BSIM3v1off;
return (OK);
return(OK);
case BSIM3v1_NQSMOD: case BSIM3v1_NQSMOD:
value->iValue = here->BSIM3v1nqsMod; value->iValue = here->BSIM3v1nqsMod;
return (OK);
return(OK);
case BSIM3v1_IC_VBS: case BSIM3v1_IC_VBS:
value->rValue = here->BSIM3v1icVBS; value->rValue = here->BSIM3v1icVBS;
return (OK);
return(OK);
case BSIM3v1_IC_VDS: case BSIM3v1_IC_VDS:
value->rValue = here->BSIM3v1icVDS; value->rValue = here->BSIM3v1icVDS;
return (OK);
return(OK);
case BSIM3v1_IC_VGS: case BSIM3v1_IC_VGS:
value->rValue = here->BSIM3v1icVGS; value->rValue = here->BSIM3v1icVGS;
return (OK);
return(OK);
case BSIM3v1_DNODE: case BSIM3v1_DNODE:
value->iValue = here->BSIM3v1dNode; value->iValue = here->BSIM3v1dNode;
return (OK);
return(OK);
case BSIM3v1_GNODE: case BSIM3v1_GNODE:
value->iValue = here->BSIM3v1gNode; value->iValue = here->BSIM3v1gNode;
return (OK);
return(OK);
case BSIM3v1_SNODE: case BSIM3v1_SNODE:
value->iValue = here->BSIM3v1sNode; value->iValue = here->BSIM3v1sNode;
return (OK);
return(OK);
case BSIM3v1_BNODE: case BSIM3v1_BNODE:
value->iValue = here->BSIM3v1bNode; value->iValue = here->BSIM3v1bNode;
return (OK);
return(OK);
case BSIM3v1_DNODEPRIME: case BSIM3v1_DNODEPRIME:
value->iValue = here->BSIM3v1dNodePrime; value->iValue = here->BSIM3v1dNodePrime;
return (OK);
return(OK);
case BSIM3v1_SNODEPRIME: case BSIM3v1_SNODEPRIME:
value->iValue = here->BSIM3v1sNodePrime; value->iValue = here->BSIM3v1sNodePrime;
return (OK);
return(OK);
case BSIM3v1_SOURCECONDUCT: case BSIM3v1_SOURCECONDUCT:
value->rValue = here->BSIM3v1sourceConductance; value->rValue = here->BSIM3v1sourceConductance;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_DRAINCONDUCT: case BSIM3v1_DRAINCONDUCT:
value->rValue = here->BSIM3v1drainConductance; value->rValue = here->BSIM3v1drainConductance;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_VBD: case BSIM3v1_VBD:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vbd); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vbd);
return (OK);
return(OK);
case BSIM3v1_VBS: case BSIM3v1_VBS:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vbs); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vbs);
return (OK);
return(OK);
case BSIM3v1_VGS: case BSIM3v1_VGS:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vgs); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vgs);
return (OK);
return(OK);
case BSIM3v1_VDS: case BSIM3v1_VDS:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vds); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1vds);
return (OK);
return(OK);
case BSIM3v1_CD: case BSIM3v1_CD:
value->rValue = here->BSIM3v1cd; value->rValue = here->BSIM3v1cd;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CBS: case BSIM3v1_CBS:
value->rValue = here->BSIM3v1cbs; value->rValue = here->BSIM3v1cbs;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CBD: case BSIM3v1_CBD:
value->rValue = here->BSIM3v1cbd; value->rValue = here->BSIM3v1cbd;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_GM: case BSIM3v1_GM:
value->rValue = here->BSIM3v1gm; value->rValue = here->BSIM3v1gm;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_GDS: case BSIM3v1_GDS:
value->rValue = here->BSIM3v1gds; value->rValue = here->BSIM3v1gds;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_GMBS: case BSIM3v1_GMBS:
value->rValue = here->BSIM3v1gmbs; value->rValue = here->BSIM3v1gmbs;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_GBD: case BSIM3v1_GBD:
value->rValue = here->BSIM3v1gbd; value->rValue = here->BSIM3v1gbd;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_GBS: case BSIM3v1_GBS:
value->rValue = here->BSIM3v1gbs; value->rValue = here->BSIM3v1gbs;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_QB: case BSIM3v1_QB:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qb); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qb);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CQB: case BSIM3v1_CQB:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqb); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqb);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_QG: case BSIM3v1_QG:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qg); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qg);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CQG: case BSIM3v1_CQG:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqg); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqg);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_QD: case BSIM3v1_QD:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qd); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qd);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CQD: case BSIM3v1_CQD:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqd); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1cqd);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CGG: case BSIM3v1_CGG:
value->rValue = here->BSIM3v1cggb; value->rValue = here->BSIM3v1cggb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CGD: case BSIM3v1_CGD:
value->rValue = here->BSIM3v1cgdb; value->rValue = here->BSIM3v1cgdb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CGS: case BSIM3v1_CGS:
value->rValue = here->BSIM3v1cgsb; value->rValue = here->BSIM3v1cgsb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CDG: case BSIM3v1_CDG:
value->rValue = here->BSIM3v1cdgb; value->rValue = here->BSIM3v1cdgb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CDD: case BSIM3v1_CDD:
value->rValue = here->BSIM3v1cddb; value->rValue = here->BSIM3v1cddb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CDS: case BSIM3v1_CDS:
value->rValue = here->BSIM3v1cdsb; value->rValue = here->BSIM3v1cdsb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CBG: case BSIM3v1_CBG:
value->rValue = here->BSIM3v1cbgb; value->rValue = here->BSIM3v1cbgb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CBDB: case BSIM3v1_CBDB:
value->rValue = here->BSIM3v1cbdb; value->rValue = here->BSIM3v1cbdb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CBSB: case BSIM3v1_CBSB:
value->rValue = here->BSIM3v1cbsb; value->rValue = here->BSIM3v1cbsb;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CAPBD: case BSIM3v1_CAPBD:
value->rValue = here->BSIM3v1capbd; value->rValue = here->BSIM3v1capbd;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_CAPBS: case BSIM3v1_CAPBS:
value->rValue = here->BSIM3v1capbs; value->rValue = here->BSIM3v1capbs;
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_VON: case BSIM3v1_VON:
value->rValue = here->BSIM3v1von; value->rValue = here->BSIM3v1von;
return (OK);
return(OK);
case BSIM3v1_VDSAT: case BSIM3v1_VDSAT:
value->rValue = here->BSIM3v1vdsat; value->rValue = here->BSIM3v1vdsat;
return (OK);
return(OK);
case BSIM3v1_QBS: case BSIM3v1_QBS:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qbs); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qbs);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
case BSIM3v1_QBD: case BSIM3v1_QBD:
value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qbd); value->rValue = *(ckt->CKTstate0 + here->BSIM3v1qbd);
value->rValue *= here->BSIM3v1m; value->rValue *= here->BSIM3v1m;
return (OK);
return(OK);
default: default:
return (E_BADPARM); return (E_BADPARM);
} }

42
src/spicelib/devices/bsim3v1/b3v1ld.c

@ -1,6 +1,6 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1ld.c
* File: b3ld.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Mansun Chan (1995) * Modified by Mansun Chan (1995)
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
@ -8,7 +8,7 @@
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -120,7 +120,7 @@ double Csg, Csd, Csb, Cbg, Cbd, Cbb;
double Cgg1, Cgb1, Cgd1, Cbg1, Cbb1, Cbd1, Qac0, Qsub0; double Cgg1, Cgb1, Cgd1, Cbg1, Cbb1, Cbd1, Qac0, Qsub0;
double dQac0_dVg, dQac0_dVd, dQac0_dVb, dQsub0_dVg, dQsub0_dVd, dQsub0_dVb; double dQac0_dVg, dQac0_dVd, dQac0_dVb, dQsub0_dVg, dQsub0_dVd, dQsub0_dVb;
double m = 0.0;
double m = 1.0;
struct bsim3v1SizeDependParam *pParam; struct bsim3v1SizeDependParam *pParam;
int ByPass, Check, ChargeComputationNeeded = 0, error; int ByPass, Check, ChargeComputationNeeded = 0, error;
@ -133,7 +133,6 @@ for (; model != NULL; model = model->BSIM3v1nextModel)
if (here->BSIM3v1owner != ARCHme) if (here->BSIM3v1owner != ARCHme)
continue; continue;
Check = 1; Check = 1;
ByPass = 0; ByPass = 0;
pParam = here->pParam; pParam = here->pParam;
@ -2018,8 +2017,25 @@ finished: /* returning Values to Calling Routine */
*/ */
if ((here->BSIM3v1off == 0) || (!(ckt->CKTmode & MODEINITFIX))) if ((here->BSIM3v1off == 0) || (!(ckt->CKTmode & MODEINITFIX)))
{ if (Check == 1) { if (Check == 1)
{
ckt->CKTnoncon++;
{ ckt->CKTnoncon++;
#ifndef NEWCONV
}
else
{ tol = ckt->CKTreltol * MAX(FABS(cdhat), FABS(here->BSIM3v1cd))
+ ckt->CKTabstol;
if (FABS(cdhat - here->BSIM3v1cd) >= tol)
{ ckt->CKTnoncon++;
}
else
{ tol = ckt->CKTreltol * MAX(FABS(cbhat),
FABS(here->BSIM3v1cbs + here->BSIM3v1cbd))
+ ckt->CKTabstol;
if (FABS(cbhat - (here->BSIM3v1cbs + here->BSIM3v1cbd))
> tol)
{ ckt->CKTnoncon++;
}
}
#endif /* NEWCONV */
} }
} }
*(ckt->CKTstate0 + here->BSIM3v1vbs) = vbs; *(ckt->CKTstate0 + here->BSIM3v1vbs) = vbs;
@ -2354,7 +2370,7 @@ line900:
if (model->BSIM3v1type > 0) if (model->BSIM3v1type > 0)
{ ceqbs += (here->BSIM3v1cbs - (here->BSIM3v1gbs - ckt->CKTgmin) * vbs); { ceqbs += (here->BSIM3v1cbs - (here->BSIM3v1gbs - ckt->CKTgmin) * vbs);
ceqbd += (here->BSIM3v1cbd - (here->BSIM3v1gbd - ckt->CKTgmin ) * vbd);
ceqbd += (here->BSIM3v1cbd - (here->BSIM3v1gbd - ckt->CKTgmin) * vbd);
ceqqg = ceqqg; ceqqg = ceqqg;
ceqqb = ceqqb; ceqqb = ceqqb;
ceqqd = ceqqd; ceqqd = ceqqd;
@ -2390,15 +2406,12 @@ line900:
- gcbgb - gcbdb - gcbsb) - here->BSIM3v1gbbs)); - gcbgb - gcbdb - gcbsb) - here->BSIM3v1gbbs));
(*(here->BSIM3v1DPdpPtr) += m * ((here->BSIM3v1drainConductance (*(here->BSIM3v1DPdpPtr) += m * ((here->BSIM3v1drainConductance
+ here->BSIM3v1gds + here->BSIM3v1gbd + here->BSIM3v1gds + here->BSIM3v1gbd
+ RevSum + gcddb) + dxpart * here->BSIM3v1gtd +
gbdpdp));
+ RevSum + gcddb) + dxpart * here->BSIM3v1gtd + gbdpdp));
(*(here->BSIM3v1SPspPtr) += m * ((here->BSIM3v1sourceConductance (*(here->BSIM3v1SPspPtr) += m * ((here->BSIM3v1sourceConductance
+ here->BSIM3v1gds + here->BSIM3v1gbs + here->BSIM3v1gds + here->BSIM3v1gbs
+ FwdSum + gcssb) + sxpart * here->BSIM3v1gts +
gbspsp));
+ FwdSum + gcssb) + sxpart * here->BSIM3v1gts + gbspsp));
(*(here->BSIM3v1DdpPtr) -= m * here->BSIM3v1drainConductance); (*(here->BSIM3v1DdpPtr) -= m * here->BSIM3v1drainConductance);
(*(here->BSIM3v1GbPtr) -= m * (gcggb + gcgdb + gcgsb +
here->BSIM3v1gtb));
(*(here->BSIM3v1GbPtr) -= m * (gcggb + gcgdb + gcgsb + here->BSIM3v1gtb));
(*(here->BSIM3v1GdpPtr) += m * (gcgdb - here->BSIM3v1gtd)); (*(here->BSIM3v1GdpPtr) += m * (gcgdb - here->BSIM3v1gtd));
(*(here->BSIM3v1GspPtr) += m * (gcgsb - here->BSIM3v1gts)); (*(here->BSIM3v1GspPtr) += m * (gcgsb - here->BSIM3v1gts));
(*(here->BSIM3v1SspPtr) -= m * here->BSIM3v1sourceConductance); (*(here->BSIM3v1SspPtr) -= m * here->BSIM3v1sourceConductance);
@ -2418,8 +2431,7 @@ line900:
(*(here->BSIM3v1SPbPtr) -= m * ((here->BSIM3v1gbs + Gmbs + gcsgb + gcsdb (*(here->BSIM3v1SPbPtr) -= m * ((here->BSIM3v1gbs + Gmbs + gcsgb + gcsdb
+ gcssb - sxpart * here->BSIM3v1gtb) - gbspb)); + gcssb - sxpart * here->BSIM3v1gtb) - gbspb));
(*(here->BSIM3v1SPdpPtr) -= m * ((here->BSIM3v1gds + RevSum - gcsdb (*(here->BSIM3v1SPdpPtr) -= m * ((here->BSIM3v1gds + RevSum - gcsdb
- sxpart * here->BSIM3v1gtd - here->BSIM3v1gbd)
- gbspdp));
- sxpart * here->BSIM3v1gtd - here->BSIM3v1gbd) - gbspdp));
*(here->BSIM3v1QqPtr) += m * ((gqdef + here->BSIM3v1gtau)); *(here->BSIM3v1QqPtr) += m * ((gqdef + here->BSIM3v1gtau));

41
src/spicelib/devices/bsim3v1/b3v1mpar.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1mpar.c
* File: b3mpar.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -118,14 +118,14 @@ BSIM3v1mParam(int param, IFvalue *value, GENmodel *inMod)
case BSIM3v1_MOD_NPEAK: case BSIM3v1_MOD_NPEAK:
mod->BSIM3v1npeak = value->rValue; mod->BSIM3v1npeak = value->rValue;
mod->BSIM3v1npeakGiven = TRUE; mod->BSIM3v1npeakGiven = TRUE;
if (mod->BSIM3v1npeak > 1.0e20)
mod->BSIM3v1npeak *= 1.0e-6;
if (mod->BSIM3v1npeak > 1.0e20)
mod->BSIM3v1npeak *= 1.0e-6;
break; break;
case BSIM3v1_MOD_NGATE: case BSIM3v1_MOD_NGATE:
mod->BSIM3v1ngate = value->rValue; mod->BSIM3v1ngate = value->rValue;
mod->BSIM3v1ngateGiven = TRUE; mod->BSIM3v1ngateGiven = TRUE;
if (mod->BSIM3v1ngate > 1.0e23)
mod->BSIM3v1ngate *= 1.0e-6;
if (mod->BSIM3v1ngate > 1.0e23)
mod->BSIM3v1ngate *= 1.0e-6;
break; break;
case BSIM3v1_MOD_GAMMA1: case BSIM3v1_MOD_GAMMA1:
mod->BSIM3v1gamma1 = value->rValue; mod->BSIM3v1gamma1 = value->rValue;
@ -445,14 +445,14 @@ BSIM3v1mParam(int param, IFvalue *value, GENmodel *inMod)
case BSIM3v1_MOD_LNPEAK: case BSIM3v1_MOD_LNPEAK:
mod->BSIM3v1lnpeak = value->rValue; mod->BSIM3v1lnpeak = value->rValue;
mod->BSIM3v1lnpeakGiven = TRUE; mod->BSIM3v1lnpeakGiven = TRUE;
if (mod->BSIM3v1lnpeak > 1.0e20)
mod->BSIM3v1lnpeak *= 1.0e-6;
if (mod->BSIM3v1lnpeak > 1.0e20)
mod->BSIM3v1lnpeak *= 1.0e-6;
break; break;
case BSIM3v1_MOD_LNGATE: case BSIM3v1_MOD_LNGATE:
mod->BSIM3v1lngate = value->rValue; mod->BSIM3v1lngate = value->rValue;
mod->BSIM3v1lngateGiven = TRUE; mod->BSIM3v1lngateGiven = TRUE;
if (mod->BSIM3v1lngate > 1.0e23)
mod->BSIM3v1lngate *= 1.0e-6;
if (mod->BSIM3v1lngate > 1.0e23)
mod->BSIM3v1lngate *= 1.0e-6;
break; break;
case BSIM3v1_MOD_LGAMMA1: case BSIM3v1_MOD_LGAMMA1:
mod->BSIM3v1lgamma1 = value->rValue; mod->BSIM3v1lgamma1 = value->rValue;
@ -764,14 +764,14 @@ BSIM3v1mParam(int param, IFvalue *value, GENmodel *inMod)
case BSIM3v1_MOD_WNPEAK: case BSIM3v1_MOD_WNPEAK:
mod->BSIM3v1wnpeak = value->rValue; mod->BSIM3v1wnpeak = value->rValue;
mod->BSIM3v1wnpeakGiven = TRUE; mod->BSIM3v1wnpeakGiven = TRUE;
if (mod->BSIM3v1wnpeak > 1.0e20)
mod->BSIM3v1wnpeak *= 1.0e-6;
if (mod->BSIM3v1wnpeak > 1.0e20)
mod->BSIM3v1wnpeak *= 1.0e-6;
break; break;
case BSIM3v1_MOD_WNGATE: case BSIM3v1_MOD_WNGATE:
mod->BSIM3v1wngate = value->rValue; mod->BSIM3v1wngate = value->rValue;
mod->BSIM3v1wngateGiven = TRUE; mod->BSIM3v1wngateGiven = TRUE;
if (mod->BSIM3v1wngate > 1.0e23)
mod->BSIM3v1wngate *= 1.0e-6;
if (mod->BSIM3v1wngate > 1.0e23)
mod->BSIM3v1wngate *= 1.0e-6;
break; break;
case BSIM3v1_MOD_WGAMMA1: case BSIM3v1_MOD_WGAMMA1:
mod->BSIM3v1wgamma1 = value->rValue; mod->BSIM3v1wgamma1 = value->rValue;
@ -1083,14 +1083,14 @@ BSIM3v1mParam(int param, IFvalue *value, GENmodel *inMod)
case BSIM3v1_MOD_PNPEAK: case BSIM3v1_MOD_PNPEAK:
mod->BSIM3v1pnpeak = value->rValue; mod->BSIM3v1pnpeak = value->rValue;
mod->BSIM3v1pnpeakGiven = TRUE; mod->BSIM3v1pnpeakGiven = TRUE;
if (mod->BSIM3v1pnpeak > 1.0e20)
mod->BSIM3v1pnpeak *= 1.0e-6;
if (mod->BSIM3v1pnpeak > 1.0e20)
mod->BSIM3v1pnpeak *= 1.0e-6;
break; break;
case BSIM3v1_MOD_PNGATE: case BSIM3v1_MOD_PNGATE:
mod->BSIM3v1pngate = value->rValue; mod->BSIM3v1pngate = value->rValue;
mod->BSIM3v1pngateGiven = TRUE; mod->BSIM3v1pngateGiven = TRUE;
if (mod->BSIM3v1pngate > 1.0e23)
mod->BSIM3v1pngate *= 1.0e-6;
if (mod->BSIM3v1pngate > 1.0e23)
mod->BSIM3v1pngate *= 1.0e-6;
break; break;
case BSIM3v1_MOD_PGAMMA1: case BSIM3v1_MOD_PGAMMA1:
mod->BSIM3v1pgamma1 = value->rValue; mod->BSIM3v1pgamma1 = value->rValue;
@ -1519,6 +1519,11 @@ BSIM3v1mParam(int param, IFvalue *value, GENmodel *inMod)
mod->BSIM3v1typeGiven = TRUE; mod->BSIM3v1typeGiven = TRUE;
} }
break; break;
/* serban */
case BSIM3v1_MOD_HDIF :
mod->BSIM3v1hdif = value->rValue;
mod->BSIM3v1hdifGiven = TRUE;
break;
default: default:
return(E_BADPARM); return(E_BADPARM);
} }

34
src/spicelib/devices/bsim3v1/b3v1noi.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1noi.c
* File: b3noi.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -46,7 +46,7 @@
static double static double
StrongInversionNoiseEval_b3v1(double vgs, double vds, BSIM3v1model *model,
StrongInversionNoiseEval_b3(double vgs, double vds, BSIM3v1model *model,
BSIM3v1instance *here, double freq, double temp) BSIM3v1instance *here, double freq, double temp)
{ {
struct bsim3v1SizeDependParam *pParam; struct bsim3v1SizeDependParam *pParam;
@ -143,9 +143,11 @@ int i;
{ (void) sprintf(name, "onoise.%s%s", { (void) sprintf(name, "onoise.%s%s",
here->BSIM3v1name, here->BSIM3v1name,
BSIM3v1nNames[i]); BSIM3v1nNames[i]);
data->namelist = TREALLOC(IFuid, data->namelist, data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
data->namelist = TREALLOC(
IFuid, data->namelist,
data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
(*(SPfrontEnd->IFnewUid)) (ckt, (*(SPfrontEnd->IFnewUid)) (ckt,
&(data->namelist[data->numPlots++]), &(data->namelist[data->numPlots++]),
(IFuid) NULL, name, UID_OTHER, (IFuid) NULL, name, UID_OTHER,
@ -158,9 +160,11 @@ int i;
{ (void) sprintf(name, "onoise_total.%s%s", { (void) sprintf(name, "onoise_total.%s%s",
here->BSIM3v1name, here->BSIM3v1name,
BSIM3v1nNames[i]); BSIM3v1nNames[i]);
data->namelist = TREALLOC(IFuid, data->namelist, data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
data->namelist = TREALLOC(
IFuid, data->namelist,
data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
(*(SPfrontEnd->IFnewUid)) (ckt, (*(SPfrontEnd->IFnewUid)) (ckt,
&(data->namelist[data->numPlots++]), &(data->namelist[data->numPlots++]),
(IFuid) NULL, name, UID_OTHER, (IFuid) NULL, name, UID_OTHER,
@ -170,9 +174,11 @@ int i;
(void) sprintf(name, "inoise_total.%s%s", (void) sprintf(name, "inoise_total.%s%s",
here->BSIM3v1name, here->BSIM3v1name,
BSIM3v1nNames[i]); BSIM3v1nNames[i]);
data->namelist = TREALLOC(IFuid, data->namelist, data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
data->namelist = TREALLOC(
IFuid, data->namelist,
data->numPlots + 1);
if (!data->namelist)
return(E_NOMEM);
(*(SPfrontEnd->IFnewUid)) (ckt, (*(SPfrontEnd->IFnewUid)) (ckt,
&(data->namelist[data->numPlots++]), &(data->namelist[data->numPlots++]),
(IFuid) NULL, name, UID_OTHER, (IFuid) NULL, name, UID_OTHER,
@ -244,7 +250,7 @@ int i;
vgs = vgs + vds; vgs = vgs + vds;
} }
if (vgs >= here->BSIM3v1von + 0.1) if (vgs >= here->BSIM3v1von + 0.1)
{ Ssi = StrongInversionNoiseEval_b3v1(vgs,
{ Ssi = StrongInversionNoiseEval_b3(vgs,
vds, model, here, data->freq, vds, model, here, data->freq,
ckt->CKTtemp); ckt->CKTtemp);
noizDens[BSIM3v1FLNOIZ] *= Ssi; noizDens[BSIM3v1FLNOIZ] *= Ssi;
@ -259,7 +265,7 @@ int i;
* 4.0e36; * 4.0e36;
Swi = T10 / T11 * here->BSIM3v1cd * here->BSIM3v1m Swi = T10 / T11 * here->BSIM3v1cd * here->BSIM3v1m
* here->BSIM3v1cd * here->BSIM3v1m; * here->BSIM3v1cd * here->BSIM3v1m;
Slimit = StrongInversionNoiseEval_b3v1(
Slimit = StrongInversionNoiseEval_b3(
here->BSIM3v1von + 0.1, vds, model, here->BSIM3v1von + 0.1, vds, model,
here, data->freq, ckt->CKTtemp); here, data->freq, ckt->CKTtemp);
T1 = Swi + Slimit; T1 = Swi + Slimit;

6
src/spicelib/devices/bsim3v1/b3v1par.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1par.c
* File: b3par.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -37,7 +37,7 @@ BSIM3v1param(int param, IFvalue *value, GENinstance *inst, IFvalue *select)
here->BSIM3v1l = value->rValue*scale; here->BSIM3v1l = value->rValue*scale;
here->BSIM3v1lGiven = TRUE; here->BSIM3v1lGiven = TRUE;
break; break;
case BSIM3v1_M:
case BSIM3v1_M:
here->BSIM3v1m = value->rValue; here->BSIM3v1m = value->rValue;
here->BSIM3v1mGiven = TRUE; here->BSIM3v1mGiven = TRUE;
break; break;

75
src/spicelib/devices/bsim3v1/b3v1set.c

@ -1,13 +1,13 @@
/********** /**********
* Copyright 1990 Regents of the University of California. All rights reserved. * Copyright 1990 Regents of the University of California. All rights reserved.
* File: b3v1set.c
* File: b3set.c
* Author: 1995 Min-Chie Jeng and Mansun Chan. * Author: 1995 Min-Chie Jeng and Mansun Chan.
* Modified by Paolo Nenzi 2002 * Modified by Paolo Nenzi 2002
**********/ **********/
/* /*
* Release Notes: * Release Notes:
* BSIM3v3.1, Released by yuhua 96/12/08
* BSIM3v1v3.1, Released by yuhua 96/12/08
*/ */
#include "ngspice.h" #include "ngspice.h"
@ -777,21 +777,40 @@ IFuid tmpName;
/* loop through all the instances of the model */ /* loop through all the instances of the model */
for (here = model->BSIM3v1instances; here != NULL ; for (here = model->BSIM3v1instances; here != NULL ;
here=here->BSIM3v1nextInstance) here=here->BSIM3v1nextInstance)
{
if (here->BSIM3v1owner == ARCHme)
{
if (here->BSIM3v1owner == ARCHme)
{ {
/* allocate a chunk of the state vector */
/* allocate a chunk of the state vector */
here->BSIM3v1states = *states; here->BSIM3v1states = *states;
*states += BSIM3v1numStates; *states += BSIM3v1numStates;
}
}
/* perform the parameter defaulting */ /* perform the parameter defaulting */
if(here->BSIM3v1m == 0.0)
here->BSIM3v1m = 1.0;
if (!here->BSIM3v1wGiven)
here->BSIM3v1w = 5e-6;
if (!here->BSIM3v1drainAreaGiven) if (!here->BSIM3v1drainAreaGiven)
here->BSIM3v1drainArea = 0.0;
{
if(model->BSIM3v1hdifGiven)
here->BSIM3v1drainArea = here->BSIM3v1w * 2 * model->BSIM3v1hdif;
else
here->BSIM3v1drainArea = 0.0;
}
if (!here->BSIM3v1drainPerimeterGiven) if (!here->BSIM3v1drainPerimeterGiven)
here->BSIM3v1drainPerimeter = 0.0;
{
if(model->BSIM3v1hdifGiven)
here->BSIM3v1drainPerimeter =
2 * here->BSIM3v1w + 4 * model->BSIM3v1hdif;
else
here->BSIM3v1drainPerimeter = 0.0;
}
if (!here->BSIM3v1drainSquaresGiven) if (!here->BSIM3v1drainSquaresGiven)
here->BSIM3v1drainSquares = 1.0; here->BSIM3v1drainSquares = 1.0;
if (!here->BSIM3v1icVBSGiven) if (!here->BSIM3v1icVBSGiven)
here->BSIM3v1icVBS = 0; here->BSIM3v1icVBS = 0;
if (!here->BSIM3v1icVDSGiven) if (!here->BSIM3v1icVDSGiven)
@ -801,11 +820,25 @@ IFuid tmpName;
if (!here->BSIM3v1lGiven) if (!here->BSIM3v1lGiven)
here->BSIM3v1l = 5e-6; here->BSIM3v1l = 5e-6;
if (!here->BSIM3v1sourceAreaGiven) if (!here->BSIM3v1sourceAreaGiven)
here->BSIM3v1sourceArea = 0;
{
if(model->BSIM3v1hdifGiven)
here->BSIM3v1sourceArea = here->BSIM3v1w * 2 * model->BSIM3v1hdif;
else
here->BSIM3v1sourceArea = 0.0;
}
if (!here->BSIM3v1sourcePerimeterGiven) if (!here->BSIM3v1sourcePerimeterGiven)
here->BSIM3v1sourcePerimeter = 0;
{
if(model->BSIM3v1hdifGiven)
here->BSIM3v1sourcePerimeter =
2 * here->BSIM3v1w + 4 * model->BSIM3v1hdif;
else
here->BSIM3v1sourcePerimeter = 0.0;
}
if (!here->BSIM3v1sourceSquaresGiven) if (!here->BSIM3v1sourceSquaresGiven)
here->BSIM3v1sourceSquares = 1; here->BSIM3v1sourceSquares = 1;
if (!here->BSIM3v1wGiven) if (!here->BSIM3v1wGiven)
here->BSIM3v1w = 5e-6; here->BSIM3v1w = 5e-6;
@ -819,11 +852,11 @@ IFuid tmpName;
if ((model->BSIM3v1sheetResistance > 0.0) && if ((model->BSIM3v1sheetResistance > 0.0) &&
(here->BSIM3v1drainSquares > 0.0 ) && (here->BSIM3v1drainSquares > 0.0 ) &&
(here->BSIM3v1dNodePrime == 0)) (here->BSIM3v1dNodePrime == 0))
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"drain");
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"drain");
if(error) return(error); if(error) return(error);
here->BSIM3v1dNodePrime = tmp->number; here->BSIM3v1dNodePrime = tmp->number;
if (ckt->CKTcopyNodesets) {
if (ckt->CKTcopyNodesets) {
if (CKTinst2Node(ckt,here,1,&tmpNode,&tmpName)==OK) { if (CKTinst2Node(ckt,here,1,&tmpNode,&tmpName)==OK) {
if (tmpNode->nsGiven) { if (tmpNode->nsGiven) {
tmp->nodeset=tmpNode->nodeset; tmp->nodeset=tmpNode->nodeset;
@ -832,16 +865,16 @@ IFuid tmpName;
} }
} }
}
else
{ here->BSIM3v1dNodePrime = here->BSIM3v1dNode;
}
else
{ here->BSIM3v1dNodePrime = here->BSIM3v1dNode;
} }
/* process source series resistance */ /* process source series resistance */
if ((model->BSIM3v1sheetResistance > 0.0) && if ((model->BSIM3v1sheetResistance > 0.0) &&
(here->BSIM3v1sourceSquares > 0.0 ) && (here->BSIM3v1sourceSquares > 0.0 ) &&
(here->BSIM3v1sNodePrime == 0)) (here->BSIM3v1sNodePrime == 0))
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"source");
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"source");
if(error) return(error); if(error) return(error);
here->BSIM3v1sNodePrime = tmp->number; here->BSIM3v1sNodePrime = tmp->number;
@ -855,19 +888,19 @@ IFuid tmpName;
} }
} }
else
{ here->BSIM3v1sNodePrime = here->BSIM3v1sNode;
else
{ here->BSIM3v1sNodePrime = here->BSIM3v1sNode;
} }
/* internal charge node */ /* internal charge node */
if ((here->BSIM3v1nqsMod) && (here->BSIM3v1qNode == 0)) if ((here->BSIM3v1nqsMod) && (here->BSIM3v1qNode == 0))
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"charge");
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v1name,"charge");
if(error) return(error); if(error) return(error);
here->BSIM3v1qNode = tmp->number; here->BSIM3v1qNode = tmp->number;
} }
else
{ here->BSIM3v1qNode = 0;
else
{ here->BSIM3v1qNode = 0;
} }
/* set Sparse Matrix Pointers */ /* set Sparse Matrix Pointers */

5
src/spicelib/devices/bsim3v1/bsim3v1def.h

@ -404,6 +404,8 @@ typedef struct sBSIM3v1model
double BSIM3v1b1; double BSIM3v1b1;
double BSIM3v1alpha0; double BSIM3v1alpha0;
double BSIM3v1beta0; double BSIM3v1beta0;
/* serban */
double BSIM3v1hdif;
/* CV model */ /* CV model */
double BSIM3v1elm; double BSIM3v1elm;
@ -805,6 +807,7 @@ typedef struct sBSIM3v1model
unsigned BSIM3v1b1Given :1; unsigned BSIM3v1b1Given :1;
unsigned BSIM3v1alpha0Given :1; unsigned BSIM3v1alpha0Given :1;
unsigned BSIM3v1beta0Given :1; unsigned BSIM3v1beta0Given :1;
unsigned BSIM3v1hdifGiven :1;
/* CV model */ /* CV model */
unsigned BSIM3v1elmGiven :1; unsigned BSIM3v1elmGiven :1;
@ -1236,6 +1239,8 @@ typedef struct sBSIM3v1model
#define BSIM3v1_MOD_VERSION 193 #define BSIM3v1_MOD_VERSION 193
#define BSIM3v1_MOD_VFBCV 194 #define BSIM3v1_MOD_VFBCV 194
#define BSIM3v1_MOD_HDIF 198
/* Length dependence */ /* Length dependence */
#define BSIM3v1_MOD_LCDSC 201 #define BSIM3v1_MOD_LCDSC 201
#define BSIM3v1_MOD_LCDSCB 202 #define BSIM3v1_MOD_LCDSCB 202

4
src/spicelib/devices/bsim3v1/bsim3v1init.c

@ -6,7 +6,7 @@
#include "bsim3v1ext.h" #include "bsim3v1ext.h"
#include "bsim3v1init.h" #include "bsim3v1init.h"
SPICEdev B3v1info = {
SPICEdev BSIM3v1info = {
{ "BSIM3v1", { "BSIM3v1",
"Berkeley Short Channel IGFET Model Version-3 (3.1)", "Berkeley Short Channel IGFET Model Version-3 (3.1)",
@ -78,5 +78,5 @@ SPICEdev B3v1info = {
SPICEdev * SPICEdev *
get_bsim3v1_info(void) get_bsim3v1_info(void)
{ {
return &B3v1info;
return &BSIM3v1info;
} }

4
src/spicelib/devices/dev.c

@ -81,8 +81,6 @@ int add_udn(int,Evt_Udn_Info_t **);
#include "bsim3/bsim3itf.h" #include "bsim3/bsim3itf.h"
#include "bsim3v0/bsim3v0itf.h" #include "bsim3v0/bsim3v0itf.h"
#include "bsim3v1/bsim3v1itf.h" #include "bsim3v1/bsim3v1itf.h"
#include "bsim3v1a/bsim3v1aitf.h"
#include "bsim3v1s/bsim3v1sitf.h"
#include "bsim3v32/bsim3v32itf.h" #include "bsim3v32/bsim3v32itf.h"
#include "bsim4/bsim4itf.h" #include "bsim4/bsim4itf.h"
#include "bsim4v2/bsim4v2itf.h" #include "bsim4v2/bsim4v2itf.h"
@ -192,8 +190,6 @@ spice_init_devices(void)
DEVices[ 6] = get_bsim3_info(); DEVices[ 6] = get_bsim3_info();
DEVices[ 7] = get_bsim3v0_info(); DEVices[ 7] = get_bsim3v0_info();
DEVices[ 8] = get_bsim3v1_info(); DEVices[ 8] = get_bsim3v1_info();
DEVices[ 9] = get_bsim3v1a_info();
DEVices[10] = get_bsim3v1s_info();
DEVices[11] = get_bsim3v32_info(); DEVices[11] = get_bsim3v32_info();
DEVices[12] = get_b4soi_info(); DEVices[12] = get_b4soi_info();
DEVices[13] = get_bsim4_info(); DEVices[13] = get_bsim4_info();

10
src/spicelib/parser/inp2m.c

@ -200,7 +200,7 @@ INP2M (CKTcircuit *ckt, INPtables * tab, card * current)
if (thismodel != NULL) if (thismodel != NULL)
{ {
if (thismodel->INPmodType != INPtypelook ("Mos1")
if (thismodel->INPmodType != INPtypelook ("Mos1")
&& thismodel->INPmodType != INPtypelook ("Mos2") && thismodel->INPmodType != INPtypelook ("Mos2")
&& thismodel->INPmodType != INPtypelook ("Mos3") && thismodel->INPmodType != INPtypelook ("Mos3")
&& thismodel->INPmodType != INPtypelook ("Mos5") && thismodel->INPmodType != INPtypelook ("Mos5")
@ -211,7 +211,7 @@ INP2M (CKTcircuit *ckt, INPtables * tab, card * current)
&& thismodel->INPmodType != INPtypelook ("BSIM2") && thismodel->INPmodType != INPtypelook ("BSIM2")
&& thismodel->INPmodType != INPtypelook ("BSIM3") && thismodel->INPmodType != INPtypelook ("BSIM3")
&& thismodel->INPmodType != INPtypelook ("BSIM3v32") && thismodel->INPmodType != INPtypelook ("BSIM3v32")
&& thismodel->INPmodType != INPtypelook ("B4SOI")
&& thismodel->INPmodType != INPtypelook ("B4SOI")
&& thismodel->INPmodType != INPtypelook ("B3SOIPD") && thismodel->INPmodType != INPtypelook ("B3SOIPD")
&& thismodel->INPmodType != INPtypelook ("B3SOIFD") && thismodel->INPmodType != INPtypelook ("B3SOIFD")
&& thismodel->INPmodType != INPtypelook ("B3SOIDD") && thismodel->INPmodType != INPtypelook ("B3SOIDD")
@ -220,10 +220,8 @@ INP2M (CKTcircuit *ckt, INPtables * tab, card * current)
&& thismodel->INPmodType != INPtypelook ("BSIM4v3") && thismodel->INPmodType != INPtypelook ("BSIM4v3")
&& thismodel->INPmodType != INPtypelook ("BSIM4v4") && thismodel->INPmodType != INPtypelook ("BSIM4v4")
&& thismodel->INPmodType != INPtypelook ("BSIM4v5") && thismodel->INPmodType != INPtypelook ("BSIM4v5")
&& thismodel->INPmodType != INPtypelook ("BSIM3v0")
&& thismodel->INPmodType != INPtypelook ("BSIM3v1")
&& thismodel->INPmodType != INPtypelook ("BSIM3v1S")
&& thismodel->INPmodType != INPtypelook ("BSIM3v1A")
&& thismodel->INPmodType != INPtypelook ("BSIM3v0")
&& thismodel->INPmodType != INPtypelook ("BSIM3v1")
&& thismodel->INPmodType != INPtypelook ("SOI3") && thismodel->INPmodType != INPtypelook ("SOI3")
#ifdef CIDER #ifdef CIDER
&& thismodel->INPmodType != INPtypelook ("NUMOS") && thismodel->INPmodType != INPtypelook ("NUMOS")

6
src/spicelib/parser/inpdomod.c

@ -285,12 +285,6 @@ char *INPdomodel(CKTcircuit *ckt, card * image, INPtables * tab)
if ( strcmp(ver, "3.1") == 0 ) { if ( strcmp(ver, "3.1") == 0 ) {
type = INPtypelook("BSIM3v1"); type = INPtypelook("BSIM3v1");
} }
if ( strcmp(ver, "3.1s") == 0 ) {
type = INPtypelook("BSIM3v1S");
}
if ( strcmp(ver, "3.1a") == 0 ) {
type = INPtypelook("BSIM3v1A");
}
if ( prefix("3.2", ver)) { /* version string ver has to start with 3.2 */ if ( prefix("3.2", ver)) { /* version string ver has to start with 3.2 */
type = INPtypelook("BSIM3v32"); type = INPtypelook("BSIM3v32");
} }

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