Correction form Dietmar Warning

22 years ago · 1912d652f6
1 changed files with 451 additions and 368 deletions
--- a/483
+++ b/483
@ -10,11 +10,12 @@ This file is useful in writing ngspice documentation.
 *************************  Linear devices  ********************************
 ***************************************************************************
 
-CAP 	- Capacitor
+CAP	- Capacitor
 	Initial Release.
 	Ver: 	N/A
 	Class:	C
 	Level:	1 (and only)
+	Dir:    devices/cap
 	Status:
 	
 	Enhancements over the original model:
@ -27,10 +28,11 @@ CAP 	- Capacitor
 	  and insulator thickness 
 
 IND 	- Inductor
-      	Initial Release.
+	Initial Release.
 	Ver: 	N/A
 	Class:	L
 	Level:	1 (and only)
+	Dir:    devices/ind
 	Status:
 	
 	Enhancements over the original model:
@ -47,6 +49,7 @@ RES	- Simple linear resistor
 	Ver:	N/A
 	Class:	R
 	Level:	1 (and only)
+	Dir:    devices/res
 	Status:	
 		
 	Enhancements over the original model:
@ -68,26 +71,28 @@ CPL	- Simple Coupled Multiconductor Lines (Kspice)
 	Ver:	N/A
 	Class:	P
 	Level:	1 (and only)
+	Dir:    devices/cpl
 	Status:	
 		
 	This model comes from swec and kspice. It is not documented, if
 	you have kspice docs, can you write a short description
 	of its use ?
 	
-	- Does not implement parallel code switches
-	- Probably a lot of memory leaks
+ 	- Does not implement parallel code switches
+ 	- Probably a lot of memory leaks
 	
 	Enhancements over the original model:
 	
 	- Better integrated into ngspice adding CPLask, CPLmAsk and
-	  CPLunsetup functions
+	CPLunsetup functions
 	
 	
 LTRA	- Lossy Transmission line
 	Initial Release.
 	Ver:	N/A
-	Class:	O
+ 	Class:	O
 	Level:	1 (and only)
+	Dir:    devices/ltra
 	Status:	
 		
 	Original spice model.
@ -99,17 +104,19 @@ TRA	- Transmission line
 	Ver:	N/A
 	Class:	T
 	Level:	1 (and only)
+	Dir:    devices/tra
 	Status:	
 	
 	Original spice model.
 	
 	- Does not implement parallel code switches
 
-TXL     - Simple Lossy Transmission Line (Kspice)
+TXL	- Simple Lossy Transmission Line (Kspice)
 	Initial Release.
 	Ver:	N/A
 	Class:	Y
 	Level:	1 (and only)
+	Dir:    devices/txl
 	Status:	
 	
 	This model comes from kspice. It is not documented, if
@ -123,10 +130,11 @@ TXL     - Simple Lossy Transmission Line (Kspice)
 
 
 URC	- Uniform distributed RC line
-	Initial Release.
+ 	Initial Release.
 	Ver:	N/A
 	Class:	U
 	Level:	1 (and only)
+	Dir:    devices/urc
 	Status:	
 	
 	Original spice model.
@ -143,17 +151,19 @@ ASRC	- Arbitrary Source
 	Ver:	N/A
 	Class:	B
 	Level:	1 (and only)
+	Dir:    devices/asrc
 	Status:	
 	
 	The arbitrary source code has been corrected with the patch
 	available on the Internet. There is still an issue to fix, the
 	current of current-controlled generators.
 
-CCCS  	- Current Controlled Current Source
+CCCS	- Current Controlled Current Source
 	Initial Release.
 	Ver:	N/A
 	Class:	F
 	Level:	1 (and only)
+	Dir:    devices/cccs
 	Status:	
 	
 	Original spice model.
@ -162,7 +172,8 @@ CCVS	- Current Controlled Voltage Source
 	Initial Release.
 	Ver:	N/A
 	Class:	H
-	Level:	1 (and only)
+ 	Level:	1 (and only)
+	Dir:    devices/ccvs
 	Status:	
 	
 	Original spice model.
@ -172,6 +183,7 @@ ISRC	- Independent Current Source
 	Ver:	N/A
 	Class:	I
 	Level:	1 (and only)
+	Dir:    devices/isrc
 	Status:	
 	
 	This is the original spice device improved by Alan Gillespie
@ -186,6 +198,7 @@ VCCS	- Voltage Controlled Current Source
 	Ver:	N/A
 	Class:	G
 	Level:	1 (and only)
+	Dir:    devices/vccs
 	Status:	
 	
 	Original spice model.
@ -195,6 +208,7 @@ VCVS	- Voltage Controlled Voltage Source
 	Ver:	N/A
 	Class:	E
 	Level:	1 (and only)
+	Dir:    devices/vcvs
 	Status:	
 	
 	Original spice model.
@ -204,6 +218,7 @@ VSRC	- Independent Voltage Source
 	Ver:	N/A
 	Class:	V
 	Level:	1 (and only)
+	Dir:    devices/vsrc
 	Status:
 	
 	This is the original spice device improved by Alan Gillespie
@ -217,21 +232,23 @@ VSRC	- Independent Voltage Source
 ****************************      Switches     ****************************
 ***************************************************************************
 		     
-CSW 	- Current controlled switch
+CSW	- Current controlled switch
 	Initial Release.
 	Ver: 	N/A
 	Class:	W
 	Level:	1 (and only) 
+	Dir:    devices/csw
 	Status: 
 	
 	This model comes from Jon Engelbert
 	
 
 SW	- Voltage controlled switch		     
-      	Initial release
+	Initial release
 	Ver: 	N/A
 	Class:	S
 	Level:	1 (and only) 
+	Dir:    devices/sw
 	Status:		
 	
 	This model comes from Jon Engelbert   
@ -242,10 +259,11 @@ SW	- Voltage controlled switch
 ***************************************************************************
 
 DIO	- Junction Diode
-        Initial Release.
+	Initial Release.
 	Ver: 	N/A
 	Class:	D
 	Level:	1 (and only) 
+	Dir:    devices/dio
 	Status: 
 	
 	Enhancements over the original model:
@ -262,10 +280,11 @@ DIO	- Junction Diode
 ***************************************************************************
       
 BJT	- Bipolar Junction Transistor
-        Initial Release.
+	Initial Release.
 	Ver: 	N/A
 	Class:	Q
 	Level:	1 
+	Dir:    devices/bjt
 	Status: 
 	
 	Enhancements over the original model:
@ -279,6 +298,7 @@ BJT2	- Bipolar Junction Transistor
 	Ver: 	N/A
 	Class:	Q
 	Level:	2 
+	Dir:    devices/bjt2
 	Status:
 	
 	This is the BJT model written by Alan Gillespie to support lateral
@ -288,7 +308,7 @@ BJT2	- Bipolar Junction Transistor
 	Enhancements over the original model:
 	
 	- Temperature correction on rc,rb,re
-	- Parallel Multiplier
+ 	- Parallel Multiplier
 	- Temperature difference from circuit temperature
 	- Different area parameters for collector, base and emitter
       
@ -297,12 +317,13 @@ VBIC	- Bipolar Junction Transistor
 	Ver: 	N/A
 	Class:	Q
 	Level:	4 
+	Dir:    devices/vbic
 	Status:
 
-        This is the Vertical Bipolar InterCompany model.
-	The author of VBIC is Colin McAndrew <mcandrew@ieee.org>
+ 	This is the Vertical Bipolar InterCompany model.
+	The author of VBIC is Colin McAndrew <mcandrew@ieee.org
 	Spice3 Implementation: Dietmar Warning DAnalyse GmbH 
-	                       <warning@danalyse.de>
+	                       <warning@danalyse.de
 	Web Site:
 	http://www.designers-guide.com/VBIC/index.html
 	
@ -315,10 +336,11 @@ VBIC	- Bipolar Junction Transistor
 ***************************************************************************
 		     
 JFET	- Junction Field Effect transistor
-        Initial Release.
+	Initial Release.
 	Ver: 	N/A
 	Class:	J
-	Level:	1 
+ 	Level:	1 
+	Dir:    devices/jfet
 	Status:
 	
 	This is the original spice JFET model.
@ -330,10 +352,11 @@ JFET	- Junction Field Effect transistor
 	- Instance temperature as difference for circuit temperature
         
 JFET2	- Junction Field Effect Transistor  (PS model)
-        Initial Release.
+	Initial Release.
 	Ver: 	N/A
 	Class:	J
 	Level:	2 
+	Dir:    devices/jfet2
 	Status:
 	
 	This is the Parker Skellern model.
@ -351,14 +374,14 @@ JFET2	- Junction Field Effect Transistor  (PS model)
 ***************************    HFET devices     ***************************
 ***************************************************************************
            
-HFET  - HFET Level 1 (MacSpice3f4)
-        Initial Release.
+HFET	- HFET Level 1 (MacSpice3f4)
+	Initial Release.
 	Ver: 	N/A
 	Class:	Z
 	Level:	5 
+	Dir:    devices/hfet
 	Status:
 	
-	
 	Enhancements over the original model:
 	
 	- Parallel multiplier
@ -366,42 +389,45 @@ HFET  - HFET Level 1 (MacSpice3f4)
 	- Added pole-zero analysis
 
      
-HFET2 - HFET Level 2 (MacSpice3f4)
-        Initial Release.
+HFET2 	- HFET Level 2 (MacSpice3f4)
+	Initial Release.
 	Ver: 	N/A
 	Class:	Z
 	Level:	6 
+	Dir:    devices/hfet2
 	Status:
 	
-	
 	Enhancements over the original model:
 	
 	- Parallel multiplier
 	- Instance temperature as difference for circuit temperature
 	- Added pole-zero analysis
 	
+ 
 ***************************************************************************
 ***************************     MES devices     ***************************
 ***************************************************************************
 		
-MES   - MESfet model
-        Initial Release.
+MES	- MESfet model
+	Initial Release.
 	Ver: 	N/A
 	Class:	Z
 	Level:	1 
+	Dir:    devices/mes
 	Status:
 	
-	
 	Enhancements over the original model:
 	
 	- Parallel multiplier
 	- Alan Gillespie junction diodes implementation
       
-MESA  - MESA model (MacSpice3f4)
-        Initial Release.
+
+MESA	- MESA model (MacSpice3f4)
+	Initial Release.
 	Ver: 	N/A
 	Class:	Z
 	Level:	2,3,4 
+	Dir:    devices/mesa
 	Status:
 	
 	This is a multilevel model. It contains code for mesa levels
@ -413,178 +439,213 @@ MESA  - MESA model (MacSpice3f4)
 	- Instance temperature as difference from circuit temperature
 	- Added pole-zero analysis
 
+ 		 
 ***************************************************************************
 ****************************    MOS devices    ****************************
 ***************************************************************************
  
-MOS1  - Level 1 MOS model
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  1
-      Status: 
+MOS1	- Level 1 MOS model
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  1
+	Dir:    devices/mos1
+	Status: 
         
-      This is the so-called Schichman-Hodges model. 
+	This is the so-called Schichman-Hodges model. 
         
-      Enhancements over the original model:
+	Enhancements over the original model:
         
-      - Parallel multiplier
-      - Temperature difference from circuit temperature
+	- Parallel multiplier
+	- Temperature difference from circuit temperature
       
 
-MOS2  - Level 2 MOS model
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  2
-      Status: 
+MOS2	- Level 2 MOS model
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  2
+	Dir:    devices/mos2
+	Status: 
         
-      This is the so-called  Grove-Frohman model. 
+	This is the so-called  Grove-Frohman model. 
         
-      Enhancements over the original model:
+	Enhancements over the original model:
         
-      - Parallel multiplier
-      - Temperature difference from circuit temperature
+	- Parallel multiplier
+	- Temperature difference from circuit temperature
 
 
-MOS3  - Level 3 MOS model
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  3
-      Status:  
+MOS3	- Level 3 MOS model
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  3
+	Dir:    devices/mos3
+	Status:  
         
-      Enhancements over the original model:
+	Enhancements over the original model:
         
-      - Parallel multiplier
-      - Temperature difference from circuit temperature
+	- Parallel multiplier
+	- Temperature difference from circuit temperature
       
 
-MOS6  - Level 6 MOS model
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  6
-      Status: 
+MOS6	- Level 6 MOS model
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  6
+	Dir:    devices/mos6
+	Status: 
         
-      Enhancements over the original model:
+	Enhancements over the original model:
         
-      - Parallel multiplier
-      - Temperature difference from circuit temperature
+	- Parallel multiplier
+	- Temperature difference from circuit temperature
 
 
-MOS9  - Level 9 MOS model
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  9
-      Status: 
+MOS9	- Level 9 MOS model
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  9
+	Dir:    devices/mos9
+	Status: 
         
-      Enhancements over the original model:
+	Enhancements over the original model:
         
-      - Temperature difference from circuit temperature
+	- Temperature difference from circuit temperature
+ 
+ 
+BSIM1	- BSIM model level 1
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  4
+	Dir:    devices/bsim1
+	Status: 
+         
+         Enhancements over the original model:
         
+         - Parallel multiplier
+         - Noise analysis
+         
+	BUGS:
+	Distortion analysis probably does not 
+	work with "parallel" devices. Equations
+	are too intricate to deal with. Any one
+	has ideas on the subject ?
+ 
+ 
+BSIM2 	- BSIM model level 2
+	Initial Release.
+	Ver:    N/A
+	Class:  M
+	Level:  5
+	Dir:    devices/bsim2
+	Status: 
         
-BSIM1 - BSIM model level 1
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  4
-      Status: 
+	Enhancements over the original model:
+         
+	- Parallel multiplier
+	- Noise analysis
+ 
+ 
+BSIM3v0 - BSIM model level 3
+	Initial Release.
+	Ver:    3.0
+	Class:  M
+	Level:  47
+	Dir:    devices/bsim3v0
+	Status: TO BE TESTED AND IMPROVED
+         
+ 
+BSIM3v1 - BSIM model level 3
+	Initial Release.
+	Ver:    3.1
+	Class:  M
+	Level:  48
+	Dir:    devices/bsim3v1a
+	Status: TO BE TESTED AND IMPROVED
         
-      Enhancements over the original model:
+	This is the BSIM3v3.1 model modified by Alan Gillespie. 
 
-      - Parallel multiplier
-      - Noise analysis
 
-      BUGS:
+BSIM3v1	- BSIM model level 3
+	Initial Release.
+	Ver:    3.1
+	Class:  M
+	Level:  49
+	Dir:    devices/bsim3v1s
+	Status: TO BE TESTED AND IMPROVED
         
-      Distortion analysis probably does not 
-      work with "parallel" devices. Equations
-      are too intricate to deal with. Any one
-      has ideas on the subject ?
+	This is the BSIM3v3.1 model modified by Serban Popescu. 
+	This is level 49 model. It is an implementation that supports 
+	"HDIF" and "M" parameters.
         
 
-BSIM2 - BSIM model level 2
-      Initial Release.
-      Ver:    N/A
-      Class:  M
-      Level:  5
-      Status: 
+BSIM3v2 - BSIM model level 3
+	Initial Relese.
+	Ver:    3.2
+	Class:  M
+	Level:  50
+	Dir:    devices/bsim3v2
+	Status: TO BE TESTED
 
-      Enhancements over the original model:
+	This is the BSIM3v3.2 model. It is included only for compatibility
+	with existing netlists and parameters files. As always, tests
+	are availabe on the Berkeley's device group site.
         
-      - Parallel multiplier
-      - Noise analysis
+	Web site:
+	http://www-device.eecs.berkeley.edu/~bsim3
 
 
 BSIM3 - BSIM model level 3
-      Initial Release.
-      Ver:    3.2.4
-      Class:  M
-      Level:  8
-      Status: TO BE TESTED 
+	Initial Release.
+	Ver:    3.2.4
+	Class:  M
+	Level:  53
+	Dir:    devices/bsim3
+	Status: TO BE TESTED 
         
-      This is the BSIM3v3.2.4 model from Berkeley device group.  
-      You can find some test netlists with results for this model
-      on its web site.
+	This is the BSIM3v3.2.4 model from Berkeley device group.  
+	You can find some test netlists with results for this model
+	on its web site.
         
-      Web site:
-      http://www-device.eecs.berkeley.edu/~bsim3
+	Web site:
+	http://www-device.eecs.berkeley.edu/~bsim3
         
-      Enhancements over the original model:
+	Enhancements over the original model:
 	
 	- Parallel Multiplier
 	- ACM Area Calculation Method
 	- Multirevision code (supports all 3v3.2 minor revisions)
 	- NodesetFix  
 
-BSIM3v1 - BSIM model level 3
-        Initial Release.
-        Ver:    N/A
-        Class:  M
-        Level:  49
-        Status: TO BE TESTED AND IMPROVED
-        
-        This is the BSIM3v3.1 model modified by Serban Popescu. 
-        This is level 49 model. It is an implementation that supports 
-        "HDIF" and "M" parameters.
-        
-
-BSIM3v2 - BSIM model level 3
-        Initial Relese.
-        Ver:    3.2
-        Class:  M
-        Level:  50
-        Status: TO BE TESTED

-        This is the BSIM3v3.2 model. It is included only for compatibility
-        with existing netlists and parameters files. As always, tests
-        are availabe on the Berkeley's device group site.
-        
-        Web site:
-        http://www-device.eecs.berkeley.edu/~bsim3
+BSIM4	- BSIM model level 4 (0.18 um)
+	Initial Release. 
+	Ver:    4.2.1 (Updated in rework 14)
+	Class:  M
+	Level:  60
+	Dir:    devices/bsim4
+	Status: TO BE TESTED
         
-BSIM4   - BSIM model level 4 (0.18 um)
-        Initial Release. 
-        Ver:    4.2.1 (Updated in rework 14)
-        Class:  M
-        Level:  14
-        Status: TO BE TESTED
+	This is the BSIM4 device model from Berkeley Device Group.
+	Test are available on its web site.
         
-        This is the BSIM4 device model from Berkeley Device Group.
-        Test are available on its web site.
+	Web site:
+	http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
       
-        Web site:
-        http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
+	*) Rework 14: Updated to 4.21 YET UNTESTED.
 	 
-      *) Rework 14: Updated to 4.21 YET UNTESTED.
 
 HiSIM	- Hiroshima-university STARC IGFET Model
 	Initial Release.
 	Ver:	1.2.0
 	Class:	M
 	Level:	64
+	Dir:    devices/hisim
 	Status:
 	
 	This is the HiSIM model available from Hiroshima University
@ -599,84 +660,106 @@ HiSIM	- Hiroshima-university STARC IGFET Model
 	- Parallel Multiplier
 	- NodesetFix
 
+ 	
 ***************************************************************************	 
 *****************************    SOI Devices   ****************************
 ***************************************************************************
 
+BSIM3SOI_FD 	- SOI model (fully depleted devices)
+		Initial Release.
+		Ver:    2.1. 
+		Class:  M
+		Level:  55
+		Dir:    devices/bsim3soi_fd
+		Status: TO BE TESTED.
+         
+		FD model has been integrated.
+		There is a bsim3soifd directory under the test
+		hierarchy. Test circuits come from the bsim3soi
         
-BSIM3SOI_FD - SOI model (fully depleted devices)
-      Initial Release.
-      Ver:    2.1. 
-      Class:  M
-      Level:  11
-      Status: TO BE TESTED.
+		Web site at:
+		http://www-device.eecs.berkeley.edu/~bsimsoi
         
-      FD model has been integrated.
-      There is a bsim3soifd directory under the test
-      hierarchy. Test circuits come from the bsim3soi
+		*) rework-14: removed #ifndef NEWCONV code.
          
-      Web site at:
-      http://www-device.eecs.berkeley.edu/~bsimsoi

-      *) rework-14: removed #ifndef NEWCONV code.
+BSIM3SOI_DD 	- SOI Model (dynamic depletion model)
+         	Initial Release. 
+		Ver:    2.1
+		Class:  M
+		Level:  56
+		Dir:    devices/bsim3soi_dd
+		Status: TO BE TESTED.
        
+		There is a bsim3soidd directory under the
+		test hierarchy. Test circuits come from bsim3soi
        
+		Web site at:
+		http://www-device.eecs.berkeley.edu/~bsimsoi
        
-BSIM3SOI_PD - SOI model (partially depleted devices)
-      Initial Release.
-      Ver:    2.2.1
-      Class:  M
-      Level:  10 
-      Status: TO BE TESTED.
+		*) rework-14: removed #ifndef NEWCONV code.
 
-      PD model has been integrated. 
-      There is a bsim3soipd directory under the test
-      hierarchy. Test circuits come from the bsim3soi

-      Web site at: 
-      http://www-device.eecs.berkeley.edu/~bsimsoi
+BSIM3SOI_PD	- SOI model (partially depleted devices)
+		Initial Release.
+		Ver:    2.2.1
+		Class:  M
+		Level:  57 
+		Dir:    devices/bsim3soi_pd
+		Status: TO BE TESTED.
         
-      *) rework-14: removed #ifndef NEWCONV code.
+		PD model has been integrated. 
+		There is a bsim3soipd directory under the test
+		hierarchy. Test circuits come from the bsim3soi
         
-BSIM3SOI_DD - SOI Model (dynamic depletion model)
-     Initial Release. 
-     Ver:    2.1
-     Class:  M
-     Level:  12
-     Status: TO BE TESTED.
+		Web site at: 
+		http://www-device.eecs.berkeley.edu/~bsimsoi
         
-     There is a bsim3soidd directory under the
-     test hierarchy. Test circuits come from bsim3soi
+		*) rework-14: removed #ifndef NEWCONV code.
 
-     Web site at:
-     http://www-device.eecs.berkeley.edu/~bsimsoi

-     *) rework-14: removed #ifndef NEWCONV code.
+BSIMSOI		 - SOI model (partially/full depleted devices)
+		Initial Release.
+		Ver:    3.0
+		Class:  M
+		Level:  58
+		Dir:    devices/bsim3soi
+		Status: TO BE TESTED.
         
-SOI3 - STAG SOI3 Model
-       Initial Release. 
-       Ver:    2.6
-       Class:  M
-       Level:  62
-       Status: TO BE TESTED
+		This is the newer version from Berkeley. 
+		Usable for partially/full depleted devices.
+         
+		Web site at: 
+		http://www-device.eecs.berkeley.edu/~bsimsoi
+ 
+ 
+SOI3 		- STAG SOI3 Model
+		Initial Release. 
+		Ver:    2.6
+		Class:  M
+		Level:  62
+		Dir:    devices/soi3
+		Status: TO BE TESTED
+         
+		Web site at:
+		http://www.micro.ecs.soton.ac.uk/stag/
        
-       Web site at:
-       http://www.micro.ecs.soton.ac.uk/stag/

 ***************************************************************************
 **************** Other devices not released as source code ****************
 ***************************************************************************
 
-EKV  - EKV model
-       Initial Release. 
-       Ver:    2.6
-       Class:  M
-       Level:  44
-       Status: TO BE TESTED
+EKV	- EKV model
+	Initial Release. 
+	Ver:    2.6
+	Class:  M
+	Level:  44
+	Dir:    devices/ekv
+	Status: TO BE TESTED
         
-       Note: This model is not released in source code.
-       You have to obtain the source code from the address below.
+	Note: This model is not released in source code.
+	You have to obtain the source code from the address below.
         
-       Web site at:
-       http://legwww.epfl.ch/ekv/
+	Web site at:
+	http://legwww.epfl.ch/ekv/