Correction form Dietmar Warning

DEVICES

@@ -15,6 +15,7 @@ CAP 	- Capacitor
 	Ver: 	N/A
 	Class:	C
 	Level:	1 (and only)
+	Dir:    devices/cap
 	Status:
  	
 	Enhancements over the original model:
@@ -31,6 +32,7 @@ IND 	- Inductor
 	Ver: 	N/A
 	Class:	L
 	Level:	1 (and only)
+	Dir:    devices/ind
 	Status:
  	
 	Enhancements over the original model:
@@ -47,6 +49,7 @@ RES	- Simple linear resistor
 	Ver:	N/A
 	Class:	R
 	Level:	1 (and only)
+	Dir:    devices/res
 	Status:	
  		
 	Enhancements over the original model:
@@ -68,6 +71,7 @@ CPL	- Simple Coupled Multiconductor Lines (Kspice)
 	Ver:	N/A
 	Class:	P
 	Level:	1 (and only)
+	Dir:    devices/cpl
 	Status:	
  		
 	This model comes from swec and kspice. It is not documented, if
@@ -88,6 +92,7 @@ LTRA	- Lossy Transmission line
 	Ver:	N/A
  	Class:	O
 	Level:	1 (and only)
+	Dir:    devices/ltra
 	Status:	
  		
 	Original spice model.
@@ -99,6 +104,7 @@ TRA	- Transmission line
 	Ver:	N/A
 	Class:	T
 	Level:	1 (and only)
+	Dir:    devices/tra
 	Status:	
  	
 	Original spice model.
@@ -110,6 +116,7 @@ TXL     - Simple Lossy Transmission Line (Kspice)
 	Ver:	N/A
 	Class:	Y
 	Level:	1 (and only)
+	Dir:    devices/txl
 	Status:	
  	
 	This model comes from kspice. It is not documented, if
@@ -127,6 +134,7 @@ URC	- Uniform distributed RC line
 	Ver:	N/A
 	Class:	U
 	Level:	1 (and only)
+	Dir:    devices/urc
 	Status:	
  	
 	Original spice model.
@@ -143,6 +151,7 @@ ASRC	- Arbitrary Source
 	Ver:	N/A
 	Class:	B
 	Level:	1 (and only)
+	Dir:    devices/asrc
 	Status:	
  	
 	The arbitrary source code has been corrected with the patch
@@ -154,6 +163,7 @@ CCCS  	- Current Controlled Current Source
 	Ver:	N/A
 	Class:	F
 	Level:	1 (and only)
+	Dir:    devices/cccs
 	Status:	
  	
 	Original spice model.
@@ -163,6 +173,7 @@ CCVS	- Current Controlled Voltage Source
 	Ver:	N/A
 	Class:	H
  	Level:	1 (and only)
+	Dir:    devices/ccvs
 	Status:	
  	
 	Original spice model.
@@ -172,6 +183,7 @@ ISRC	- Independent Current Source
 	Ver:	N/A
 	Class:	I
 	Level:	1 (and only)
+	Dir:    devices/isrc
 	Status:	
  	
 	This is the original spice device improved by Alan Gillespie
@@ -186,6 +198,7 @@ VCCS	- Voltage Controlled Current Source
 	Ver:	N/A
 	Class:	G
 	Level:	1 (and only)
+	Dir:    devices/vccs
 	Status:	
  	
 	Original spice model.
@@ -195,6 +208,7 @@ VCVS	- Voltage Controlled Voltage Source
 	Ver:	N/A
 	Class:	E
 	Level:	1 (and only)
+	Dir:    devices/vcvs
 	Status:	
  	
 	Original spice model.
@@ -204,6 +218,7 @@ VSRC	- Independent Voltage Source
 	Ver:	N/A
 	Class:	V
 	Level:	1 (and only)
+	Dir:    devices/vsrc
 	Status:
  	
 	This is the original spice device improved by Alan Gillespie
@@ -222,6 +237,7 @@ CSW 	- Current controlled switch
 	Ver: 	N/A
 	Class:	W
 	Level:	1 (and only) 
+	Dir:    devices/csw
 	Status: 
  	
 	This model comes from Jon Engelbert
@@ -232,6 +248,7 @@ SW	- Voltage controlled switch
 	Ver: 	N/A
 	Class:	S
 	Level:	1 (and only) 
+	Dir:    devices/sw
 	Status:		
  	
 	This model comes from Jon Engelbert   
@@ -246,6 +263,7 @@ DIO	- Junction Diode
 	Ver: 	N/A
 	Class:	D
 	Level:	1 (and only) 
+	Dir:    devices/dio
 	Status: 
  	
 	Enhancements over the original model:
@@ -266,6 +284,7 @@ BJT	- Bipolar Junction Transistor
 	Ver: 	N/A
 	Class:	Q
 	Level:	1 
+	Dir:    devices/bjt
 	Status: 
  	
 	Enhancements over the original model:
@@ -279,6 +298,7 @@ BJT2	- Bipolar Junction Transistor
 	Ver: 	N/A
 	Class:	Q
 	Level:	2 
+	Dir:    devices/bjt2
 	Status:
  	
 	This is the BJT model written by Alan Gillespie to support lateral
@@ -297,12 +317,13 @@ VBIC	- Bipolar Junction Transistor
 	Ver: 	N/A
 	Class:	Q
 	Level:	4 
+	Dir:    devices/vbic
 	Status:
  
  	This is the Vertical Bipolar InterCompany model.
-	The author of VBIC is Colin McAndrew <mcandrew@ieee.org>
+	The author of VBIC is Colin McAndrew <mcandrew@ieee.org
 	Spice3 Implementation: Dietmar Warning DAnalyse GmbH 
-	                       <warning@danalyse.de>
+	                       <warning@danalyse.de
 	Web Site:
 	http://www.designers-guide.com/VBIC/index.html
  	
@@ -319,6 +340,7 @@ JFET	- Junction Field Effect transistor
 	Ver: 	N/A
 	Class:	J
  	Level:	1 
+	Dir:    devices/jfet
 	Status:
  	
 	This is the original spice JFET model.
@@ -334,6 +356,7 @@ JFET2	- Junction Field Effect Transistor  (PS model)
 	Ver: 	N/A
 	Class:	J
 	Level:	2 
+	Dir:    devices/jfet2
 	Status:
  	
 	This is the Parker Skellern model.
@@ -356,9 +379,9 @@ HFET  - HFET Level 1 (MacSpice3f4)
 	Ver: 	N/A
 	Class:	Z
 	Level:	5 
+	Dir:    devices/hfet
 	Status:
  	
-	
 	Enhancements over the original model:
  	
 	- Parallel multiplier
@@ -371,15 +394,16 @@ HFET2 - HFET Level 2 (MacSpice3f4)
 	Ver: 	N/A
 	Class:	Z
 	Level:	6 
+	Dir:    devices/hfet2
 	Status:
  	
-	
 	Enhancements over the original model:
  	
 	- Parallel multiplier
 	- Instance temperature as difference for circuit temperature
 	- Added pole-zero analysis
 	
+ 
 ***************************************************************************
 ***************************     MES devices     ***************************
 ***************************************************************************
@@ -389,19 +413,21 @@ MES   - MESfet model
 	Ver: 	N/A
 	Class:	Z
 	Level:	1 
+	Dir:    devices/mes
 	Status:
  	
-	
 	Enhancements over the original model:
  	
 	- Parallel multiplier
 	- Alan Gillespie junction diodes implementation
        
+
 MESA	- MESA model (MacSpice3f4)
 	Initial Release.
 	Ver: 	N/A
 	Class:	Z
 	Level:	2,3,4 
+	Dir:    devices/mesa
 	Status:
  	
 	This is a multilevel model. It contains code for mesa levels
@@ -413,6 +439,7 @@ MESA  - MESA model (MacSpice3f4)
 	- Instance temperature as difference from circuit temperature
 	- Added pole-zero analysis
  
+ 		 
 ***************************************************************************
 ****************************    MOS devices    ****************************
 ***************************************************************************
@@ -422,6 +449,7 @@ MOS1  - Level 1 MOS model
 	Ver:    N/A
 	Class:  M
 	Level:  1
+	Dir:    devices/mos1
 	Status: 
          
 	This is the so-called Schichman-Hodges model. 
@@ -437,6 +465,7 @@ MOS2  - Level 2 MOS model
 	Ver:    N/A
 	Class:  M
 	Level:  2
+	Dir:    devices/mos2
 	Status: 
          
 	This is the so-called  Grove-Frohman model. 
@@ -452,6 +481,7 @@ MOS3  - Level 3 MOS model
 	Ver:    N/A
 	Class:  M
 	Level:  3
+	Dir:    devices/mos3
 	Status:  
          
 	Enhancements over the original model:
@@ -465,6 +495,7 @@ MOS6  - Level 6 MOS model
 	Ver:    N/A
 	Class:  M
 	Level:  6
+	Dir:    devices/mos6
 	Status: 
          
 	Enhancements over the original model:
@@ -478,6 +509,7 @@ MOS9  - Level 9 MOS model
 	Ver:    N/A
 	Class:  M
 	Level:  9
+	Dir:    devices/mos9
 	Status: 
          
 	Enhancements over the original model:
@@ -490,6 +522,7 @@ BSIM1 - BSIM model level 1
 	Ver:    N/A
 	Class:  M
 	Level:  4
+	Dir:    devices/bsim1
 	Status: 
          
          Enhancements over the original model:
@@ -498,7 +531,6 @@ BSIM1 - BSIM model level 1
          - Noise analysis
          
 	BUGS:
-      
 	Distortion analysis probably does not 
 	work with "parallel" devices. Equations
 	are too intricate to deal with. Any one
@@ -510,6 +542,7 @@ BSIM2 - BSIM model level 2
 	Ver:    N/A
 	Class:  M
 	Level:  5
+	Dir:    devices/bsim2
 	Status: 
          
 	Enhancements over the original model:
@@ -518,32 +551,32 @@ BSIM2 - BSIM model level 2
 	- Noise analysis
  
  
-BSIM3 - BSIM model level 3
+BSIM3v0 - BSIM model level 3
 	Initial Release.
-      Ver:    3.2.4
+	Ver:    3.0
 	Class:  M
-      Level:  8
-      Status: TO BE TESTED 
+	Level:  47
+	Dir:    devices/bsim3v0
+	Status: TO BE TESTED AND IMPROVED
          
-      This is the BSIM3v3.2.4 model from Berkeley device group.  
-      You can find some test netlists with results for this model
-      on its web site.
  
-      Web site:
-      http://www-device.eecs.berkeley.edu/~bsim3
+BSIM3v1 - BSIM model level 3
+	Initial Release.
+	Ver:    3.1
+	Class:  M
+	Level:  48
+	Dir:    devices/bsim3v1a
+	Status: TO BE TESTED AND IMPROVED
          
-      Enhancements over the original model:
+	This is the BSIM3v3.1 model modified by Alan Gillespie. 
  
-	- Parallel Multiplier
-	- ACM Area Calculation Method
-	- Multirevision code (supports all 3v3.2 minor revisions)
-	- NodesetFix  
  
 BSIM3v1	- BSIM model level 3
 	Initial Release.
-        Ver:    N/A
+	Ver:    3.1
 	Class:  M
 	Level:  49
+	Dir:    devices/bsim3v1s
 	Status: TO BE TESTED AND IMPROVED
          
 	This is the BSIM3v3.1 model modified by Serban Popescu. 
@@ -556,6 +589,7 @@ BSIM3v2 - BSIM model level 3
 	Ver:    3.2
 	Class:  M
 	Level:  50
+	Dir:    devices/bsim3v2
 	Status: TO BE TESTED
  
 	This is the BSIM3v3.2 model. It is included only for compatibility
@@ -565,11 +599,36 @@ BSIM3v2 - BSIM model level 3
 	Web site:
 	http://www-device.eecs.berkeley.edu/~bsim3
  
+ 
+BSIM3 - BSIM model level 3
+	Initial Release.
+	Ver:    3.2.4
+	Class:  M
+	Level:  53
+	Dir:    devices/bsim3
+	Status: TO BE TESTED 
+         
+	This is the BSIM3v3.2.4 model from Berkeley device group.  
+	You can find some test netlists with results for this model
+	on its web site.
+         
+	Web site:
+	http://www-device.eecs.berkeley.edu/~bsim3
+         
+	Enhancements over the original model:
+ 	
+	- Parallel Multiplier
+	- ACM Area Calculation Method
+	- Multirevision code (supports all 3v3.2 minor revisions)
+	- NodesetFix  
+ 
+
 BSIM4	- BSIM model level 4 (0.18 um)
 	Initial Release. 
 	Ver:    4.2.1 (Updated in rework 14)
 	Class:  M
-        Level:  14
+	Level:  60
+	Dir:    devices/bsim4
 	Status: TO BE TESTED
          
 	This is the BSIM4 device model from Berkeley Device Group.
@@ -580,11 +639,13 @@ BSIM4   - BSIM model level 4 (0.18 um)
        
 	*) Rework 14: Updated to 4.21 YET UNTESTED.
  	 
+ 
 HiSIM	- Hiroshima-university STARC IGFET Model
 	Initial Release.
 	Ver:	1.2.0
 	Class:	M
 	Level:	64
+	Dir:    devices/hisim
 	Status:
  	
 	This is the HiSIM model available from Hiroshima University
@@ -599,16 +660,17 @@ HiSIM	- Hiroshima-university STARC IGFET Model
 	- Parallel Multiplier
 	- NodesetFix
  
+ 	
 ***************************************************************************	 
 *****************************    SOI Devices   ****************************
 ***************************************************************************
  
-
 BSIM3SOI_FD 	- SOI model (fully depleted devices)
 		Initial Release.
 		Ver:    2.1. 
 		Class:  M
-      Level:  11
+		Level:  55
+		Dir:    devices/bsim3soi_fd
 		Status: TO BE TESTED.
          
 		FD model has been integrated.
@@ -621,12 +683,29 @@ BSIM3SOI_FD - SOI model (fully depleted devices)
 		*) rework-14: removed #ifndef NEWCONV code.
           
 
+BSIM3SOI_DD 	- SOI Model (dynamic depletion model)
+         	Initial Release. 
+		Ver:    2.1
+		Class:  M
+		Level:  56
+		Dir:    devices/bsim3soi_dd
+		Status: TO BE TESTED.
+        
+		There is a bsim3soidd directory under the
+		test hierarchy. Test circuits come from bsim3soi
+        
+		Web site at:
+		http://www-device.eecs.berkeley.edu/~bsimsoi
+        
+		*) rework-14: removed #ifndef NEWCONV code.
+ 
 
 BSIM3SOI_PD	- SOI model (partially depleted devices)
 		Initial Release.
 		Ver:    2.2.1
 		Class:  M
-      Level:  10 
+		Level:  57 
+		Dir:    devices/bsim3soi_pd
 		Status: TO BE TESTED.
          
 		PD model has been integrated. 
@@ -638,31 +717,34 @@ BSIM3SOI_PD - SOI model (partially depleted devices)
          
 		*) rework-14: removed #ifndef NEWCONV code.
  
-BSIM3SOI_DD - SOI Model (dynamic depletion model)
+
+BSIMSOI		 - SOI model (partially/full depleted devices)
 		Initial Release.
-     Ver:    2.1
+		Ver:    3.0
 		Class:  M
-     Level:  12
+		Level:  58
+		Dir:    devices/bsim3soi
 		Status: TO BE TESTED.
          
-     There is a bsim3soidd directory under the
-     test hierarchy. Test circuits come from bsim3soi
+		This is the newer version from Berkeley. 
+		Usable for partially/full depleted devices.
          
 		Web site at: 
 		http://www-device.eecs.berkeley.edu/~bsimsoi
  
-     *) rework-14: removed #ifndef NEWCONV code.
  
 SOI3 		- STAG SOI3 Model
 		Initial Release. 
 		Ver:    2.6
 		Class:  M
 		Level:  62
+		Dir:    devices/soi3
 		Status: TO BE TESTED
          
 		Web site at:
 		http://www.micro.ecs.soton.ac.uk/stag/
         
+
 ***************************************************************************
 **************** Other devices not released as source code ****************
 ***************************************************************************
@@ -672,6 +754,7 @@ EKV  - EKV model
 	Ver:    2.6
 	Class:  M
 	Level:  44
+	Dir:    devices/ekv
 	Status: TO BE TESTED
          
 	Note: This model is not released in source code.