pyNgSpice

Brian Taylor f570b04d6c For unspecified gate delays (logic and tristate gates), which PSpice would consider as zero, set the rise and fall delays to 1.e-12s (the minimum for Xspice). For dff, jkff, dlatch, and srlatch use the Xspice default 1.0ns for rise and fall delays. If the ngspice variable (ps_port_directions & 2) is true, write the translated subckt to stdout, with TRANS_OUT prefix, for debugging purposes. The user could edit and replace the translated subckt if desired.		3 years ago
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README	XSPICE example: delta-sigma converter	14 years ago
count-latch-dac.cir	XSPICE example: delta-sigma converter	14 years ago
counter-test.cir	XSPICE example: delta-sigma converter	14 years ago
delta-sigma-1.cir	add y-axis label	4 years ago
mod1-ct-test.cir	XSPICE example: delta-sigma converter	14 years ago
mod1-ct.cir	XSPICE example: delta-sigma converter	14 years ago

README

A simple delta sigma converter using XSPICE
according to 
Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005
Fig. 2.13, p. 31; Fig. 2.27, p.58


delta-sigma-1.cir
converter complete, tested against sine input

mod1-ct.cir
first order modulator
consists of analog continuous time integrator and
digitally latched comparator

count-latch-dac.cir
contains subcircuits of 
10 bit digital latch
10 bit counter, non-revolving, saturating
simple 10 bit DAC with analog B source

mod1-ct-test.cir
test of modulator with sine input, shows noise shaping 20dB/decade

counter-test.cir
simple test with reset