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10 lines
256 B
10 lines
256 B
VHDL-controlled simple timer.
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* This is the model for an RS flip-flop implemented by Icarus Verilog.
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.model vlog_ff d_cosim simulation="./timer_core" sim_args=["555"]
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* The bulk of the circuit is in a shared file.
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.include ../verilator/555.shared
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.end
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