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pyNgSpice/test_cases

History

Holger Vogt d8eb685fcc Preliminary fix to get_number_terminals: check for tokens with '=' to stop and get number of nodes by stepping back.		3 years ago
..
capacitor	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
cccs	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
ccvs	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
diode	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
hicuml2	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
inductor	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
multiple_devices	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
node_collapsing	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
resistor	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
vccs	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
vcvs	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago
testing.py	prototype for Verilog-A integration using OSDI and OpenVAF	3 years ago