Home Explore Help
Register Sign In
epilectrik
/
pyNgSpice
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
6316 Commits
1 Branch
0 Tags
36 MiB
C 90.4%
C++ 3.2%
AMPL 2.4%
M4 1.4%
Perl 0.4%
Other 1.8%
 
 
 
 
 
 
Tree: d03df9d326
pre-master-46
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'd03df9d326'
${ noResults }
pyNgSpice/tests/regression
History
Holger Vogt 4f3b0ca137
add .if ... .endif test to misc in regression
7 years ago
..
func correct entry for vdmos bulk diode in acload 7 years ago
lib-processing correct entry for vdmos bulk diode in acload 7 years ago
misc correct entry for vdmos bulk diode in acload 7 years ago
model correct entry for vdmos bulk diode in acload 7 years ago
parser regression/**/*.cir, hide printed numeric values in some test cases 9 years ago
pipe add alter-1.cir to EXTRA_DIST 8 years ago
pz correct entry for vdmos bulk diode in acload 7 years ago
sens correct entry for vdmos bulk diode in acload 7 years ago
subckt-processing correct entry for vdmos bulk diode in acload 7 years ago
temper upgrade regression test to the previous commit 10 years ago
Makefile.am regression test for device.c "alter" 8 years ago
Powered by Gitea Version: 1.14.2 Page: 249ms Template: 220ms
English
English 简体中文 繁體中文(香港) 繁體中文(台灣) Deutsch français Nederlands latviešu русский Українська 日本語 español português do Brasil Português de Portugal polski български italiano suomi Türkçe čeština српски svenska 한국어
Licenses API Website Go1.16.4