pyNgSpice

Holger Vogt 3d1e560828 Add configure flag --enable-shortcheck to enable a shortened make check Only BSIM3 and BSIM4 are tested, when selected.		4 years ago
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bin	Add the support files for co-simulation with Verilog code	2 years ago
bsim1	Add the support files for co-simulation with Verilog code	2 years ago
bsim2	Add the support files for co-simulation with Verilog code	2 years ago
bsim3	Add the support files for co-simulation with Verilog code	2 years ago
bsim3soidd	Add the support files for co-simulation with Verilog code	2 years ago
bsim3soifd	Add the support files for co-simulation with Verilog code	2 years ago
bsim3soipd	Add the support files for co-simulation with Verilog code	2 years ago
bsim4	Add the support files for co-simulation with Verilog code	2 years ago
bsimbulk	Add the support files for co-simulation with Verilog code	2 years ago
bsimsoi	Add the support files for co-simulation with Verilog code	2 years ago
filters	Add the support files for co-simulation with Verilog code	2 years ago
general	Add the support files for co-simulation with Verilog code	2 years ago
hfet	Add the support files for co-simulation with Verilog code	2 years ago
hicum2	Add the support files for co-simulation with Verilog code	2 years ago
hisim	Add the support files for co-simulation with Verilog code	2 years ago
hisimhv1	Add the support files for co-simulation with Verilog code	2 years ago
hisimhv2	Add the support files for co-simulation with Verilog code	2 years ago
jfet	Add the support files for co-simulation with Verilog code	2 years ago
mes	Add the support files for co-simulation with Verilog code	2 years ago
mesa	Add the support files for co-simulation with Verilog code	2 years ago
mos6	Add the support files for co-simulation with Verilog code	2 years ago
polezero	Add the support files for co-simulation with Verilog code	2 years ago
regression	Add the support files for co-simulation with Verilog code	2 years ago
resistance	Add the support files for co-simulation with Verilog code	2 years ago
sensitivity	Add the support files for co-simulation with Verilog code	2 years ago
transient	Add the support files for co-simulation with Verilog code	2 years ago
transmission	Add the support files for co-simulation with Verilog code	2 years ago
vbic	Add the support files for co-simulation with Verilog code	2 years ago
xspice	Add the support files for co-simulation with Verilog code	2 years ago
.gitignore	bsim4 generates .out files	11 years ago
ChangeLog	Update of docs and test. Added mesa test files.	25 years ago
Makefile.am	Add configure flag --enable-shortcheck to enable a shortened make check	4 years ago
README	Fixed spelling errors	21 years ago

README

ngspice test and example files:
===============================

This directory is organized as a tree of subdirectories containing test files
for devices and analyses implemented in ngspice.

Some files comes from the original Spice3f5 package and others have been 
contributed by developers and users.


File Extension Convention:

.cir : Circuit file. This can be a simple circuit description or a spice2
       input file.
.out : .cir files have been run and results are recorded into this
       type of file. This is useful if want to test ngspice against
       known (hopefully correct results).        
               
REPLICATE TESTS

To replicate tests you have to launch configure without any option and
compile ngspice. In the future this will change.

TO ADD NEW TESTS

Take an existing test and adopt it to your liking.  Add the test
script and its supporting files to Makefile.am.  Use `make check' to
see your new test in action.