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60 lines
1.5 KiB
60 lines
1.5 KiB
* Simple SRAM cell in a subcircuit, double exponential current pulses
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* control volate
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* IHP Open PDK
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* Path to the PDK
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.lib "D:\Spice_general\IHP-Open-PDK\ihp-sg13g2\libs.tech\ngspice\models\cornerMOSlv.lib" mos_tt
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.param vdd = 1.2
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.param deltat=11n deltat2=25n
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.param tochar = 1e-13
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.param talpha = 500p tbeta=20p
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.param Inull = 'tochar/(talpha-tbeta)'
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* the voltage sources:
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Vdd vd gnd DC 'vdd'
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Vwl wl 0 0 PULSE 0 'vdd' 50n 1n 1n 7n 1
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Vbl bl 0 'vdd'
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Vbln bln 0 0
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Vctrl ctrl 0 pulse (0 1 10n 1n 1n 1 1)
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* Exponential current source with control input
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aseegen1 ctrl [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1
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.model seemod1 seegen (tdelay = 8n tperiod=25n)
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Xnot1 n1 vdd vss n2 not1
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Xnot2 n2 vdd vss n1 not1
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xmo02 n2 wl bl vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
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xmo01 n1 wl bln vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
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Vmeasvss vss 0 0
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Vmeasvdd vd vdd 0
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Vm1 m1 0 0
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Vm2 m2 0 0
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.subckt not1 a vdd vss z
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xm01 z a vdd vdd sg13_lv_pmos l=0.15u w=0.99u as=0.26235p ad=0.26235p ps=2.51u pd=2.51u
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xm02 z a vss vss sg13_lv_nmos l=0.15u w=0.495u as=0.131175p ad=0.131175p ps=1.52u pd=1.52u
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c3 a vss 0.384f
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c2 z vss 0.576f
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.ends
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* starting condition for SRAM cell
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.ic v(n2)=0 v(n1)='vdd'
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* simulation command:
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.tran 100ps 120ns
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.options method=gear
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.control
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pre_osdi C:\Spice64\lib\ngspice\psp103_nqs.osdi
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run
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rusage
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*set nolegend
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set xbrushwidth=3
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plot i(Vmeasvss) i(Vmeasvdd)
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plot n1 n2+2 wl+4 i(vm1)*10000+6 i(vm2)*10000+8
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.endc
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.end
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