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pyNgSpice/examples/xspice

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Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2 years ago
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d_lut	Set lower case for variables or vectors in command 'echo'.	1 year ago
d_process	Set lower case for variables or vectors in command 'echo'.	1 year ago
d_source	Set lower case for variables or vectors in command 'echo'.	1 year ago
delay	Set lower case for variables or vectors in command 'echo'.	1 year ago
delta-sigma	Set lower case for variables or vectors in command 'echo'.	1 year ago
filesource	Set lower case for variables or vectors in command 'echo'.	1 year ago
icarus_verilog	Set lower case for variables or vectors in command 'echo'.	1 year ago
original-examples	Set lower case for variables or vectors in command 'echo'.	1 year ago
pll	Set lower case for variables or vectors in command 'echo'.	1 year ago
pwm-osc	Set lower case for variables or vectors in command 'echo'.	1 year ago
state	Set lower case for variables or vectors in command 'echo'.	1 year ago
table	Set lower case for variables or vectors in command 'echo'.	1 year ago
various	Set lower case for variables or vectors in command 'echo'.	1 year ago
verilator	Set lower case for variables or vectors in command 'echo'.	1 year ago