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pyNgSpice/tests
Holger Vogt 3d1e560828
Add configure flag --enable-shortcheck to enable a shortened make check 		4 years ago
..
bin prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim1 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim2 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim3 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim3soidd prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim3soifd prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim3soipd prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsim4 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsimbulk prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
bsimsoi prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
filters prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
general prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
hfet prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
hicum2 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
hisim prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
hisimhv1 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
hisimhv2 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
jfet prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
mes prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
mesa prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
mos6 prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
polezero prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
regression prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
resistance prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
sensitivity prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
transient prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
transmission prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
vbic prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
xspice prototype for Verilog-A integration using OSDI and OpenVAF 3 years ago
.gitignore bsim4 generates .out files 11 years ago
ChangeLog Update of docs and test. Added mesa test files. 25 years ago
Makefile.am Add configure flag --enable-shortcheck to enable a shortened make check 4 years ago
README Fixed spelling errors 21 years ago

README 

ngspice test and example files:
===============================

This directory is organized as a tree of subdirectories containing test files
for devices and analyses implemented in ngspice.

Some files comes from the original Spice3f5 package and others have been 
contributed by developers and users.


File Extension Convention:

.cir : Circuit file. This can be a simple circuit description or a spice2
       input file.
.out : .cir files have been run and results are recorded into this
       type of file. This is useful if want to test ngspice against
       known (hopefully correct results).        
               
REPLICATE TESTS

To replicate tests you have to launch configure without any option and
compile ngspice. In the future this will change.

TO ADD NEW TESTS

Take an existing test and adopt it to your liking.  Add the test
script and its supporting files to Makefile.am.  Use `make check' to
see your new test in action.