pyNgSpice

rlar 74f03ff027 convert all visual studio proj and sln files to crlf line endings perl -pi -e 's/\r\n/\r\n/' visualc/.vcproj visualc/.sln		11 years ago
..
README	update to XSPICE phase-locked loop example	14 years ago
f-p-det-d-sub.cir	new XSPICE example: mixed mode pll circuit	14 years ago
loop-filter-2.cir	update to XSPICE phase-locked loop example	14 years ago
loop-filter.cir	update to XSPICE phase-locked loop example	14 years ago
pll-xspice-fstep.cir	pll: just include one of the two vco available	14 years ago
pll-xspice.cir	pll: just include one of the two vco available	14 years ago
test-f-p-det.cir	add BSIM3 model parameters for loop filer with transistor charge pump	14 years ago
test_vco.cir	correct the plot output	14 years ago
vco_sub.cir	update to XSPICE phase-locked loop example	14 years ago
vco_sub_new.cir	update to XSPICE phase-locked loop example	14 years ago

README

This directory contains a mixed mode pll, combining
ngspice and XSPICE circuit blocks.
The pll consists of the following blocks:

** voltage controlled oscillator:
vco_sub.cir
   7 stage ring oscillator with gain cells, CMOS devices
or
vco_sub_new.cir
   vco made from code model d_osc, cntl_array/freq_array data
   are gained by running test-vco.cir with vco_sub.cir

** digital divider and frequency reference:
pll-xspice.cir

** phase frequency detector:
f-p-det-d-sub.cir

** loop filter:
loop-filter.cir
   switched current sources as charge pump, 2nd order
   passive RC filter
or
loop-filter-2.cir
   transistors as switches for charge pump, 2nd or 3rd
   order passive RC filters

** main simulation control:
pll-xspice.cir

Two test files are included:
test-vco.cir simulates vco frequency versus control voltage
test-f-p-det.cir simulates the phase frequency detector and the loop filter.

The main building blocks are organised as subcircuits.

main simulation control with three reference frequencies:
pll-xspice-fstep.cir
   simulates two steps of the reference in one simulation run