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pyNgSpice/examples/xspice

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Giles Atkinson 35968d1da6 Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.		2 years ago
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d_lut	no built-in model for bsimbulk, so no qa test needed	1 year ago
d_process	no built-in model for bsimbulk, so no qa test needed	1 year ago
d_source	no built-in model for bsimbulk, so no qa test needed	1 year ago
delay	no built-in model for bsimbulk, so no qa test needed	1 year ago
delta-sigma	no built-in model for bsimbulk, so no qa test needed	1 year ago
filesource	no built-in model for bsimbulk, so no qa test needed	1 year ago
icarus_verilog	no built-in model for bsimbulk, so no qa test needed	1 year ago
original-examples	no built-in model for bsimbulk, so no qa test needed	1 year ago
pll	no built-in model for bsimbulk, so no qa test needed	1 year ago
pwm-osc	no built-in model for bsimbulk, so no qa test needed	1 year ago
state	no built-in model for bsimbulk, so no qa test needed	1 year ago
table	no built-in model for bsimbulk, so no qa test needed	1 year ago
various	no built-in model for bsimbulk, so no qa test needed	1 year ago
verilator	no built-in model for bsimbulk, so no qa test needed	1 year ago