epilectrik
/
pyNgSpice
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
8915 Commits
1 Branch
0 Tags
36 MiB
 
 
 
 
 
 
Tree: 442d8554f0
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '442d8554f0'
${ noResults }
pyNgSpice/tests
Holger Vogt 57185286cf
Skip output lines starting with 'Operating' 		2 years ago
..
bin Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim1 Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim2 Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim3 Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim3soidd Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim3soifd Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim3soipd Enable single terminal n devices (Verilog-A modules) 2 years ago
bsim4 Enable single terminal n devices (Verilog-A modules) 2 years ago
bsimbulk adms bsimbulk and bsimcmg implementation based on work from Robert Larice 5 years ago
bsimsoi Enable single terminal n devices (Verilog-A modules) 2 years ago
filters Enable single terminal n devices (Verilog-A modules) 2 years ago
general Enable single terminal n devices (Verilog-A modules) 2 years ago
hfet Enable single terminal n devices (Verilog-A modules) 2 years ago
hicum2 Enable single terminal n devices (Verilog-A modules) 2 years ago
hisim Enable single terminal n devices (Verilog-A modules) 2 years ago
hisimhv1 Enable single terminal n devices (Verilog-A modules) 2 years ago
hisimhv2 Enable single terminal n devices (Verilog-A modules) 2 years ago
jfet Enable single terminal n devices (Verilog-A modules) 2 years ago
mes Enable single terminal n devices (Verilog-A modules) 2 years ago
mesa Enable single terminal n devices (Verilog-A modules) 2 years ago
mos6 Enable single terminal n devices (Verilog-A modules) 2 years ago
polezero Enable single terminal n devices (Verilog-A modules) 2 years ago
regression Enable single terminal n devices (Verilog-A modules) 2 years ago
resistance Enable single terminal n devices (Verilog-A modules) 2 years ago
sensitivity Enable single terminal n devices (Verilog-A modules) 2 years ago
transient Enable single terminal n devices (Verilog-A modules) 2 years ago
transmission Enable single terminal n devices (Verilog-A modules) 2 years ago
vbic Enable single terminal n devices (Verilog-A modules) 2 years ago
xspice Enable single terminal n devices (Verilog-A modules) 2 years ago
.gitignore bsim4 generates .out files 11 years ago
ChangeLog Update of docs and test. Added mesa test files. 25 years ago
Makefile.am Add configure flag --enable-shortcheck to enable a shortened make check 4 years ago
README Fixed spelling errors 21 years ago

README 

ngspice test and example files:
===============================

This directory is organized as a tree of subdirectories containing test files
for devices and analyses implemented in ngspice.

Some files comes from the original Spice3f5 package and others have been 
contributed by developers and users.


File Extension Convention:

.cir : Circuit file. This can be a simple circuit description or a spice2
       input file.
.out : .cir files have been run and results are recorded into this
       type of file. This is useful if want to test ngspice against
       known (hopefully correct results).        
               
REPLICATE TESTS

To replicate tests you have to launch configure without any option and
compile ngspice. In the future this will change.

TO ADD NEW TESTS

Take an existing test and adopt it to your liking.  Add the test
script and its supporting files to Makefile.am.  Use `make check' to
see your new test in action.