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54 lines
1.2 KiB
54 lines
1.2 KiB
*Sample netlist for BSIM-MG
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* (exec-spice "ngspice %s" t)
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*17-stage ring oscillator
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.include Modelcards/modelcard.nmos
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.include Modelcards/modelcard.pmos
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* --- Voltage Sources ---
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vdd supply 0 dc=1.0
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* --- Inverter Subcircuit ---
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.subckt mg_inv vin vout vdd gnd
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NP1 vout vin vdd vdd BSIMCMG_osdi_P
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NN1 vout vin gnd gnd BSIMCMG_osdi_N
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.ends
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* --- 17 Stage Ring oscillator ---
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Xinv1 1 2 supply 0 mg_inv
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Xinv2 2 3 supply 0 mg_inv
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Xinv3 3 4 supply 0 mg_inv
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Xinv4 4 5 supply 0 mg_inv
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Xinv5 5 6 supply 0 mg_inv
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Xinv6 6 7 supply 0 mg_inv
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Xinv7 7 8 supply 0 mg_inv
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Xinv8 8 9 supply 0 mg_inv
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Xinv9 9 10 supply 0 mg_inv
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Xinv10 10 11 supply 0 mg_inv
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Xinv11 11 12 supply 0 mg_inv
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Xinv12 12 13 supply 0 mg_inv
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Xinv13 13 14 supply 0 mg_inv
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Xinv14 14 15 supply 0 mg_inv
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Xinv15 15 16 supply 0 mg_inv
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Xinv16 16 17 supply 0 mg_inv
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Xinv17 17 1 supply 0 mg_inv
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* --- Initial Condition ---
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.ic v(1)=1
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.tran 1p 1n
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.measure tran t1 when v(1)=0.5 cross=1
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.measure tran t2 when v(1)=0.5 cross=7
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.measure tran period param='(t2-t1)/3'
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.measure tran frequency param='3/(t2-t1)'
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.measure tran delay_per_stage param='period/34'
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.control
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pre_osdi test_osdi_libs/bsimcmg.osdi
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set xbrushwidth=3
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run
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plot v(1)
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.endc
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.end
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