You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 
Giles Atkinson c18447f9f5 Add the support files for co-simulation with Verilog code 2 years ago
..
README.txt Add the support files for co-simulation with Verilog code 2 years ago
adc.cir Add the support files for co-simulation with Verilog code 2 years ago
adc.v Add the support files for co-simulation with Verilog code 2 years ago

README.txt

The circuit adc.cir in this directory illustrates the use of the d_cosim
XSPICE code model as a container for a Verilog simulation. Before the
simulation can be run, the Verilog code must be compiled by Verilator
using the command:

ngspice vlnggen adc.v

That should create a shared library file, adc.so (or adc.DLL on Windows)
that will be loaded by the d_cosim code model. The compiled Verilog code that
it contains will be executed during simulation.