2472 Commits (fed39f18c9ed1723a32b3e2e27d63154ee9e9539)

Author SHA1 Message Date
dwarning fed39f18c9 diode: introduce few parameter aliases for compatibility to other simulators 1 year ago
dwarning ae1437cb52 VBIC: simplify nqs derivatives 1 year ago
Holger Vogt dd07008b55 Remove ADMS related code 1 year ago
Holger Vogt 216f462583 Automtically set optran step time for at least 50 iterations 1 year ago
dwarning 20334c495c VBIC: lean and mean code revision 1 year ago
dwarning 22ef170bac VBIC: fix NQS problems in transient simulation by implementing adjunct network for excess phase 1 year ago
Árpád Bűrmen 91040891f9 Temperature handling inconsistency in jfetnoise.c fixed. 1 year ago
Holger Vogt 796b4fd634 Fixes wrong @bxxx[i] return values of B source, ignoring the m parameter. 1 year ago
Holger Vogt c8dc858f9e use effective gate voltage 1 year ago
dwarning 3da74cacb6 VDMOS: use effektive Gatespannung for mobility reduction of Beta 1 year ago
Árpád Bűrmen d659943d77 Per-device load timing support. 1 year ago
dwarning a6d6a07f79 S to Z matrix conversion by formula instead of Y inversion 1 year ago
Holger Vogt e0a7d821e9 Notes go to stdout, not stderr 1 year ago
dwarning 3f562ae4f6 fix diode level=3 setup for multiple simulations 1 year ago
dwarning 4bd5ebe3e3 Fixed the diode scaling bug reported by A. Buermen 1 year ago
Holger Vogt f9b7455d10 Proper conversion bool to int 1 year ago
Holger Vogt deb3cd9809 Replace all BOOLEAN, BOOL, _Bool by bool 1 year ago
dwarning 07994ff225 VDMOS: concatenate inner node name 1 year ago
Giles Atkinson abc3fceb7e Enhance sensitivity analysis with an option to choose the parameters 1 year ago
Giles Atkinson c30bc423ba Initial fix for Bug 710 - 1 year ago
Holger Vogt 3d7dbc0124 Update to 1 year ago
Holger Vogt 8c806912d0 Improve convergence in Infineon Power MOS. 1 year ago
Brian Taylor 75c2811fa9 Fix some memory leaks. 1 year ago
Holger Vogt a2b8b0d733 In batch mode: if transient simulation fails with 'Timestep too small', 1 year ago
Holger Vogt 5000e0d57a Fix a bug: AF and KF had been interchanged. 1 year ago
Holger Vogt 5d47c9b696 Add AF and KF: error messages in commands 'showmod' or .sens are gone. 1 year ago
dwarning 7b815c743e intel cc see obsolete }; as empty declaration 1 year ago
Holger Vogt 7ac92bb9fc Bail out when the number of s parameter ports is less than 2. 1 year ago
Holger Vogt 70b407d835 Improve error message during setup of TXL or CPL 1 year ago
Holger Vogt de7ae6e678 Fix bug 711 reported by Sonia Edward 1 year ago
Holger Vogt 3d6d0d880a Improve comment 1 year ago
Giles Atkinson e3f7cf3e0a Fix Bug #698 - 1 year ago
Brian Taylor e130371410 Added: Error: Pole/zero analysis is not (yet) supported with 'option KLU'. 2 years ago
briantofleeds 09d352be12 This does not fix noise analysis with klu. 2 years ago
Alessio Cacciatori f300154922 Insert correct conversion sections for KLU matrices 2 years ago
Holger Vogt 2129ac26fd Add optional series resistance or junction capacitance, if non 2 years ago
Francesco Lannutti 419e821a09 Fixed KLU conversion to complex for SP Analysis 2 years ago
Brian Taylor 3528156d14 Fix bug #680. Check that src/dest memcpy arguments are non-NULL. 2 years ago
Matthias Schweikardt 8fbd357fdd extend bsim4 operating point info list 2 years ago
dwarning 4cffcd96ce add missing klu bindings 2 years ago
Vogt 606c6d0df7 Notes go to stdout. 2 years ago
Vogt 232101af10 Don't dereference a NULL pointer. 2 years ago
Vogt 34549c4524 Note directed to stdout 2 years ago
dwarning 9c5507d1c8 vbic: have to load Vrxf/Itxf with value 2 years ago
dwarning 14402ea911 vbic: correct op reporting for excess phase model 2 years ago
dwarning 8c6fb7c5e0 format: rm misleading indentation 2 years ago
Holger Vogt 28c501bfef Add #define RESMIN 1e-6 as a minimum resistor value 2 years ago
dwarning 08d834841f diode: init of potential uninitialized variable 2 years ago
dwarning 4ad7d10aef init of potential uninitialized variables 2 years ago
dwarning bbfb3953ed repair missing parenthesis 2 years ago