Tree: e5d4d7d63f

pre-master-46

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'e5d4d7d63f'

${ noResults }

Commit Graph

1 Commits (e5d4d7d63fc75ed3fef682a3927e101eb30878ef)

Author	SHA1	Message	Date
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago
Giles Atkinson	c18447f9f5	Add the support files for co-simulation with Verilog code compiled by Verilator. Also add script files to Visual Studio builds that are already installed by the Makefile builds.	2 years ago