Tree: d549b882df

pre-master-46

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'd549b882df'

${ noResults }

Commit Graph

1 Commits (d549b882dff2d7ef37f919d886caf552e8149db9)

Author	SHA1	Message	Date
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago