"The log file appears blank when a VDMOS element is added".
The problen was caused by a crash during sensitivity analysis
caused by selecting parameters for wariation based on their
values. That is not repeatable between passes. The fix is to
remove that code, but it causes many more parameters to be used.
when TC or scale is used on the instance line of C and L.
Reason is the missing reset when CKTtemp is called once during each
simulation command. TC or scale is then applied again and again,
a reset is missing.
This patch adds a reset, i.e. the capacitance or inductance is
reset to its instance value in a call to *temp. It fixes bug#594.
Command 'alter' has been tested.
Resistance has not been tackled by this bug, because the line
here->RESconduct = here->RESm / (here->RESresist * factor * here->RESscale);
differs from
here->CAPcapac = here->CAPcapac * factor * here->CAPscale;
in that there is no accumulation of correction factors with here->RESconduct
Giles Atkinson
Holger Vogt
rlar
h_vogt
Francesco Lannutti
pnenzi
arno