pyNgSpice

Author	SHA1	Message	Date
Brian Taylor	6500caeba1	Now that checks on actuals and formals have been fixed for X* instances, some older PSpice libraries will not translate correctly in psa mode. This commit removes unnecessary power and ground nodes from X* instances of subcircuits where the nodes are optional. These X* instances occur within the body of another subcircuit which is being translated. MicroCap libraries that we can translate in ngspice do not have such cases. To enable the removal of the power and ground nodes, set ps_global_tmodels=1 in .spiceinit. This is not set by default since an extra pass through the circuit word list is necessary to find the subcircuits whose instances do not require power and ground node removal. Without enabling this feature, errors reporting too many parameters may be reported.	1 year ago
Brian Taylor	a70297e87a	Several PSPICE 9.1 evaluation digital libraries contain timing .model statements at the global level for subckts with U* instances that reference those models. By specifying "set ps_global_tmodels=1" in .spiceinit an extra pass inside u_instances() will collect those global timing models for use in subckts. Report errors detected when ngspice parses a LOGICEXP but has not added support for operator precendence. Include a hint of how to fix those errors by inserting parentheses. This error only occurs in 10 of 585 cases in the libraries. Note that inpcompat.c has been saved as a unix filetype.	2 years ago
Brian Taylor	492bb64d92	By default, use the shortest typical delay estimate. This makes the digi_74LS90_74LS42.cir testcase for bug641 behave almost the same as MicroCap 12. In ngspice and MicroCap, the only signal with a glitch is not_y8. The other not_* signals look the same. Setting ps_use_mntymx in .spiceinit will change the delay estimates. See the function set_u_devices_info in src/frontend/udevices.c for the various settings of ps_use_mntymx.	3 years ago
Brian Taylor	56d0c72924	Add port directions when logicexp or pindly are present.	3 years ago
Brian Taylor	7ff8f3773f	Handle cases where logicexp has a timing model but no pindly. This is rare, only 22 tests from the digital libraries. Move digital examples, add missing .spiceint file.	3 years ago
Brian Taylor	62aab3885d	Move f_logicexp, f_pindly calls to u_process_instance. Use u_add_instance to copy gate instances and models to the replacement cards.	3 years ago
Brian Taylor	2d9f86c742	Check for name collisions between nodes generated during translation from Pspice to Xspice and instance pin or subckt port names. These are reported as ERRRORs.	4 years ago
Brian Taylor	7f38ce4ebb	Remove debug code.	4 years ago
Brian Taylor	e38e1099b5	Create pin and port lists only when variable ps_pins_and_ports is set != 0.	4 years ago
Brian Taylor	bc8d67d5fa	Generate lists of subckt ports indicating direction (in, out, inout.)	4 years ago
Brian Taylor	96a1b528fd	Replace Pspice U* and .model cards with their Xspice equivalent statements. There are still memory leaks which will be plugged next. The .subckts have only digital ports, which will need to addressed for mixed A/D designs.	4 years ago
Brian Taylor	a2fd346b1a	Trial run at scanning cards for Pspice U* devices and models. #define INTEGRATE_UDEVICES to turn it on. No new cards are created yet, just lots of debugging info.	4 years ago
Brian Taylor	620c15a981	Initial files for translating Pspice u.. instances and timing models into Xspice equivalents. Standard gates, tristate gates, dff, jkff, dlatch are supported. Compound gates and pullup/down are not done. Makefile and frontend/inpcom.c changes have not been finished. These modifications will be needed to complete integration.	4 years ago

13 Commits (6500caeba170e821dcf3fc7c3f6d6cb7e7094acb)