Tree: 5f059abdca

pre-master-46

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from '5f059abdca'

${ noResults }

Commit Graph

1 Commits (5f059abdcadaa406cd2c6cd470aecf702780652f)

Author	SHA1	Message	Date
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago