57dd3342ef
Enable CIDER with KLU for DC, OP, and TRAN analyses. Small signal AC analysis is not yet supported for CIDER complex valued device KLU matrices. The examples/cider testcases produce printed simulation result values which have slight differences between Sparse and KLU. Differences are probably expected and in a few cases are ~1-2%, sometimes a little more. This should be good enough for most CIDER analyses. Francesco did a good piece of work. Runtimes are significantly shorter with KLU.
7 months ago
b19f5ca4c3
bsim4: unify error printout
7 months ago
ecac7a07a2
bsim4: reimplement mobility and binning extension
7 months ago
82bf2169b1
reply commit e5c162f1: dc sweep fails after transient sim
7 months ago
a97dcda62b
prevent warning if NOBYPASS is not defined
7 months ago
32c50aa254
adapt instance parameter extension to new bsim4 multiplier concept
7 months ago
86c78150b7
add KLU bindings for diode selfheating effect, bug #802
7 months ago
5e21393fbb
prevent unused warning
8 months ago
68c3fc1031
diode needs both current components (bottom and sidewall) for Vcrit and breakdown voltage calculation
8 months ago
05bbb2aaa2
introduce aliases for certain diode breakdown model parameter
8 months ago
a0c7af575d
bsim4 update to version 4.8.3
8 months ago
cb944fdb7a
icvgs, icvds, and icvbs should be IOP.
9 months ago
56ecfa9e69
BSIM3 3.3.0 undeclared instance IC parameters.
9 months ago
2c76daf2d1
MESFET m and ic parameters fixed.
10 months ago
87aecbcba7
dtemp bug fixed.
11 months ago
7aa8ed0170
Involve optional d-s shunt in ac and pz analysis
1 year ago
a271ac821a
Correct matrix entries for VDMOS pz analysis
1 year ago
34046a29c1
VDMOS: use Vdsat in mobility reduction formula
1 year ago
a8e54dfb31
Fixed MOS9 scaling.
11 months ago
cc8183a96c
Fixed MOS3 scaling.
11 months ago
fcbee261ac
Fixed MOS2 scaling.
11 months ago
8e2859d30d
Fixed MOS1 noise scaling.
12 months ago
fed39f18c9
diode: introduce few parameter aliases for compatibility to other simulators
1 year ago
ae1437cb52
VBIC: simplify nqs derivatives
1 year ago
dd07008b55
Remove ADMS related code
1 year ago
20334c495c
VBIC: lean and mean code revision
1 year ago
22ef170bac
VBIC: fix NQS problems in transient simulation by implementing adjunct network for excess phase
1 year ago
91040891f9
Temperature handling inconsistency in jfetnoise.c fixed.
1 year ago
796b4fd634
Fixes wrong @bxxx[i] return values of B source, ignoring the m parameter.
Reported in bug 734 by Stefan.
1 year ago
c8dc858f9e
use effective gate voltage
1 year ago
3da74cacb6
VDMOS: use effektive Gatespannung for mobility reduction of Beta
1 year ago
d659943d77
Per-device load timing support.
1 year ago
3f562ae4f6
fix diode level=3 setup for multiple simulations
1 year ago
4bd5ebe3e3
Fixed the diode scaling bug reported by A. Buermen
1 year ago
f9b7455d10
Proper conversion bool to int
1 year ago
deb3cd9809
Replace all BOOLEAN, BOOL, _Bool by bool
Remove all #undef bool (set in conjunction with #iclude <Windows.h>)
1 year ago
07994ff225
VDMOS: concatenate inner node name
1 year ago
c30bc423ba
Initial fix for Bug 710 -
"The log file appears blank when a VDMOS element is added".
The problen was caused by a crash during sensitivity analysis
caused by selecting parameters for wariation based on their
values. That is not repeatable between passes. The fix is to
remove that code, but it causes many more parameters to be used.
1 year ago
3d7dbc0124
Update to
a43c6f491 ("Add #define RESMIN 1e-6 as a minimum resistor value", 2024-07-12)
Remove bug with TL071 model.
1 year ago
5000e0d57a
Fix a bug: AF and KF had been interchanged.
1 year ago
5d47c9b696
Add AF and KF: error messages in commands 'showmod' or .sens are gone.
1 year ago
70b407d835
Improve error message during setup of TXL or CPL
1 year ago
de7ae6e678
Fix bug 711 reported by Sonia Edward
1 year ago
e3f7cf3e0a
Fix Bug #698 -
"Initial transient solution assumes voltage source=0 even if it is not."
Cause was another error in ad5bb9eb8d#607 , which uncovered
an earlier latent bug.
1 year ago
2129ac26fd
Add optional series resistance or junction capacitance, if non
is defined in the .model statement. This may help achieving
convergence if subcircut models of opamps etc use simple diodes
as voltage limiters. Example call:
.options diode_cj0=20p diode_rser=20m
2 years ago
8fbd357fdd
extend bsim4 operating point info list
2 years ago
4cffcd96ce
add missing klu bindings
2 years ago
9c5507d1c8
vbic: have to load Vrxf/Itxf with value
2 years ago
14402ea911
vbic: correct op reporting for excess phase model
2 years ago
8c6fb7c5e0
format: rm misleading indentation
2 years ago
Brian Taylor
dwarning
Árpád Bűrmen
Holger Vogt
dwarning
Giles Atkinson