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pre-master-46

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4 Commits (3fea077ebee5b34d4d9ef2d7e968606d64c1d653)

Author	SHA1	Message	Date
dwarning	96dd397251	correct the plot output	14 years ago
h_vogt	19a67fb7c5	pll: just include one of the two vco available (avoid a bug which has been removed only recently)	14 years ago
h_vogt	a0db6f0ccd	update to XSPICE phase-locked loop example	14 years ago
h_vogt	85ece25a3a	new XSPICE example: mixed mode pll circuit	14 years ago