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1 Commits (144f1c6fc6cb81aa24ad65907ea63edea6944de5)

Author	SHA1	Message	Date
Giles Atkinson	35968d1da6	Add additional examples of Verilog co-simulation and share the Verilog source and large parts of the example circuits between Verilator and Icarus Verilog. Verilog source file adc.v has improved style: all assignments in the always block are now non-blocking.	2 years ago