epilectrik
/
pyNgSpice
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

devices/bsim3v32: whitespace cleanup

pre-master-46
dwarning 13 years ago
committed by rlar
parent
7b2bd10b64
commit
ff6a4990bd
5 changed files with 77 additions and 81 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 3
      src/include/ngspice/devdefs.h
  2. 135
      src/spicelib/devices/bsim3v32/b3v32ld.c
  3. 10
      src/spicelib/devices/bsim3v32/b3v32set.c
  4. 9
      src/spicelib/devices/bsim3v32/b3v32temp.c
  5. 1
      src/spicelib/devices/bsim3v32/bsim3v32def.h

3
src/include/ngspice/devdefs.h
View File

@ -28,9 +28,6 @@ double limitJunctionVoltage( double, double, int * );
double limitVbe( double, double, int * );
double limitVce( double, double, int * );
double limitVgb( double, double, int * );
/* Area Calculation Method (ACM) for MOS models (devsup.c) */
int

135
src/spicelib/devices/bsim3v32/b3v32ld.c
View File

@ -2452,84 +2452,85 @@ finished:
along gate side
*/
if (model->BSIM3v32acmMod == 0)
{
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbd = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32drainArea; /*bug fix */
czbs = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32sourceArea;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbd = model->BSIM3v32unitAreaJctCap * here->BSIM3v32drainArea;
czbs = model->BSIM3v32unitAreaJctCap * here->BSIM3v32sourceArea;
}
if (here->BSIM3v32drainPerimeter < pParam->BSIM3v32weff)
if (model->BSIM3v32acmMod == 0)
{
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* here->BSIM3v32drainPerimeter;
czbd = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32drainArea; /*bug fix */
czbs = model->BSIM3v32unitAreaTempJctCap * here->BSIM3v32sourceArea;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbdswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32drainPerimeter;
czbd = model->BSIM3v32unitAreaJctCap * here->BSIM3v32drainArea;
czbs = model->BSIM3v32unitAreaJctCap * here->BSIM3v32sourceArea;
}
czbdsw = 0.0;
}
else
{
czbdsw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
}
if (here->BSIM3v32sourcePerimeter < pParam->BSIM3v32weff)
{
czbssw = 0.0;
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* here->BSIM3v32sourcePerimeter;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32sourcePerimeter;
if (here->BSIM3v32drainPerimeter < pParam->BSIM3v32weff)
{
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* here->BSIM3v32drainPerimeter;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbdswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32drainPerimeter;
}
czbdsw = 0.0;
}
}
else
{
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbssw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbssw = model->BSIM3v32unitLengthSidewallJctCap
* (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
* pParam->BSIM3v32weff;
else
{
czbdsw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32drainPerimeter - pParam->BSIM3v32weff);
czbdswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
}
}
} else {
if (here->BSIM3v32sourcePerimeter < pParam->BSIM3v32weff)
{
czbssw = 0.0;
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* here->BSIM3v32sourcePerimeter;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
* here->BSIM3v32sourcePerimeter;
}
}
else
{
/* Added revision dependent code */
switch (model->BSIM3v32intVersion) {
case BSIM3v32V324:
case BSIM3v32V323:
czbssw = model->BSIM3v32unitLengthSidewallTempJctCap
* (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
czbsswg = model->BSIM3v32unitLengthGateSidewallTempJctCap
* pParam->BSIM3v32weff;
break;
case BSIM3v32V322:
case BSIM3v32V32:
default:
czbssw = model->BSIM3v32unitLengthSidewallJctCap
* (here->BSIM3v32sourcePerimeter - pParam->BSIM3v32weff);
czbsswg = model->BSIM3v32unitLengthGateSidewallJctCap
* pParam->BSIM3v32weff;
}
}
} else {
error = ACM_junctionCapacitances(
model->BSIM3v32acmMod,
model->BSIM3v32calcacm,
@ -2558,7 +2559,7 @@ finished:
);
if (error)
return(error);
}
}
MJ = model->BSIM3v32bulkJctBotGradingCoeff;
MJSW = model->BSIM3v32bulkJctSideGradingCoeff;

10
src/spicelib/devices/bsim3v32/b3v32set.c
View File

@ -1001,14 +1001,14 @@ IFuid tmpName;
{ here->BSIM3v32sNodePrime = here->BSIM3v32sNode;
}
/* internal charge node */
/* internal charge node */
if (here->BSIM3v32nqsMod)
{ if(here->BSIM3v32qNode == 0)
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v32name,"charge");
if(error) return(error);
here->BSIM3v32qNode = tmp->number;
}
{ error = CKTmkVolt(ckt,&tmp,here->BSIM3v32name,"charge");
if(error) return(error);
here->BSIM3v32qNode = tmp->number;
}
}
else
{ here->BSIM3v32qNode = 0;

9
src/spicelib/devices/bsim3v32/b3v32temp.c
View File

@ -880,10 +880,10 @@ int Size_Not_Found, error;
/* ACM model */
if (model->BSIM3v32acmMod == 0)
{
here->BSIM3v32drainConductance = model->BSIM3v32sheetResistance
* here->BSIM3v32drainSquares;
here->BSIM3v32sourceConductance = model->BSIM3v32sheetResistance
* here->BSIM3v32sourceSquares;
here->BSIM3v32drainConductance = model->BSIM3v32sheetResistance
* here->BSIM3v32drainSquares;
here->BSIM3v32sourceConductance = model->BSIM3v32sheetResistance
* here->BSIM3v32sourceSquares;
}
else /* ACM > 0 */
{
@ -1012,7 +1012,6 @@ int Size_Not_Found, error;
break;
}
}
}
}
return(OK);

1
src/spicelib/devices/bsim3v32/bsim3v32def.h
View File

@ -1757,7 +1757,6 @@ typedef struct sBSIM3v32model
/* ACM parameters */
#define BSIM3v32_MOD_XL 703
#define BSIM3v32_MOD_XW 704
#define BSIM3v32_MOD_HDIF 711
#define BSIM3v32_MOD_LDIF 712
#define BSIM3v32_MOD_LD 713

Write Preview
Loading…
Cancel
Save