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reported by Carsten Schoenert
pre-master-46
Holger Vogt 7 years ago
parent
a98f6ac69b
commit
feaebe6bd9
3 changed files with 3 additions and 3 deletions
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  1. 2
      src/spicelib/devices/bsim4/b4.c
  2. 2
      src/spicelib/devices/bsim4v6/b4v6.c
  3. 2
      src/spicelib/devices/bsim4v7/b4v7.c

2
src/spicelib/devices/bsim4/b4.c
View File

@ -467,7 +467,7 @@ IOP( "jtssws", BSIM4_MOD_JTSSWS, IF_REAL, "Source STI sidewall trap-assisted sat
IOP( "jtsswd", BSIM4_MOD_JTSSWD, IF_REAL, "Drain STI sidewall trap-assisted saturation current density"),
IOP( "jtsswgs", BSIM4_MOD_JTSSWGS, IF_REAL, "Source gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtsswgd", BSIM4_MOD_JTSSWGD, IF_REAL, "Drain gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtweff", BSIM4_MOD_JTWEFF, IF_REAL, "TAT current width dependance"),
IOP( "jtweff", BSIM4_MOD_JTWEFF, IF_REAL, "TAT current width dependence"),
IOP( "njts", BSIM4_MOD_NJTS, IF_REAL, "Non-ideality factor for bottom junction"),
IOP( "njtssw", BSIM4_MOD_NJTSSW, IF_REAL, "Non-ideality factor for STI sidewall junction"),
IOP( "njtsswg", BSIM4_MOD_NJTSSWG, IF_REAL, "Non-ideality factor for gate-edge sidewall junction"),

2
src/spicelib/devices/bsim4v6/b4v6.c
View File

@ -413,7 +413,7 @@ IOP( "jtssws", BSIM4v6_MOD_JTSSWS, IF_REAL, "Source STI sidewall trap-assisted s
IOP( "jtsswd", BSIM4v6_MOD_JTSSWD, IF_REAL, "Drain STI sidewall trap-assisted saturation current density"),
IOP( "jtsswgs", BSIM4v6_MOD_JTSSWGS, IF_REAL, "Source gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtsswgd", BSIM4v6_MOD_JTSSWGD, IF_REAL, "Drain gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtweff", BSIM4v6_MOD_JTWEFF, IF_REAL, "TAT current width dependance"),
IOP( "jtweff", BSIM4v6_MOD_JTWEFF, IF_REAL, "TAT current width dependence"),
IOP( "njts", BSIM4v6_MOD_NJTS, IF_REAL, "Non-ideality factor for bottom junction"),
IOP( "njtssw", BSIM4v6_MOD_NJTSSW, IF_REAL, "Non-ideality factor for STI sidewall junction"),
IOP( "njtsswg", BSIM4v6_MOD_NJTSSWG, IF_REAL, "Non-ideality factor for gate-edge sidewall junction"),

2
src/spicelib/devices/bsim4v7/b4v7.c
View File

@ -430,7 +430,7 @@ IOP( "jtssws", BSIM4v7_MOD_JTSSWS, IF_REAL, "Source STI sidewall trap-assisted s
IOP( "jtsswd", BSIM4v7_MOD_JTSSWD, IF_REAL, "Drain STI sidewall trap-assisted saturation current density"),
IOP( "jtsswgs", BSIM4v7_MOD_JTSSWGS, IF_REAL, "Source gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtsswgd", BSIM4v7_MOD_JTSSWGD, IF_REAL, "Drain gate-edge sidewall trap-assisted saturation current density"),
IOP( "jtweff", BSIM4v7_MOD_JTWEFF, IF_REAL, "TAT current width dependance"),
IOP( "jtweff", BSIM4v7_MOD_JTWEFF, IF_REAL, "TAT current width dependence"),
IOP( "njts", BSIM4v7_MOD_NJTS, IF_REAL, "Non-ideality factor for bottom junction"),
IOP( "njtssw", BSIM4v7_MOD_NJTSSW, IF_REAL, "Non-ideality factor for STI sidewall junction"),
IOP( "njtsswg", BSIM4v7_MOD_NJTSSWG, IF_REAL, "Non-ideality factor for gate-edge sidewall junction"),

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