Changed line ending of several files from DOS to UNIX

src/spicelib/devices/bsim3soi_dd/BsimTerms_use

@@ -1,29 +1,29 @@
-The terms under which the software is provided  are as the following.
-
-Software is distributed as is, completely without warranty or service
-support. The University of California and its employees are not liable
-for the condition or performance of the software.
-
-The University owns the copyright but shall not be liable for any
-infringement of copyright or other proprietary rights brought by third
-parties against the users of the software.
-
-The University of California hereby disclaims all implied warranties.
-
-The University of California grants the users the right to modify, copy,
-and redistribute the software and documentation, both within the user's
-organization and externally, subject to the following restrictions
-
-1. The users agree not to charge for the University of California code
-   itself but may charge for additions, extensions, or support.
-
-2. In any product based on the software, the users agree to acknowledge
-   the UC Berkeley BSIM Research Group that developed the software. This
-   acknowledgment shall appear in the product documentation.
-
-3. The users agree to obey all U.S. Government restrictions governing
-   redistribution or export of the software.
-
-4. The users agree to reproduce any copyright notice which appears on
-   the software on any copy or modification of such made available 
-   to others.
+The terms under which the software is provided  are as the following.
+
+Software is distributed as is, completely without warranty or service
+support. The University of California and its employees are not liable
+for the condition or performance of the software.
+
+The University owns the copyright but shall not be liable for any
+infringement of copyright or other proprietary rights brought by third
+parties against the users of the software.
+
+The University of California hereby disclaims all implied warranties.
+
+The University of California grants the users the right to modify, copy,
+and redistribute the software and documentation, both within the user's
+organization and externally, subject to the following restrictions
+
+1. The users agree not to charge for the University of California code
+   itself but may charge for additions, extensions, or support.
+
+2. In any product based on the software, the users agree to acknowledge
+   the UC Berkeley BSIM Research Group that developed the software. This
+   acknowledgment shall appear in the product documentation.
+
+3. The users agree to obey all U.S. Government restrictions governing
+   redistribution or export of the software.
+
+4. The users agree to reproduce any copyright notice which appears on
+   the software on any copy or modification of such made available 
+   to others.

src/spicelib/devices/bsim3soi_fd/BsimTerms_use

@@ -1,29 +1,29 @@
-The terms under which the software is provided  are as the following.
-
-Software is distributed as is, completely without warranty or service
-support. The University of California and its employees are not liable
-for the condition or performance of the software.
-
-The University owns the copyright but shall not be liable for any
-infringement of copyright or other proprietary rights brought by third
-parties against the users of the software.
-
-The University of California hereby disclaims all implied warranties.
-
-The University of California grants the users the right to modify, copy,
-and redistribute the software and documentation, both within the user's
-organization and externally, subject to the following restrictions
-
-1. The users agree not to charge for the University of California code
-   itself but may charge for additions, extensions, or support.
-
-2. In any product based on the software, the users agree to acknowledge
-   the UC Berkeley BSIM Research Group that developed the software. This
-   acknowledgment shall appear in the product documentation.
-
-3. The users agree to obey all U.S. Government restrictions governing
-   redistribution or export of the software.
-
-4. The users agree to reproduce any copyright notice which appears on
-   the software on any copy or modification of such made available 
-   to others.
+The terms under which the software is provided  are as the following.
+
+Software is distributed as is, completely without warranty or service
+support. The University of California and its employees are not liable
+for the condition or performance of the software.
+
+The University owns the copyright but shall not be liable for any
+infringement of copyright or other proprietary rights brought by third
+parties against the users of the software.
+
+The University of California hereby disclaims all implied warranties.
+
+The University of California grants the users the right to modify, copy,
+and redistribute the software and documentation, both within the user's
+organization and externally, subject to the following restrictions
+
+1. The users agree not to charge for the University of California code
+   itself but may charge for additions, extensions, or support.
+
+2. In any product based on the software, the users agree to acknowledge
+   the UC Berkeley BSIM Research Group that developed the software. This
+   acknowledgment shall appear in the product documentation.
+
+3. The users agree to obey all U.S. Government restrictions governing
+   redistribution or export of the software.
+
+4. The users agree to reproduce any copyright notice which appears on
+   the software on any copy or modification of such made available 
+   to others.

src/spicelib/devices/bsim3soi_pd/BsimTerms_use

@@ -1,29 +1,29 @@
-The terms under which the software is provided  are as the following.
-
-Software is distributed as is, completely without warranty or service
-support. The University of California and its employees are not liable
-for the condition or performance of the software.
-
-The University owns the copyright but shall not be liable for any
-infringement of copyright or other proprietary rights brought by third
-parties against the users of the software.
-
-The University of California hereby disclaims all implied warranties.
-
-The University of California grants the users the right to modify, copy,
-and redistribute the software and documentation, both within the user's
-organization and externally, subject to the following restrictions
-
-1. The users agree not to charge for the University of California code
-   itself but may charge for additions, extensions, or support.
-
-2. In any product based on the software, the users agree to acknowledge
-   the UC Berkeley BSIM Research Group that developed the software. This
-   acknowledgment shall appear in the product documentation.
-
-3. The users agree to obey all U.S. Government restrictions governing
-   redistribution or export of the software.
-
-4. The users agree to reproduce any copyright notice which appears on
-   the software on any copy or modification of such made available 
-   to others.
+The terms under which the software is provided  are as the following.
+
+Software is distributed as is, completely without warranty or service
+support. The University of California and its employees are not liable
+for the condition or performance of the software.
+
+The University owns the copyright but shall not be liable for any
+infringement of copyright or other proprietary rights brought by third
+parties against the users of the software.
+
+The University of California hereby disclaims all implied warranties.
+
+The University of California grants the users the right to modify, copy,
+and redistribute the software and documentation, both within the user's
+organization and externally, subject to the following restrictions
+
+1. The users agree not to charge for the University of California code
+   itself but may charge for additions, extensions, or support.
+
+2. In any product based on the software, the users agree to acknowledge
+   the UC Berkeley BSIM Research Group that developed the software. This
+   acknowledgment shall appear in the product documentation.
+
+3. The users agree to obey all U.S. Government restrictions governing
+   redistribution or export of the software.
+
+4. The users agree to reproduce any copyright notice which appears on
+   the software on any copy or modification of such made available 
+   to others.

src/xspice/examples/hybrid_models1_dc.deck

@@ -1,46 +1,46 @@
-Code Model Test - DC: d_osc, dac_bridge, adc_bridge
-*
-*
-*** analysis type ***
-.op
-*
-*** input sources ***
-v1 1 0 DC 2 
-*
-v2 2 0 DC 2
-*
-*** d_osc block ***
-a1 1 10 d_osc1 
-.model d_osc1 d_osc (cntl_array=[-1.0 0.0 1.0 2.0] 
-+                    freq_array=[100 100 1000 1000]
-+                    duty_cycle=0.5 init_phase=0.0
-+                    rise_delay=1.0e-6 fall_delay=2.0e-6)
-*
-*** dac_bridge block ***
-a2 [10] [20] dac_bridge1
-.model dac_bridge1 dac_bridge (out_low=0.5 out_high=4.5 out_undef=1.8
-+                              input_load=1.0e-12
-+                              t_rise=1.0e-6 t_fall=2.0e-6)
-*
-*
-*** adc_bridge block ***
-a3 [2] [30] adc_bridge1
-.model adc_bridge1 adc_bridge (in_low=0.7 in_high=2.4 
-+                              rise_delay=1.0e-12 fall_delay=2.0e-12)
-*
-*
-*
-*** resistors to ground ***
-r1 1 0 1k
-r2 2 0 1k
-*
-r20 20 0 1k
-*
-*
-.end
-
-
-
-
-
-
+Code Model Test - DC: d_osc, dac_bridge, adc_bridge
+*
+*
+*** analysis type ***
+.op
+*
+*** input sources ***
+v1 1 0 DC 2 
+*
+v2 2 0 DC 2
+*
+*** d_osc block ***
+a1 1 10 d_osc1 
+.model d_osc1 d_osc (cntl_array=[-1.0 0.0 1.0 2.0] 
++                    freq_array=[100 100 1000 1000]
++                    duty_cycle=0.5 init_phase=0.0
++                    rise_delay=1.0e-6 fall_delay=2.0e-6)
+*
+*** dac_bridge block ***
+a2 [10] [20] dac_bridge1
+.model dac_bridge1 dac_bridge (out_low=0.5 out_high=4.5 out_undef=1.8
++                              input_load=1.0e-12
++                              t_rise=1.0e-6 t_fall=2.0e-6)
+*
+*
+*** adc_bridge block ***
+a3 [2] [30] adc_bridge1
+.model adc_bridge1 adc_bridge (in_low=0.7 in_high=2.4 
++                              rise_delay=1.0e-12 fall_delay=2.0e-12)
+*
+*
+*
+*** resistors to ground ***
+r1 1 0 1k
+r2 2 0 1k
+*
+r20 20 0 1k
+*
+*
+.end
+
+
+
+
+
+

src/xspice/examples/initial_conditions.deck

@@ -1,19 +1,19 @@
-Capacitor and inductor with natural initial conditions
-*
-* This circuit contains a capacitor and an inductor with
-* initial conditions on them.  Each of the components
-* has a parallel resistor so that an exponential decay
-* of the initial condition occurs with a time constant of
-* 1 second.
-*
-.tran 0.1 5
-*
-a1 1 0 cap
-.model cap capacitor (c=1000uf ic=1)
-r1 1 0 1k
-*
-a2 2 0 ind
-.model ind inductor (l=1H ic=1)
-r2 2 0 1.0
-*
-.end
+Capacitor and inductor with natural initial conditions
+*
+* This circuit contains a capacitor and an inductor with
+* initial conditions on them.  Each of the components
+* has a parallel resistor so that an exponential decay
+* of the initial condition occurs with a time constant of
+* 1 second.
+*
+.tran 0.1 5
+*
+a1 1 0 cap
+.model cap capacitor (c=1000uf ic=1)
+r1 1 0 1k
+*
+a2 2 0 ind
+.model ind inductor (l=1H ic=1)
+r2 2 0 1.0
+*
+.end

src/xspice/examples/io_ordering.deck

@@ -1,17 +1,17 @@
-IO ordering
-*
-* This circuit contains a simple gain block.  The order of
-* the nodes listed on the instance line follows the order
-* of the connections defined in the 'ifspec.ifs' file for
-* the model.  Refer to /atesse-su/src/cml/gain/ifspec.ifs .
-*
-.tran 1e-5 1e-3
-*
-v1 1 0 0.0 sin(0 1 1k)
-r1 1 0 1k
-*
-a1 1 2 gain_block
-.model gain_block gain (gain=10)
-r2 2 0 1k
-*
-.end
+IO ordering
+*
+* This circuit contains a simple gain block.  The order of
+* the nodes listed on the instance line follows the order
+* of the connections defined in the 'ifspec.ifs' file for
+* the model.  Refer to /atesse-su/src/cml/gain/ifspec.ifs .
+*
+.tran 1e-5 1e-3
+*
+v1 1 0 0.0 sin(0 1 1k)
+r1 1 0 1k
+*
+a1 1 2 gain_block
+.model gain_block gain (gain=10)
+r2 2 0 1k
+*
+.end

src/xspice/examples/io_types.deck

@@ -1,34 +1,34 @@
-IO types
-*
-* This circuit contains a mix of input output types including
-* voltages, currents, digital signals, and user defined
-* signals.
-*
-.tran 1e-6 1e-4
-*
-v1  1 0  0.0 pulse(0 1 2e-5)
-r1  1 0  1k
-*
-abridge1  [1] [enable]  node_bridge1
-.model node_bridge1 adc_bridge
-*
-aclk  [enable clk] clk  nand
-.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
-*
-abridge2  clk enable real_node1  node_bridge2
-.model node_bridge2 d_to_real (zero=-1 one=1)
-*
-again  real_node1 real_node2  times10
-.model times10 real_gain (gain=10)
-*
-abridge3  real_node2 analog_node  node_bridge3
-.model node_bridge3 real_to_v
-*
-rout  analog_node 0  1k
-*
-again %vnam v1 %i i_out gain_block
-.model gain_block gain (gain=10)
-ri_out i_out 0 1k
-*
-*
-.end
+IO types
+*
+* This circuit contains a mix of input output types including
+* voltages, currents, digital signals, and user defined
+* signals.
+*
+.tran 1e-6 1e-4
+*
+v1  1 0  0.0 pulse(0 1 2e-5)
+r1  1 0  1k
+*
+abridge1  [1] [enable]  node_bridge1
+.model node_bridge1 adc_bridge
+*
+aclk  [enable clk] clk  nand
+.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
+*
+abridge2  clk enable real_node1  node_bridge2
+.model node_bridge2 d_to_real (zero=-1 one=1)
+*
+again  real_node1 real_node2  times10
+.model times10 real_gain (gain=10)
+*
+abridge3  real_node2 analog_node  node_bridge3
+.model node_bridge3 real_to_v
+*
+rout  analog_node 0  1k
+*
+again %vnam v1 %i i_out gain_block
+.model gain_block gain (gain=10)
+ri_out i_out 0 1k
+*
+*
+.end

src/xspice/examples/long_names.deck

@@ -1,19 +1,19 @@
-Long names
-*
-* This circuit contains a sine wave source followed by a
-* gain block code model with a gain of 10.  Long names
-* are used for instances, models, and nodes.
-*
-.tran 1e-5 1e-3
-*
-v1_123456789_123456789_1234  1 0  0.0 sin(0 1 2k)
-*
-r1_123456789_123456789_1234  1 0  1k
-*
-a1_123456789_123456789_1234  1 out_123456789_123456789_1234
-+   gain_block_123456789_123456789_1234
-*
-.model gain_block_123456789_123456789_1234 gain (gain=10)
-r2_123456789_123456789_1234  out_123456789_123456789_1234 0  1k
-*
-.end
+Long names
+*
+* This circuit contains a sine wave source followed by a
+* gain block code model with a gain of 10.  Long names
+* are used for instances, models, and nodes.
+*
+.tran 1e-5 1e-3
+*
+v1_123456789_123456789_1234  1 0  0.0 sin(0 1 2k)
+*
+r1_123456789_123456789_1234  1 0  1k
+*
+a1_123456789_123456789_1234  1 out_123456789_123456789_1234
++   gain_block_123456789_123456789_1234
+*
+.model gain_block_123456789_123456789_1234 gain (gain=10)
+r2_123456789_123456789_1234  out_123456789_123456789_1234 0  1k
+*
+.end

src/xspice/examples/mixed_case.deck

@@ -1,15 +1,15 @@
-MiXeD CaSe
-*
-* This circuit contains a simple gain block to demonstrate
-* that the simulator deck parsing code is case-insensitive.
-*
-.TrAn 1E-5 1e-3
-*
-V1 1 0 0.0 sIn(0 1 1k)
-r1 1 0 1k
-*
-A1 1 2 GaIn_BlOcK
-.MODel gAiN_bLoCk GAin (gaIN=10)
-r2 2 0 1K
-*
-.eNd
+MiXeD CaSe
+*
+* This circuit contains a simple gain block to demonstrate
+* that the simulator deck parsing code is case-insensitive.
+*
+.TrAn 1E-5 1e-3
+*
+V1 1 0 0.0 sIn(0 1 1k)
+r1 1 0 1k
+*
+A1 1 2 GaIn_BlOcK
+.MODel gAiN_bLoCk GAin (gaIN=10)
+r2 2 0 1K
+*
+.eNd

src/xspice/examples/mixed_io_size.deck

@@ -1,33 +1,33 @@
-Mixed IO sizes
-*
-* This circuit contains a collection of digital and analog
-* models with saclar and vector inputs of varying sizes.
-*
-.tran 1e-5 1e-3
-*
-v1 1 0 0.0 pulse(0 1 1e-4)
-r1 1 0 1k
-*
-v2 2 0 0.0 sin(0 1 2k)
-r2 2 0 1k
-*
-abridge1 [1] [enable] atod
-.model atod adc_bridge
-*
-aosc [enable clk] clk nand
-.model nand d_nand (rise_delay=1e-4 fall_delay=1e-4)
-*
-ainv clk clk_bar inv
-.model inv d_inverter (rise_delay=1e-5 fall_delay=1e-5)
-*
-adac [clk clk_bar] [3 4] dac
-.model dac dac_bridge (t_rise=1e-5 t_fall=1e-5)
-*
-asum [1 2 3 4] 5 sum
-.model sum summer
-*
-r3 3 0 1k
-r4 4 0 1k
-r5 5 0 1k
-*
-.end
+Mixed IO sizes
+*
+* This circuit contains a collection of digital and analog
+* models with saclar and vector inputs of varying sizes.
+*
+.tran 1e-5 1e-3
+*
+v1 1 0 0.0 pulse(0 1 1e-4)
+r1 1 0 1k
+*
+v2 2 0 0.0 sin(0 1 2k)
+r2 2 0 1k
+*
+abridge1 [1] [enable] atod
+.model atod adc_bridge
+*
+aosc [enable clk] clk nand
+.model nand d_nand (rise_delay=1e-4 fall_delay=1e-4)
+*
+ainv clk clk_bar inv
+.model inv d_inverter (rise_delay=1e-5 fall_delay=1e-5)
+*
+adac [clk clk_bar] [3 4] dac
+.model dac dac_bridge (t_rise=1e-5 t_fall=1e-5)
+*
+asum [1 2 3 4] 5 sum
+.model sum summer
+*
+r3 3 0 1k
+r4 4 0 1k
+r5 5 0 1k
+*
+.end

src/xspice/examples/mixed_mode.deck

@@ -1,98 +1,98 @@
-Mixed IO types
-*
-* This circuit contains a mixture of IO types, including
-* analog, digital, user-defined (real), and 'null'.
-*
-* The circuit demonstrates the use of the digital and
-* user-defined node capability to model system-level designs
-* such as sampled-data filters.  The simulated circuit
-* contains a digital oscillator enabled after 100us.  The
-* square wave oscillator output is divided by 8 with a
-* ripple counter.  The result is passed through a digital
-* filter to convert it to a sine wave.
-*
-.tran 1e-5 1e-3
-*
-v1 1 0 0.0 pulse(0 1 1e-4 1e-6)
-r1 1 0 1k
-*
-abridge1 [1] [enable] atod
-.model atod adc_bridge
-*
-aclk [enable clk] clk nand
-.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
-*
-adiv2 div2_out clk NULL NULL NULL div2_out dff
-adiv4 div4_out div2_out NULL NULL NULL div4_out dff
-adiv8 div8_out div4_out NULL NULL NULL div8_out dff
-.model dff d_dff
-*
-abridge2 div8_out enable filt_in node_bridge2
-.model node_bridge2 d_to_real (zero=-1 one=1)
-*
-xfilter  filt_in clk filt_out  dig_filter
-*
-abridge3 filt_out a_out node_bridge3
-.model node_bridge3 real_to_v
-*
-rlpf1 a_out oa_minus 10k
-*
-xlpf  0 oa_minus lpf_out  opamp
-*
-rlpf2 oa_minus lpf_out 10k
-clpf  lpf_out oa_minus 0.01uF
-*
-*
-.subckt  dig_filter  filt_in clk filt_out
-*
-.model n0 real_gain (gain=1.0)
-.model n1 real_gain (gain=2.0)
-.model n2 real_gain (gain=1.0)
-.model g1 real_gain (gain=0.125)
-.model zm1 real_delay
-.model d0a real_gain (gain=-0.75)
-.model d1a real_gain (gain=0.5625)
-.model d0b real_gain (gain=-0.3438)
-.model d1b real_gain (gain=1.0)
-*
-an0a filt_in x0a n0
-an1a filt_in x1a n1
-an2a filt_in x2a n2
-*
-az0a x0a clk x1a zm1
-az1a x1a clk x2a zm1
-*
-ad0a x2a x0a d0a
-ad1a x2a x1a d1a
-*
-az2a x2a filt1_out g1
-az3a filt1_out clk filt2_in zm1
-*
-an0b filt2_in x0b n0
-an1b filt2_in x1b n1
-an2b filt2_in x2b n2
-*
-az0b x0b clk x1b zm1
-az1b x1b clk x2b zm1
-*
-ad0 x2b x0b d0b
-ad1 x2b x1b d1b
-*
-az2b x2b clk filt_out zm1
-*
-.ends dig_filter
-*
-*
-.subckt  opamp  plus minus out
-*
-r1 plus minus 300k
-a1 %vd (plus minus) outint lim
-.model lim limit (out_lower_limit = -12 out_upper_limit = 12
-+             fraction = true  limit_range = 0.2  gain=300e3)
-r3 outint out 50.0
-r2 out 0 1e12
-*
-.ends opamp
-*
-*
-.end
+Mixed IO types
+*
+* This circuit contains a mixture of IO types, including
+* analog, digital, user-defined (real), and 'null'.
+*
+* The circuit demonstrates the use of the digital and
+* user-defined node capability to model system-level designs
+* such as sampled-data filters.  The simulated circuit
+* contains a digital oscillator enabled after 100us.  The
+* square wave oscillator output is divided by 8 with a
+* ripple counter.  The result is passed through a digital
+* filter to convert it to a sine wave.
+*
+.tran 1e-5 1e-3
+*
+v1 1 0 0.0 pulse(0 1 1e-4 1e-6)
+r1 1 0 1k
+*
+abridge1 [1] [enable] atod
+.model atod adc_bridge
+*
+aclk [enable clk] clk nand
+.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
+*
+adiv2 div2_out clk NULL NULL NULL div2_out dff
+adiv4 div4_out div2_out NULL NULL NULL div4_out dff
+adiv8 div8_out div4_out NULL NULL NULL div8_out dff
+.model dff d_dff
+*
+abridge2 div8_out enable filt_in node_bridge2
+.model node_bridge2 d_to_real (zero=-1 one=1)
+*
+xfilter  filt_in clk filt_out  dig_filter
+*
+abridge3 filt_out a_out node_bridge3
+.model node_bridge3 real_to_v
+*
+rlpf1 a_out oa_minus 10k
+*
+xlpf  0 oa_minus lpf_out  opamp
+*
+rlpf2 oa_minus lpf_out 10k
+clpf  lpf_out oa_minus 0.01uF
+*
+*
+.subckt  dig_filter  filt_in clk filt_out
+*
+.model n0 real_gain (gain=1.0)
+.model n1 real_gain (gain=2.0)
+.model n2 real_gain (gain=1.0)
+.model g1 real_gain (gain=0.125)
+.model zm1 real_delay
+.model d0a real_gain (gain=-0.75)
+.model d1a real_gain (gain=0.5625)
+.model d0b real_gain (gain=-0.3438)
+.model d1b real_gain (gain=1.0)
+*
+an0a filt_in x0a n0
+an1a filt_in x1a n1
+an2a filt_in x2a n2
+*
+az0a x0a clk x1a zm1
+az1a x1a clk x2a zm1
+*
+ad0a x2a x0a d0a
+ad1a x2a x1a d1a
+*
+az2a x2a filt1_out g1
+az3a filt1_out clk filt2_in zm1
+*
+an0b filt2_in x0b n0
+an1b filt2_in x1b n1
+an2b filt2_in x2b n2
+*
+az0b x0b clk x1b zm1
+az1b x1b clk x2b zm1
+*
+ad0 x2b x0b d0b
+ad1 x2b x1b d1b
+*
+az2b x2b clk filt_out zm1
+*
+.ends dig_filter
+*
+*
+.subckt  opamp  plus minus out
+*
+r1 plus minus 300k
+a1 %vd (plus minus) outint lim
+.model lim limit (out_lower_limit = -12 out_upper_limit = 12
++             fraction = true  limit_range = 0.2  gain=300e3)
+r3 outint out 50.0
+r2 out 0 1e12
+*
+.ends opamp
+*
+*
+.end

src/xspice/examples/mixed_ref.deck

@@ -1,41 +1,41 @@
-Mixed references
-*
-* This circuit demonstrates the use of single-ended and
-* differential inputs and outputs.
-*
-* Note that digital models reference a single node for
-* their inputs and output (i.e. they are single-ended)
-*
-.tran 1e-5 1e-3
-*
-v1  1 0  0.0 sin(0 1 5k)
-v2  2 0  0.0 sin(0 1 1k)
-*
-r1  1 0  1k
-r2  2 0  1k
-*
-*
-a1  %v 1  %i 10  times10
-r10  10 0  1k
-*
-*
-a2  %vd (1 2)  %id(11 12)  times10
-r11  11 0  1k
-r12  12 0  1k
-r11_12  11 12  1.0
-*
-*
-r3  2 3  1k
-a3  %i 3  %v 13  times10
-r13  13 0  1k
-*
-a4  [1] [digital_node1]  adc
-.model adc adc_bridge
-*
-a5  digital_node1 digital_node2  inv
-.model inv d_inverter
-*
-*
-.model times10 gain (gain=10)
-*
-.end
+Mixed references
+*
+* This circuit demonstrates the use of single-ended and
+* differential inputs and outputs.
+*
+* Note that digital models reference a single node for
+* their inputs and output (i.e. they are single-ended)
+*
+.tran 1e-5 1e-3
+*
+v1  1 0  0.0 sin(0 1 5k)
+v2  2 0  0.0 sin(0 1 1k)
+*
+r1  1 0  1k
+r2  2 0  1k
+*
+*
+a1  %v 1  %i 10  times10
+r10  10 0  1k
+*
+*
+a2  %vd (1 2)  %id(11 12)  times10
+r11  11 0  1k
+r12  12 0  1k
+r11_12  11 12  1.0
+*
+*
+r3  2 3  1k
+a3  %i 3  %v 13  times10
+r13  13 0  1k
+*
+a4  [1] [digital_node1]  adc
+.model adc adc_bridge
+*
+a5  digital_node1 digital_node2  inv
+.model inv d_inverter
+*
+*
+.model times10 gain (gain=10)
+*
+.end

src/xspice/examples/mosamp2.in

@@ -1,42 +1,42 @@
-mosamp2 - mos amplifier - transient
-.options acct abstol=10n  vntol=10n
-.tran 0.1us 10us
-m1  15 15  1 32 m w=88.9u  l=25.4u
-m2   1  1  2 32 m w=12.7u  l=266.7u
-m3   2  2 30 32 m w=88.9u  l=25.4u
-m4  15  5  4 32 m w=12.7u  l=106.7u
-m5   4  4 30 32 m w=88.9u  l=12.7u
-m6  15 15  5 32 m w=44.5u  l=25.4u
-m7   5 20  8 32 m w=482.6u l=12.7u
-m8   8  2 30 32 m w=88.9u  l=25.4u
-m9  15 15  6 32 m w=44.5u  l=25.4u
-m10  6 21  8 32 m w=482.6u l=12.7u
-m11 15  6  7 32 m w=12.7u  l=106.7u
-m12  7  4 30 32 m w=88.9u  l=12.7u
-m13 15 10  9 32 m w=139.7u l=12.7u
-m14  9 11 30 32 m w=139.7u l=12.7u
-m15 15 15 12 32 m w=12.7u  l=207.8u
-m16 12 12 11 32 m w=54.1u  l=12.7u
-m17 11 11 30 32 m w=54.1u  l=12.7u
-m18 15 15 10 32 m w=12.7u  l=45.2u
-m19 10 12 13 32 m w=270.5u l=12.7u
-m20 13  7 30 32 m w=270.5u l=12.7u
-m21 15 10 14 32 m w=254u   l=12.7u
-m22 14 11 30 32 m w=241.3u l=12.7u
-m23 15 20 16 32 m w=19u    l=38.1u
-m24 16 14 30 32 m w=406.4u l=12.7u
-m25 15 15 20 32 m w=38.1u  l=42.7u
-m26 20 16 30 32 m w=381u   l=25.4u
-m27 20 15 66 32 m w=22.9u  l=7.6u
-cc 7 9 40pf
-cl 66 0 70pf
-vin 21 0 pulse(0 5 1ns 1ns 1ns 5us 10us)
-vccp 15 0 dc +15
-vddn 30 0 dc -15
-vb 32 0 dc -20
-.model m nmos(nsub=2.2e15 uo=575 ucrit=49k uexp=0.1 tox=0.11u xj=2.95u
-+   level=2 cgso=1.5n cgdo=1.5n cbd=4.5f cbs=4.5f ld=2.4485u nss=3.2e10
-+   kp=2e-5 phi=0.6 )
-.print tran v(20) v(66)
-.plot  tran v(20) v(66)
-.end 
+mosamp2 - mos amplifier - transient
+.options acct abstol=10n  vntol=10n
+.tran 0.1us 10us
+m1  15 15  1 32 m w=88.9u  l=25.4u
+m2   1  1  2 32 m w=12.7u  l=266.7u
+m3   2  2 30 32 m w=88.9u  l=25.4u
+m4  15  5  4 32 m w=12.7u  l=106.7u
+m5   4  4 30 32 m w=88.9u  l=12.7u
+m6  15 15  5 32 m w=44.5u  l=25.4u
+m7   5 20  8 32 m w=482.6u l=12.7u
+m8   8  2 30 32 m w=88.9u  l=25.4u
+m9  15 15  6 32 m w=44.5u  l=25.4u
+m10  6 21  8 32 m w=482.6u l=12.7u
+m11 15  6  7 32 m w=12.7u  l=106.7u
+m12  7  4 30 32 m w=88.9u  l=12.7u
+m13 15 10  9 32 m w=139.7u l=12.7u
+m14  9 11 30 32 m w=139.7u l=12.7u
+m15 15 15 12 32 m w=12.7u  l=207.8u
+m16 12 12 11 32 m w=54.1u  l=12.7u
+m17 11 11 30 32 m w=54.1u  l=12.7u
+m18 15 15 10 32 m w=12.7u  l=45.2u
+m19 10 12 13 32 m w=270.5u l=12.7u
+m20 13  7 30 32 m w=270.5u l=12.7u
+m21 15 10 14 32 m w=254u   l=12.7u
+m22 14 11 30 32 m w=241.3u l=12.7u
+m23 15 20 16 32 m w=19u    l=38.1u
+m24 16 14 30 32 m w=406.4u l=12.7u
+m25 15 15 20 32 m w=38.1u  l=42.7u
+m26 20 16 30 32 m w=381u   l=25.4u
+m27 20 15 66 32 m w=22.9u  l=7.6u
+cc 7 9 40pf
+cl 66 0 70pf
+vin 21 0 pulse(0 5 1ns 1ns 1ns 5us 10us)
+vccp 15 0 dc +15
+vddn 30 0 dc -15
+vb 32 0 dc -20
+.model m nmos(nsub=2.2e15 uo=575 ucrit=49k uexp=0.1 tox=0.11u xj=2.95u
++   level=2 cgso=1.5n cgdo=1.5n cbd=4.5f cbs=4.5f ld=2.4485u nss=3.2e10
++   kp=2e-5 phi=0.6 )
+.print tran v(20) v(66)
+.plot  tran v(20) v(66)
+.end 

src/xspice/examples/mosmem.in

@@ -1,27 +1,27 @@
-mosmem - mos memory cell
-.width in=72
-.opt abstol=1u
-.opt acct list node
-.tran 20ns 2us
-vdd 9 0 dc 5
-vs 7 0 pulse(2 0 520ns 20ns 20ns 500ns 2000ns)
-vw 1 0 pulse(0 2 20ns 20ns 500ns 200ns)
-vwb 2 0 pulse(2 0 20ns 20ns 20ns 2000ns 2000ns)
-m1 3 1 0 0 mod w=250u l=5u
-m2 4 2 0 0 mod w=250u l=5u
-m3 9 9 3 0 mod w=5u   l=5u
-m4 9 9 4 0 mod w=5u   l=5u
-m5 5 7 3 0 mod w=50u  l=5u
-m6 6 7 4 0 mod w=50u  l=5u
-m7 5 6 0 0 mod w=250u  l=5u
-m8 6 5 0 0 mod w=250u  l=5u
-m9 9 9 5 0 mod w=5u   l=5u
-m10 9 9 6 0 mod w=5u  l=5u
-m11 8 4 0 0 mod w=250u l=5u
-m12 9 9 8 0 mod w=5u   l=5u
-.model mod nmos(vto=0.5 phi=0.7 kp=1.0e-6 gamma=1.83 lambda=0.115
-+   level=1 cgso=1u cgdo=1u cbd=50p cbs=50p)
-.print dc v(5) v(6)
-.plot dc v(6)
-.plot tran v(6) v(5) v(7) v(1) v(2)
-.end
+mosmem - mos memory cell
+.width in=72
+.opt abstol=1u
+.opt acct list node
+.tran 20ns 2us
+vdd 9 0 dc 5
+vs 7 0 pulse(2 0 520ns 20ns 20ns 500ns 2000ns)
+vw 1 0 pulse(0 2 20ns 20ns 500ns 200ns)
+vwb 2 0 pulse(2 0 20ns 20ns 20ns 2000ns 2000ns)
+m1 3 1 0 0 mod w=250u l=5u
+m2 4 2 0 0 mod w=250u l=5u
+m3 9 9 3 0 mod w=5u   l=5u
+m4 9 9 4 0 mod w=5u   l=5u
+m5 5 7 3 0 mod w=50u  l=5u
+m6 6 7 4 0 mod w=50u  l=5u
+m7 5 6 0 0 mod w=250u  l=5u
+m8 6 5 0 0 mod w=250u  l=5u
+m9 9 9 5 0 mod w=5u   l=5u
+m10 9 9 6 0 mod w=5u  l=5u
+m11 8 4 0 0 mod w=250u l=5u
+m12 9 9 8 0 mod w=5u   l=5u
+.model mod nmos(vto=0.5 phi=0.7 kp=1.0e-6 gamma=1.83 lambda=0.115
++   level=1 cgso=1u cgdo=1u cbd=50p cbs=50p)
+.print dc v(5) v(6)
+.plot dc v(6)
+.plot tran v(6) v(5) v(7) v(1) v(2)
+.end

src/xspice/examples/param_defaults.deck

@@ -1,16 +1,16 @@
-Parameter defaults
-*
-* This circuit contains a code model with
-* parameters of various types, which are all defaulted,
-* and prints the default values.
-*
-.op
-*
-r1 1 0 1k
-r2 2 0 1k
-r3 1 2 1k
-*
-a1 [1 2] mod
-.model mod print_param_types 
-*
-.end
+Parameter defaults
+*
+* This circuit contains a code model with
+* parameters of various types, which are all defaulted,
+* and prints the default values.
+*
+.op
+*
+r1 1 0 1k
+r2 2 0 1k
+r3 1 2 1k
+*
+a1 [1 2] mod
+.model mod print_param_types 
+*
+.end

src/xspice/examples/param_types.deck

@@ -1,23 +1,23 @@
-Parameter types
-*
-* This circuit contains a code model which accepts several
-* parameters of various types and prints them.
-*
-.op
-*
-r1 1 0 1k
-r2 2 0 1k
-r3 1 2 1k
-*
-a1 [1 2] mod
-.model mod print_param_types 
-+  integer=2
-+  real=3.0
-+  complex=<4.0 5.0>
-+  string=six
-+  integer_array=[7 8]
-+  real_array=[9.0 10.0]
-+  complex_array=[< 11.0 12.0 > < 13.0 14.0 >]
-+  string_array=[fifteen sixteen]
-*
-.end
+Parameter types
+*
+* This circuit contains a code model which accepts several
+* parameters of various types and prints them.
+*
+.op
+*
+r1 1 0 1k
+r2 2 0 1k
+r3 1 2 1k
+*
+a1 [1 2] mod
+.model mod print_param_types 
++  integer=2
++  real=3.0
++  complex=<4.0 5.0>
++  string=six
++  integer_array=[7 8]
++  real_array=[9.0 10.0]
++  complex_array=[< 11.0 12.0 > < 13.0 14.0 >]
++  string_array=[fifteen sixteen]
+*
+.end

src/xspice/examples/parsing.deck

@@ -1,16 +1,16 @@
-Parsing
-*
-* This circuit contains a simple gain block to demonstrate
-* that the simulator parses the syntax used to reference
-* code models.
-*
-.tran 1e-5 1e-3
-*
-v1 1 0 0.0 sin(0 1 1k)
-r1 1 0 1k
-*
-a1 1 2 gain_block
-.model gain_block gain (gain=10)
-r2 2 0 1k
-*
-.end
+Parsing
+*
+* This circuit contains a simple gain block to demonstrate
+* that the simulator parses the syntax used to reference
+* code models.
+*
+.tran 1e-5 1e-3
+*
+v1 1 0 0.0 sin(0 1 1k)
+r1 1 0 1k
+*
+a1 1 2 gain_block
+.model gain_block gain (gain=10)
+r2 2 0 1k
+*
+.end

src/xspice/examples/polarity.deck

@@ -1,26 +1,26 @@
-Polarity of voltages and currents
-*
-* This circuit contains a set of gain blocks to evaluate
-* the polarity of voltages and currents on code models
-*
-.tran 1e-5 1e-3
-*
-v1  1 0  0.0 sin(0 1 1k)
-*
-r1  1 0  1k
-*
-*
-a1  %v 1  %v 10  times10
-r10  10 0  1k
-*
-r1_2  1 2  1k
-a2  %i 2  %v 11  times10
-r11  11 0  1k
-*
-a3  1  %i 12  times10
-r12  12 0  1k
-*
-*
-.model times10 gain (gain=10)
-*
-.end
+Polarity of voltages and currents
+*
+* This circuit contains a set of gain blocks to evaluate
+* the polarity of voltages and currents on code models
+*
+.tran 1e-5 1e-3
+*
+v1  1 0  0.0 sin(0 1 1k)
+*
+r1  1 0  1k
+*
+*
+a1  %v 1  %v 10  times10
+r10  10 0  1k
+*
+r1_2  1 2  1k
+a2  %i 2  %v 11  times10
+r11  11 0  1k
+*
+a3  1  %i 12  times10
+r12  12 0  1k
+*
+*
+.model times10 gain (gain=10)
+*
+.end

src/xspice/examples/schmitt.in

@@ -1,24 +1,24 @@
-schmitt ckt - ecl compatible schmitt trigger
-.width in=72
-.opt acct list node lvlcod=2
-.tran 10ns 1000ns
-vin 1 0 pulse(-1.6 -1.2 10ns 400ns 400ns 100ns 10000ns)
-vee 8 0 -5
-rin 1 2 50
-rc1 0 3 50
-r1 3 5 185
-r2 5 8 760
-rc2 0 6 100
-re 4 8 260
-rth1 7 8 125
-rth2 7 0 85
-cload 7 0 5pf
-q1 3 2 4 qstd off
-q2 6 5 4 qstd
-q3 0 6 7 qstd
-q4 0 6 7 qstd
-.model qstd npn(is=1.0e-16 bf=50 br=0.1 rb=50 rc=10 tf=0.12ns tr=5ns
-+   cje=0.4pf pe=0.8 me=0.4 cjc=0.5pf pc=0.8 mc=0.333 ccs=1pf va=50)
-.print tran v(1) v(3) v(5) v(6)
-.plot tran v(3) v(5) v(6) v(1)
-.end
+schmitt ckt - ecl compatible schmitt trigger
+.width in=72
+.opt acct list node lvlcod=2
+.tran 10ns 1000ns
+vin 1 0 pulse(-1.6 -1.2 10ns 400ns 400ns 100ns 10000ns)
+vee 8 0 -5
+rin 1 2 50
+rc1 0 3 50
+r1 3 5 185
+r2 5 8 760
+rc2 0 6 100
+re 4 8 260
+rth1 7 8 125
+rth2 7 0 85
+cload 7 0 5pf
+q1 3 2 4 qstd off
+q2 6 5 4 qstd
+q3 0 6 7 qstd
+q4 0 6 7 qstd
+.model qstd npn(is=1.0e-16 bf=50 br=0.1 rb=50 rc=10 tf=0.12ns tr=5ns
++   cje=0.4pf pe=0.8 me=0.4 cjc=0.5pf pc=0.8 mc=0.333 ccs=1pf va=50)
+.print tran v(1) v(3) v(5) v(6)
+.plot tran v(3) v(5) v(6) v(1)
+.end

src/xspice/examples/spice3.deck

@@ -1,25 +1,25 @@
-A Berkeley SPICE3 compatible circuit
-*
-* This circuit contains only Berkeley SPICE3 components.
-*
-* The circuit is an AC coupled transistor amplifier with
-* a sinewave input at node "1", a gain of approximately -3.9,
-* and output on node "coll".
-*
-.tran 1e-5 2e-3
-*
-vcc  vcc 0  12.0
-vin  1 0  0.0 ac 1.0 sin(0 1 1k)
-*
-ccouple  1 base  10uF
-*
-rbias1  vcc base  100k
-rbias2  base 0  24k
-*
-q1  coll base emit  generic
-.model generic npn
-*
-rcollector  vcc coll  3.9k
-remitter  emit 0  1k
-*
-.end
+A Berkeley SPICE3 compatible circuit
+*
+* This circuit contains only Berkeley SPICE3 components.
+*
+* The circuit is an AC coupled transistor amplifier with
+* a sinewave input at node "1", a gain of approximately -3.9,
+* and output on node "coll".
+*
+.tran 1e-5 2e-3
+*
+vcc  vcc 0  12.0
+vin  1 0  0.0 ac 1.0 sin(0 1 1k)
+*
+ccouple  1 base  10uF
+*
+rbias1  vcc base  100k
+rbias2  base 0  24k
+*
+q1  coll base emit  generic
+.model generic npn
+*
+rcollector  vcc coll  3.9k
+remitter  emit 0  1k
+*
+.end

src/xspice/examples/suffixes.deck

@@ -1,25 +1,25 @@
-Engineering suffixes
-*
-* This circuit contains a code model which accepts several
-* parameters of various types and prints them.  The values
-* specified on the .model card use engineering suffixes on
-* the numeric parameters.
-*
-.op
-*
-r1 1 0 1k
-r2 2 0 1k
-r3 1 2 1k
-*
-a1 [1 2] mod
-.model mod print_param_types 
-+  integer=2k
-+  real=3.0u
-+  complex=< 4.0f 5.0mil >
-+  string=six
-+  integer_array=[7meg 8]
-+  real_array=[9.0n 10.0p]
-+  complex_array=[< 11.0t 12.0g > < 13.0m 14.0 >]
-+  string_array=[fifteen sixteen]
-*
-.end
+Engineering suffixes
+*
+* This circuit contains a code model which accepts several
+* parameters of various types and prints them.  The values
+* specified on the .model card use engineering suffixes on
+* the numeric parameters.
+*
+.op
+*
+r1 1 0 1k
+r2 2 0 1k
+r3 1 2 1k
+*
+a1 [1 2] mod
+.model mod print_param_types 
++  integer=2k
++  real=3.0u
++  complex=< 4.0f 5.0mil >
++  string=six
++  integer_array=[7meg 8]
++  real_array=[9.0n 10.0p]
++  complex_array=[< 11.0t 12.0g > < 13.0m 14.0 >]
++  string_array=[fifteen sixteen]
+*
+.end

src/xspice/examples/supply_ramping.deck

@@ -1,30 +1,30 @@
-Supply ramping option
-*
-* This circuit demonstrates the use of the option
-* "ramptime" which ramps independent sources and the
-* capacitor and inductor initial conditions from 
-* zero to their final value during the time period
-* specified.
-*
-*
-.tran 0.1 5
-.option ramptime=0.2
-*
-a1 1 0 cap
-.model cap capacitor (c=1000uf ic=1)
-r1 1 0 1k
-*
-a2 2 0 ind
-.model ind inductor (l=1H ic=1)
-r2 2 0 1.0
-*
-v1 3 0 1.0
-r3 3 0 1k
-*
-i1 4 0 1e-3
-r4 4 0 1k
-*
-v2 5 0 0.0  sin(0 1 0.3 0 0 45.0)
-r5 5 0 1k
-*
-.end
+Supply ramping option
+*
+* This circuit demonstrates the use of the option
+* "ramptime" which ramps independent sources and the
+* capacitor and inductor initial conditions from 
+* zero to their final value during the time period
+* specified.
+*
+*
+.tran 0.1 5
+.option ramptime=0.2
+*
+a1 1 0 cap
+.model cap capacitor (c=1000uf ic=1)
+r1 1 0 1k
+*
+a2 2 0 ind
+.model ind inductor (l=1H ic=1)
+r2 2 0 1.0
+*
+v1 3 0 1.0
+r3 3 0 1k
+*
+i1 4 0 1e-3
+r4 4 0 1k
+*
+v2 5 0 0.0  sin(0 1 0.3 0 0 45.0)
+r5 5 0 1k
+*
+.end

src/xspice/examples/user_defined_nodes.deck

@@ -1,30 +1,30 @@
-User defined nodes
-*
-* This circuit contains a mix of node types including
-* two 'real' type user-defined nodes and associated
-* node bridges.
-*
-.tran 1e-6 1e-4
-*
-v1  1 0  0.0 pulse(0 1 2e-5)
-r1  1 0  1k
-*
-abridge1  [1] [enable]  node_bridge1
-.model node_bridge1 adc_bridge
-*
-aclk  [enable clk] clk  nand
-.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
-*
-abridge2  clk enable real_node1  node_bridge2
-.model node_bridge2 d_to_real (zero=-1 one=1)
-*
-again  real_node1 real_node2  times10
-.model times10 real_gain (gain=10)
-*
-abridge3  real_node2 analog_node  node_bridge3
-.model node_bridge3 real_to_v
-*
-rout  analog_node 0  1k
-*
-*
-.end
+User defined nodes
+*
+* This circuit contains a mix of node types including
+* two 'real' type user-defined nodes and associated
+* node bridges.
+*
+.tran 1e-6 1e-4
+*
+v1  1 0  0.0 pulse(0 1 2e-5)
+r1  1 0  1k
+*
+abridge1  [1] [enable]  node_bridge1
+.model node_bridge1 adc_bridge
+*
+aclk  [enable clk] clk  nand
+.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5)
+*
+abridge2  clk enable real_node1  node_bridge2
+.model node_bridge2 d_to_real (zero=-1 one=1)
+*
+again  real_node1 real_node2  times10
+.model times10 real_gain (gain=10)
+*
+abridge3  real_node2 analog_node  node_bridge3
+.model node_bridge3 real_to_v
+*
+rout  analog_node 0  1k
+*
+*
+.end

src/xspice/examples/xspice.deck

@@ -1,22 +1,22 @@
-A simple XSPICE amplifier circuit
-*
-* This uses an XSPICE "gain" code model to substitute for
-* the transistor amplifier circuit in spice3.deck.
-*
-.tran 1e-5 2e-3
-*
-vin  1 0  0.0 ac 1.0 sin(0 1 1k)
-*
-ccouple  1 in  10uF
-*
-*
-rzin  in 0  19.35k
-*
-aamp  in coll  gain_block
-.model gain_block gain (gain = -3.9  out_offset = 7.003)
-*
-rzout out coll 3.9k
-rbig  coll 0   1e12
-*
-*
-.end
+A simple XSPICE amplifier circuit
+*
+* This uses an XSPICE "gain" code model to substitute for
+* the transistor amplifier circuit in spice3.deck.
+*
+.tran 1e-5 2e-3
+*
+vin  1 0  0.0 ac 1.0 sin(0 1 1k)
+*
+ccouple  1 in  10uF
+*
+*
+rzin  in 0  19.35k
+*
+aamp  in coll  gain_block
+.model gain_block gain (gain = -3.9  out_offset = 7.003)
+*
+rzout out coll 3.9k
+rbig  coll 0   1e12
+*
+*
+.end