From dc6340f8bcbfd16bb530c37270d1f6d012ecde39 Mon Sep 17 00:00:00 2001 From: pnenzi Date: Mon, 11 Aug 2003 19:54:07 +0000 Subject: [PATCH] Bsim 3v1 (Alan Gillespie version). Import. --- src/spicelib/devices/bsim3v1a/Makefile.am | 33 + src/spicelib/devices/bsim3v1a/b3v1a.c | 434 ++++ src/spicelib/devices/bsim3v1a/b3v1aacld.c | 184 ++ src/spicelib/devices/bsim3v1a/b3v1aask.c | 223 ++ src/spicelib/devices/bsim3v1a/b3v1acvtest.c | 91 + src/spicelib/devices/bsim3v1a/b3v1adel.c | 39 + src/spicelib/devices/bsim3v1a/b3v1adest.c | 37 + src/spicelib/devices/bsim3v1a/b3v1agetic.c | 45 + src/spicelib/devices/bsim3v1a/b3v1ald.c | 1947 ++++++++++++++++++ src/spicelib/devices/bsim3v1a/b3v1amask.c | 1087 ++++++++++ src/spicelib/devices/bsim3v1a/b3v1amdel.c | 43 + src/spicelib/devices/bsim3v1a/b3v1ampar.c | 1483 +++++++++++++ src/spicelib/devices/bsim3v1a/b3v1anoi.c | 357 ++++ src/spicelib/devices/bsim3v1a/b3v1apar.c | 97 + src/spicelib/devices/bsim3v1a/b3v1apzld.c | 152 ++ src/spicelib/devices/bsim3v1a/b3v1aset.c | 928 +++++++++ src/spicelib/devices/bsim3v1a/b3v1atemp.c | 632 ++++++ src/spicelib/devices/bsim3v1a/b3v1atrunc.c | 51 + src/spicelib/devices/bsim3v1a/bsim3v1adef.h | 1580 ++++++++++++++ src/spicelib/devices/bsim3v1a/bsim3v1aext.h | 30 + src/spicelib/devices/bsim3v1a/bsim3v1ainit.c | 85 + src/spicelib/devices/bsim3v1a/bsim3v1ainit.h | 13 + src/spicelib/devices/bsim3v1a/bsim3v1aitf.h | 14 + 23 files changed, 9585 insertions(+) create mode 100644 src/spicelib/devices/bsim3v1a/Makefile.am create mode 100644 src/spicelib/devices/bsim3v1a/b3v1a.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1aacld.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1aask.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1acvtest.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1adel.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1adest.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1agetic.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1ald.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1amask.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1amdel.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1ampar.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1anoi.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1apar.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1apzld.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1aset.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1atemp.c create mode 100644 src/spicelib/devices/bsim3v1a/b3v1atrunc.c create mode 100644 src/spicelib/devices/bsim3v1a/bsim3v1adef.h create mode 100644 src/spicelib/devices/bsim3v1a/bsim3v1aext.h create mode 100644 src/spicelib/devices/bsim3v1a/bsim3v1ainit.c create mode 100644 src/spicelib/devices/bsim3v1a/bsim3v1ainit.h create mode 100644 src/spicelib/devices/bsim3v1a/bsim3v1aitf.h diff --git a/src/spicelib/devices/bsim3v1a/Makefile.am b/src/spicelib/devices/bsim3v1a/Makefile.am new file mode 100644 index 000000000..f4e4a77bd --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/Makefile.am @@ -0,0 +1,33 @@ +## Process this file with automake to produce Makefile.in + +noinst_LIBRARIES = libbsim3v1a.a + +libbsim3v1a_a_SOURCES = \ + b3v1a.c \ + b3v1aacld.c \ + b3v1aask.c \ + b3v1acvtest.c \ + b3v1adel.c \ + b3v1adest.c \ + b3v1agetic.c \ + b3v1ald.c \ + b3v1amask.c \ + b3v1amdel.c \ + b3v1ampar.c \ + b3v1anoi.c \ + b3v1apar.c \ + b3v1apzld.c \ + b3v1aset.c \ + b3v1atemp.c \ + b3v1atrunc.c \ + bsim3v1adef.h \ + bsim3v1aext.h \ + bsim3v1ainit.c \ + bsim3v1ainit.h \ + bsim3v1aitf.h + + + +INCLUDES = -I$(top_srcdir)/src/include + +MAINTAINERCLEANFILES = Makefile.in diff --git a/src/spicelib/devices/bsim3v1a/b3v1a.c b/src/spicelib/devices/bsim3v1a/b3v1a.c new file mode 100644 index 000000000..8fbc37bfe --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1a.c @@ -0,0 +1,434 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1a.c +**********/ + +#include "ngspice.h" +#include "devdefs.h" +#include "bsim3v1adef.h" +#include "suffix.h" + +IFparm BSIM3v1ApTable[] = { /* parameters */ +IOP( "l", BSIM3v1A_L, IF_REAL , "Length"), +IOP( "w", BSIM3v1A_W, IF_REAL , "Width"), +IOP( "m", BSIM3v1A_M, IF_REAL , "Parallel multiplier"), +IOP( "ad", BSIM3v1A_AD, IF_REAL , "Drain area"), +IOP( "as", BSIM3v1A_AS, IF_REAL , "Source area"), +IOP( "pd", BSIM3v1A_PD, IF_REAL , "Drain perimeter"), +IOP( "ps", BSIM3v1A_PS, IF_REAL , "Source perimeter"), +IOP( "nrd", BSIM3v1A_NRD, IF_REAL , "Number of squares in drain"), +IOP( "nrs", BSIM3v1A_NRS, IF_REAL , "Number of squares in source"), +IOP( "off", BSIM3v1A_OFF, IF_FLAG , "Device is initially off"), +IOP( "nqsmod", BSIM3v1A_NQSMOD, IF_INTEGER, "Non-quasi-static model selector"), +IP( "ic", BSIM3v1A_IC, IF_REALVEC , "Vector of DS,GS,BS initial voltages"), +OP( "gmbs", BSIM3v1A_GMBS, IF_REAL, "Gmb"), +OP( "gm", BSIM3v1A_GM, IF_REAL, "Gm"), +OP( "gds", BSIM3v1A_GDS, IF_REAL, "Gds"), +OP( "vdsat", BSIM3v1A_VDSAT, IF_REAL, "Vdsat"), +OP( "vth", BSIM3v1A_VON, IF_REAL, "Vth"), +OP( "id", BSIM3v1A_CD, IF_REAL, "Ids"), +OP( "vbs", BSIM3v1A_VBS, IF_REAL, "Vbs"), +OP( "vgs", BSIM3v1A_VGS, IF_REAL, "Vgs"), +OP( "vds", BSIM3v1A_VDS, IF_REAL, "Vds"), +OP( "gbd", BSIM3v1A_GBD, IF_REAL, "Gbd"), +OP( "gbs", BSIM3v1A_GBS, IF_REAL, "Gbs"), +OP( "ibd", BSIM3v1A_CBD, IF_REAL, "Ibd"), +OP( "ibs", BSIM3v1A_CBS, IF_REAL, "Ibs"), +}; + +IFparm BSIM3v1AmPTable[] = { /* model parameters */ +IOP( "capmod", BSIM3v1A_MOD_CAPMOD, IF_INTEGER, "Capacitance model selector"), +IOP( "nqsmod", BSIM3v1A_MOD_NQSMOD, IF_INTEGER, "Non-quasi-static model selector"), +IOP( "mobmod", BSIM3v1A_MOD_MOBMOD, IF_INTEGER, "Mobility model selector"), +IOP( "noimod", BSIM3v1A_MOD_NOIMOD, IF_INTEGER, "Noise model selector"), +IOP( "binunit", BSIM3v1A_MOD_BINUNIT, IF_INTEGER, "Bin unit selector"), +IOP( "tox", BSIM3v1A_MOD_TOX, IF_REAL, "Gate oxide thickness in meters"), + +IOP( "cdsc", BSIM3v1A_MOD_CDSC, IF_REAL, "Drain/Source and channel coupling capacitance"), +IOP( "cdscb", BSIM3v1A_MOD_CDSCB, IF_REAL, "Body-bias dependence of cdsc"), +IOP( "cdscd", BSIM3v1A_MOD_CDSCD, IF_REAL, "Drain-bias dependence of cdsc"), +IOP( "cit", BSIM3v1A_MOD_CIT, IF_REAL, "Interface state capacitance"), +IOP( "nfactor", BSIM3v1A_MOD_NFACTOR, IF_REAL, "Subthreshold swing Coefficient"), +IOP( "xj", BSIM3v1A_MOD_XJ, IF_REAL, "Junction depth in meters"), +IOP( "vsat", BSIM3v1A_MOD_VSAT, IF_REAL, "Saturation velocity at tnom"), +IOP( "at", BSIM3v1A_MOD_AT, IF_REAL, "Temperature coefficient of vsat"), +IOP( "a0", BSIM3v1A_MOD_A0, IF_REAL, "Non-uniform depletion width effect coefficient."), +IOP( "ags", BSIM3v1A_MOD_AGS, IF_REAL, "Gate bias coefficient of Abulk."), +IOP( "a1", BSIM3v1A_MOD_A1, IF_REAL, "Non-saturation effect coefficient"), +IOP( "a2", BSIM3v1A_MOD_A2, IF_REAL, "Non-saturation effect coefficient"), +IOP( "keta", BSIM3v1A_MOD_KETA, IF_REAL, "Body-bias coefficient of non-uniform depletion width effect."), +IOP( "nsub", BSIM3v1A_MOD_NSUB, IF_REAL, "Substrate doping concentration"), +IOP( "nch", BSIM3v1A_MOD_NPEAK, IF_REAL, "Channel doping concentration"), +IOP( "ngate", BSIM3v1A_MOD_NGATE, IF_REAL, "Poly-gate doping concentration"), +IOP( "gamma1", BSIM3v1A_MOD_GAMMA1, IF_REAL, "Vth body coefficient"), +IOP( "gamma2", BSIM3v1A_MOD_GAMMA2, IF_REAL, "Vth body coefficient"), +IOP( "vbx", BSIM3v1A_MOD_VBX, IF_REAL, "Vth transition body Voltage"), +IOP( "vbm", BSIM3v1A_MOD_VBM, IF_REAL, "Maximum body voltage"), + +IOP( "xt", BSIM3v1A_MOD_XT, IF_REAL, "Doping depth"), +IOP( "k1", BSIM3v1A_MOD_K1, IF_REAL, "Bulk effect coefficient 1"), +IOP( "kt1", BSIM3v1A_MOD_KT1, IF_REAL, "Temperature coefficient of Vth"), +IOP( "kt1l", BSIM3v1A_MOD_KT1L, IF_REAL, "Temperature coefficient of Vth"), +IOP( "kt2", BSIM3v1A_MOD_KT2, IF_REAL, "Body-coefficient of kt1"), +IOP( "k2", BSIM3v1A_MOD_K2, IF_REAL, "Bulk effect coefficient 2"), +IOP( "k3", BSIM3v1A_MOD_K3, IF_REAL, "Narrow width effect coefficient"), +IOP( "k3b", BSIM3v1A_MOD_K3B, IF_REAL, "Body effect coefficient of k3"), +IOP( "w0", BSIM3v1A_MOD_W0, IF_REAL, "Narrow width effect parameter"), +IOP( "nlx", BSIM3v1A_MOD_NLX, IF_REAL, "Lateral non-uniform doping effect"), +IOP( "dvt0", BSIM3v1A_MOD_DVT0, IF_REAL, "Short channel effect coeff. 0"), +IOP( "dvt1", BSIM3v1A_MOD_DVT1, IF_REAL, "Short channel effect coeff. 1"), +IOP( "dvt2", BSIM3v1A_MOD_DVT2, IF_REAL, "Short channel effect coeff. 2"), +IOP( "dvt0w", BSIM3v1A_MOD_DVT0W, IF_REAL, "Narrow Width coeff. 0"), +IOP( "dvt1w", BSIM3v1A_MOD_DVT1W, IF_REAL, "Narrow Width effect coeff. 1"), +IOP( "dvt2w", BSIM3v1A_MOD_DVT2W, IF_REAL, "Narrow Width effect coeff. 2"), +IOP( "drout", BSIM3v1A_MOD_DROUT, IF_REAL, "DIBL coefficient of output resistance"), +IOP( "dsub", BSIM3v1A_MOD_DSUB, IF_REAL, "DIBL coefficient in the subthreshold region"), +IOP( "vth0", BSIM3v1A_MOD_VTH0, IF_REAL,"Threshold voltage"), +IOP( "vtho", BSIM3v1A_MOD_VTH0, IF_REAL,"Threshold voltage"), +IOP( "ua", BSIM3v1A_MOD_UA, IF_REAL, "Linear gate dependence of mobility"), +IOP( "ua1", BSIM3v1A_MOD_UA1, IF_REAL, "Temperature coefficient of ua"), +IOP( "ub", BSIM3v1A_MOD_UB, IF_REAL, "Quadratic gate dependence of mobility"), +IOP( "ub1", BSIM3v1A_MOD_UB1, IF_REAL, "Temperature coefficient of ub"), +IOP( "uc", BSIM3v1A_MOD_UC, IF_REAL, "Body-bias dependence of mobility"), +IOP( "uc1", BSIM3v1A_MOD_UC1, IF_REAL, "Temperature coefficient of uc"), +IOP( "u0", BSIM3v1A_MOD_U0, IF_REAL, "Low-field mobility at Tnom"), +IOP( "ute", BSIM3v1A_MOD_UTE, IF_REAL, "Temperature coefficient of mobility"), +IOP( "voff", BSIM3v1A_MOD_VOFF, IF_REAL, "Threshold voltage offset"), +IOP( "tnom", BSIM3v1A_MOD_TNOM, IF_REAL, "Parameter measurement temperature"), +IOP( "cgso", BSIM3v1A_MOD_CGSO, IF_REAL, "Gate-source overlap capacitance per width"), +IOP( "cgdo", BSIM3v1A_MOD_CGDO, IF_REAL, "Gate-drain overlap capacitance per width"), +IOP( "cgbo", BSIM3v1A_MOD_CGBO, IF_REAL, "Gate-bulk overlap capacitance per length"), +IOP( "xpart", BSIM3v1A_MOD_XPART, IF_REAL, "Channel charge partitioning"), +IOP( "elm", BSIM3v1A_MOD_ELM, IF_REAL, "Non-quasi-static Elmore Constant Parameter"), +IOP( "delta", BSIM3v1A_MOD_DELTA, IF_REAL, "Effective Vds parameter"), +IOP( "rsh", BSIM3v1A_MOD_RSH, IF_REAL, "Source-drain sheet resistance"), +IOP( "rdsw", BSIM3v1A_MOD_RDSW, IF_REAL, "Source-drain resistance per width"), + +IOP( "prwg", BSIM3v1A_MOD_PRWG, IF_REAL, "Gate-bias effect on parasitic resistance "), +IOP( "prwb", BSIM3v1A_MOD_PRWB, IF_REAL, "Body-effect on parasitic resistance "), + +IOP( "prt", BSIM3v1A_MOD_PRT, IF_REAL, "Temperature coefficient of parasitic resistance "), +IOP( "eta0", BSIM3v1A_MOD_ETA0, IF_REAL, "Subthreshold region DIBL coefficient"), +IOP( "etab", BSIM3v1A_MOD_ETAB, IF_REAL, "Subthreshold region DIBL coefficient"), +IOP( "pclm", BSIM3v1A_MOD_PCLM, IF_REAL, "Channel length modulation Coefficient"), +IOP( "pdiblc1", BSIM3v1A_MOD_PDIBL1, IF_REAL, "Drain-induced barrier lowering coefficient"), +IOP( "pdiblc2", BSIM3v1A_MOD_PDIBL2, IF_REAL, "Drain-induced barrier lowering coefficient"), +IOP( "pdiblcb", BSIM3v1A_MOD_PDIBLB, IF_REAL, "Body-effect on drain-induced barrier lowering"), +IOP( "pscbe1", BSIM3v1A_MOD_PSCBE1, IF_REAL, "Substrate current body-effect coefficient"), +IOP( "pscbe2", BSIM3v1A_MOD_PSCBE2, IF_REAL, "Substrate current body-effect coefficient"), +IOP( "pvag", BSIM3v1A_MOD_PVAG, IF_REAL, "Gate dependence of output resistance parameter"), +IOP( "js", BSIM3v1A_MOD_JS, IF_REAL, "Source/drain junction reverse saturation current density"), +IOP( "pb", BSIM3v1A_MOD_PB, IF_REAL, "Source/drain junction built-in potential"), +IOP( "mj", BSIM3v1A_MOD_MJ, IF_REAL, "Source/drain bottom junction capacitance grading coefficient"), +IOP( "pbsw", BSIM3v1A_MOD_PBSW, IF_REAL, "Source/drain sidewall junction capacitance built in potential"), +IOP( "mjsw", BSIM3v1A_MOD_MJSW, IF_REAL, "Source/drain sidewall junction capacitance grading coefficient"), +IOP( "cj", BSIM3v1A_MOD_CJ, IF_REAL, "Source/drain bottom junction capacitance per unit area"), +IOP( "cjsw", BSIM3v1A_MOD_CJSW, IF_REAL, "Source/drain sidewall junction capacitance per unit area"), + +IOP( "lint", BSIM3v1A_MOD_LINT, IF_REAL, "Length reduction parameter"), +IOP( "ll", BSIM3v1A_MOD_LL, IF_REAL, "Length reduction parameter"), +IOP( "lln", BSIM3v1A_MOD_LLN, IF_REAL, "Length reduction parameter"), +IOP( "lw", BSIM3v1A_MOD_LW, IF_REAL, "Length reduction parameter"), +IOP( "lwn", BSIM3v1A_MOD_LWN, IF_REAL, "Length reduction parameter"), +IOP( "lwl", BSIM3v1A_MOD_LWL, IF_REAL, "Length reduction parameter"), +IOP( "lmin", BSIM3v1A_MOD_LMIN, IF_REAL, "Minimum length for the model"), +IOP( "lmax", BSIM3v1A_MOD_LMAX, IF_REAL, "Maximum length for the model"), + +IOP( "wr", BSIM3v1A_MOD_WR, IF_REAL, "Width dependence of rds"), +IOP( "wint", BSIM3v1A_MOD_WINT, IF_REAL, "Width reduction parameter"), +IOP( "dwg", BSIM3v1A_MOD_DWG, IF_REAL, "Width reduction parameter"), +IOP( "dwb", BSIM3v1A_MOD_DWB, IF_REAL, "Width reduction parameter"), + +IOP( "wl", BSIM3v1A_MOD_WL, IF_REAL, "Width reduction parameter"), +IOP( "wln", BSIM3v1A_MOD_WLN, IF_REAL, "Width reduction parameter"), +IOP( "ww", BSIM3v1A_MOD_WW, IF_REAL, "Width reduction parameter"), +IOP( "wwn", BSIM3v1A_MOD_WWN, IF_REAL, "Width reduction parameter"), +IOP( "wwl", BSIM3v1A_MOD_WWL, IF_REAL, "Width reduction parameter"), +IOP( "wmin", BSIM3v1A_MOD_WMIN, IF_REAL, "Minimum width for the model"), +IOP( "wmax", BSIM3v1A_MOD_WMAX, IF_REAL, "Maximum width for the model"), + +IOP( "b0", BSIM3v1A_MOD_B0, IF_REAL, "Abulk narrow width parameter"), +IOP( "b1", BSIM3v1A_MOD_B1, IF_REAL, "Abulk narrow width parameter"), + +IOP( "cgsl", BSIM3v1A_MOD_CGSL, IF_REAL, "New C-V model parameter"), +IOP( "cgdl", BSIM3v1A_MOD_CGDL, IF_REAL, "New C-V model parameter"), +IOP( "ckappa", BSIM3v1A_MOD_CKAPPA, IF_REAL, "New C-V model parameter"), +IOP( "cf", BSIM3v1A_MOD_CF, IF_REAL, "Fringe capacitance parameter"), +IOP( "clc", BSIM3v1A_MOD_CLC, IF_REAL, "Vdsat parameter for C-V model"), +IOP( "cle", BSIM3v1A_MOD_CLE, IF_REAL, "Vdsat parameter for C-V model"), +IOP( "dwc", BSIM3v1A_MOD_DWC, IF_REAL, "Delta W for C-V model"), +IOP( "dlc", BSIM3v1A_MOD_DLC, IF_REAL, "Delta L for C-V model"), + +IOP( "alpha0", BSIM3v1A_MOD_ALPHA0, IF_REAL, "substrate current model parameter"), +IOP( "beta0", BSIM3v1A_MOD_BETA0, IF_REAL, "substrate current model parameter"), + +IOP( "lcdsc", BSIM3v1A_MOD_LCDSC, IF_REAL, "Length dependence of cdsc"), +IOP( "lcdscb", BSIM3v1A_MOD_LCDSCB, IF_REAL, "Length dependence of cdscb"), +IOP( "lcdscd", BSIM3v1A_MOD_LCDSCD, IF_REAL, "Length dependence of cdscd"), +IOP( "lcit", BSIM3v1A_MOD_LCIT, IF_REAL, "Length dependence of cit"), +IOP( "lnfactor", BSIM3v1A_MOD_LNFACTOR, IF_REAL, "Length dependence of nfactor"), +IOP( "lxj", BSIM3v1A_MOD_LXJ, IF_REAL, "Length dependence of xj"), +IOP( "lvsat", BSIM3v1A_MOD_LVSAT, IF_REAL, "Length dependence of vsat"), +IOP( "lat", BSIM3v1A_MOD_LAT, IF_REAL, "Length dependence of at"), +IOP( "la0", BSIM3v1A_MOD_LA0, IF_REAL, "Length dependence of a0"), +IOP( "lags", BSIM3v1A_MOD_LAGS, IF_REAL, "Length dependence of ags"), +IOP( "la1", BSIM3v1A_MOD_LA1, IF_REAL, "Length dependence of a1"), +IOP( "la2", BSIM3v1A_MOD_LA2, IF_REAL, "Length dependence of a2"), +IOP( "lketa", BSIM3v1A_MOD_LKETA, IF_REAL, "Length dependence of keta"), +IOP( "lnsub", BSIM3v1A_MOD_LNSUB, IF_REAL, "Length dependence of nsub"), +IOP( "lnch", BSIM3v1A_MOD_LNPEAK, IF_REAL, "Length dependence of nch"), +IOP( "lngate", BSIM3v1A_MOD_LNGATE, IF_REAL, "Length dependence of ngate"), +IOP( "lgamma1", BSIM3v1A_MOD_LGAMMA1, IF_REAL, "Length dependence of gamma1"), +IOP( "lgamma2", BSIM3v1A_MOD_LGAMMA2, IF_REAL, "Length dependence of gamma2"), +IOP( "lvbx", BSIM3v1A_MOD_LVBX, IF_REAL, "Length dependence of vbx"), +IOP( "lvbm", BSIM3v1A_MOD_LVBM, IF_REAL, "Length dependence of vbm"), +IOP( "lxt", BSIM3v1A_MOD_LXT, IF_REAL, "Length dependence of xt"), +IOP( "lk1", BSIM3v1A_MOD_LK1, IF_REAL, "Length dependence of k1"), +IOP( "lkt1", BSIM3v1A_MOD_LKT1, IF_REAL, "Length dependence of kt1"), +IOP( "lkt1l", BSIM3v1A_MOD_LKT1L, IF_REAL, "Length dependence of kt1l"), +IOP( "lkt2", BSIM3v1A_MOD_LKT2, IF_REAL, "Length dependence of kt2"), +IOP( "lk2", BSIM3v1A_MOD_LK2, IF_REAL, "Length dependence of k2"), +IOP( "lk3", BSIM3v1A_MOD_LK3, IF_REAL, "Length dependence of k3"), +IOP( "lk3b", BSIM3v1A_MOD_LK3B, IF_REAL, "Length dependence of k3b"), +IOP( "lw0", BSIM3v1A_MOD_LW0, IF_REAL, "Length dependence of w0"), +IOP( "lnlx", BSIM3v1A_MOD_LNLX, IF_REAL, "Length dependence of nlx"), +IOP( "ldvt0", BSIM3v1A_MOD_LDVT0, IF_REAL, "Length dependence of dvt0"), +IOP( "ldvt1", BSIM3v1A_MOD_LDVT1, IF_REAL, "Length dependence of dvt1"), +IOP( "ldvt2", BSIM3v1A_MOD_LDVT2, IF_REAL, "Length dependence of dvt2"), +IOP( "ldvt0w", BSIM3v1A_MOD_LDVT0W, IF_REAL, "Length dependence of dvt0w"), +IOP( "ldvt1w", BSIM3v1A_MOD_LDVT1W, IF_REAL, "Length dependence of dvt1w"), +IOP( "ldvt2w", BSIM3v1A_MOD_LDVT2W, IF_REAL, "Length dependence of dvt2w"), +IOP( "ldrout", BSIM3v1A_MOD_LDROUT, IF_REAL, "Length dependence of drout"), +IOP( "ldsub", BSIM3v1A_MOD_LDSUB, IF_REAL, "Length dependence of dsub"), +IOP( "lvth0", BSIM3v1A_MOD_LVTH0, IF_REAL,"Length dependence of vto"), +IOP( "lvtho", BSIM3v1A_MOD_LVTH0, IF_REAL,"Length dependence of vto"), +IOP( "lua", BSIM3v1A_MOD_LUA, IF_REAL, "Length dependence of ua"), +IOP( "lua1", BSIM3v1A_MOD_LUA1, IF_REAL, "Length dependence of ua1"), +IOP( "lub", BSIM3v1A_MOD_LUB, IF_REAL, "Length dependence of ub"), +IOP( "lub1", BSIM3v1A_MOD_LUB1, IF_REAL, "Length dependence of ub1"), +IOP( "luc", BSIM3v1A_MOD_LUC, IF_REAL, "Length dependence of uc"), +IOP( "luc1", BSIM3v1A_MOD_LUC1, IF_REAL, "Length dependence of uc1"), +IOP( "lu0", BSIM3v1A_MOD_LU0, IF_REAL, "Length dependence of u0"), +IOP( "lute", BSIM3v1A_MOD_LUTE, IF_REAL, "Length dependence of ute"), +IOP( "lvoff", BSIM3v1A_MOD_LVOFF, IF_REAL, "Length dependence of voff"), +IOP( "lelm", BSIM3v1A_MOD_LELM, IF_REAL, "Length dependence of elm"), +IOP( "ldelta", BSIM3v1A_MOD_LDELTA, IF_REAL, "Length dependence of delta"), +IOP( "lrdsw", BSIM3v1A_MOD_LRDSW, IF_REAL, "Length dependence of rdsw "), + +IOP( "lprwg", BSIM3v1A_MOD_LPRWG, IF_REAL, "Length dependence of prwg "), +IOP( "lprwb", BSIM3v1A_MOD_LPRWB, IF_REAL, "Length dependence of prwb "), + +IOP( "lprt", BSIM3v1A_MOD_LPRT, IF_REAL, "Length dependence of prt "), +IOP( "leta0", BSIM3v1A_MOD_LETA0, IF_REAL, "Length dependence of eta0"), +IOP( "letab", BSIM3v1A_MOD_LETAB, IF_REAL, "Length dependence of etab"), +IOP( "lpclm", BSIM3v1A_MOD_LPCLM, IF_REAL, "Length dependence of pclm"), +IOP( "lpdiblc1", BSIM3v1A_MOD_LPDIBL1, IF_REAL, "Length dependence of pdiblc1"), +IOP( "lpdiblc2", BSIM3v1A_MOD_LPDIBL2, IF_REAL, "Length dependence of pdiblc2"), +IOP( "lpdiblcb", BSIM3v1A_MOD_LPDIBLB, IF_REAL, "Length dependence of pdiblcb"), +IOP( "lpscbe1", BSIM3v1A_MOD_LPSCBE1, IF_REAL, "Length dependence of pscbe1"), +IOP( "lpscbe2", BSIM3v1A_MOD_LPSCBE2, IF_REAL, "Length dependence of pscbe2"), +IOP( "lpvag", BSIM3v1A_MOD_LPVAG, IF_REAL, "Length dependence of pvag"), +IOP( "lwr", BSIM3v1A_MOD_LWR, IF_REAL, "Length dependence of wr"), +IOP( "ldwg", BSIM3v1A_MOD_LDWG, IF_REAL, "Length dependence of dwg"), +IOP( "ldwb", BSIM3v1A_MOD_LDWB, IF_REAL, "Length dependence of dwb"), +IOP( "lb0", BSIM3v1A_MOD_LB0, IF_REAL, "Length dependence of b0"), +IOP( "lb1", BSIM3v1A_MOD_LB1, IF_REAL, "Length dependence of b1"), +IOP( "lcgsl", BSIM3v1A_MOD_LCGSL, IF_REAL, "Length dependence of cgsl"), +IOP( "lcgdl", BSIM3v1A_MOD_LCGDL, IF_REAL, "Length dependence of cgdl"), +IOP( "lckappa", BSIM3v1A_MOD_LCKAPPA, IF_REAL, "Length dependence of ckappa"), +IOP( "lcf", BSIM3v1A_MOD_LCF, IF_REAL, "Length dependence of cf"), +IOP( "lclc", BSIM3v1A_MOD_LCLC, IF_REAL, "Length dependence of clc"), +IOP( "lcle", BSIM3v1A_MOD_LCLE, IF_REAL, "Length dependence of cle"), +IOP( "lalpha0", BSIM3v1A_MOD_LALPHA0, IF_REAL, "Length dependence of alpha0"), +IOP( "lbeta0", BSIM3v1A_MOD_LBETA0, IF_REAL, "Length dependence of beta0"), + +IOP( "wcdsc", BSIM3v1A_MOD_WCDSC, IF_REAL, "Width dependence of cdsc"), +IOP( "wcdscb", BSIM3v1A_MOD_WCDSCB, IF_REAL, "Width dependence of cdscb"), +IOP( "wcdscd", BSIM3v1A_MOD_WCDSCD, IF_REAL, "Width dependence of cdscd"), +IOP( "wcit", BSIM3v1A_MOD_WCIT, IF_REAL, "Width dependence of cit"), +IOP( "wnfactor", BSIM3v1A_MOD_WNFACTOR, IF_REAL, "Width dependence of nfactor"), +IOP( "wxj", BSIM3v1A_MOD_WXJ, IF_REAL, "Width dependence of xj"), +IOP( "wvsat", BSIM3v1A_MOD_WVSAT, IF_REAL, "Width dependence of vsat"), +IOP( "wat", BSIM3v1A_MOD_WAT, IF_REAL, "Width dependence of at"), +IOP( "wa0", BSIM3v1A_MOD_WA0, IF_REAL, "Width dependence of a0"), +IOP( "wags", BSIM3v1A_MOD_WAGS, IF_REAL, "Width dependence of ags"), +IOP( "wa1", BSIM3v1A_MOD_WA1, IF_REAL, "Width dependence of a1"), +IOP( "wa2", BSIM3v1A_MOD_WA2, IF_REAL, "Width dependence of a2"), +IOP( "wketa", BSIM3v1A_MOD_WKETA, IF_REAL, "Width dependence of keta"), +IOP( "wnsub", BSIM3v1A_MOD_WNSUB, IF_REAL, "Width dependence of nsub"), +IOP( "wnch", BSIM3v1A_MOD_WNPEAK, IF_REAL, "Width dependence of nch"), +IOP( "wngate", BSIM3v1A_MOD_WNGATE, IF_REAL, "Width dependence of ngate"), +IOP( "wgamma1", BSIM3v1A_MOD_WGAMMA1, IF_REAL, "Width dependence of gamma1"), +IOP( "wgamma2", BSIM3v1A_MOD_WGAMMA2, IF_REAL, "Width dependence of gamma2"), +IOP( "wvbx", BSIM3v1A_MOD_WVBX, IF_REAL, "Width dependence of vbx"), +IOP( "wvbm", BSIM3v1A_MOD_WVBM, IF_REAL, "Width dependence of vbm"), +IOP( "wxt", BSIM3v1A_MOD_WXT, IF_REAL, "Width dependence of xt"), +IOP( "wk1", BSIM3v1A_MOD_WK1, IF_REAL, "Width dependence of k1"), +IOP( "wkt1", BSIM3v1A_MOD_WKT1, IF_REAL, "Width dependence of kt1"), +IOP( "wkt1l", BSIM3v1A_MOD_WKT1L, IF_REAL, "Width dependence of kt1l"), +IOP( "wkt2", BSIM3v1A_MOD_WKT2, IF_REAL, "Width dependence of kt2"), +IOP( "wk2", BSIM3v1A_MOD_WK2, IF_REAL, "Width dependence of k2"), +IOP( "wk3", BSIM3v1A_MOD_WK3, IF_REAL, "Width dependence of k3"), +IOP( "wk3b", BSIM3v1A_MOD_WK3B, IF_REAL, "Width dependence of k3b"), +IOP( "ww0", BSIM3v1A_MOD_WW0, IF_REAL, "Width dependence of w0"), +IOP( "wnlx", BSIM3v1A_MOD_WNLX, IF_REAL, "Width dependence of nlx"), +IOP( "wdvt0", BSIM3v1A_MOD_WDVT0, IF_REAL, "Width dependence of dvt0"), +IOP( "wdvt1", BSIM3v1A_MOD_WDVT1, IF_REAL, "Width dependence of dvt1"), +IOP( "wdvt2", BSIM3v1A_MOD_WDVT2, IF_REAL, "Width dependence of dvt2"), +IOP( "wdvt0w", BSIM3v1A_MOD_WDVT0W, IF_REAL, "Width dependence of dvt0w"), +IOP( "wdvt1w", BSIM3v1A_MOD_WDVT1W, IF_REAL, "Width dependence of dvt1w"), +IOP( "wdvt2w", BSIM3v1A_MOD_WDVT2W, IF_REAL, "Width dependence of dvt2w"), +IOP( "wdrout", BSIM3v1A_MOD_WDROUT, IF_REAL, "Width dependence of drout"), +IOP( "wdsub", BSIM3v1A_MOD_WDSUB, IF_REAL, "Width dependence of dsub"), +IOP( "wvth0", BSIM3v1A_MOD_WVTH0, IF_REAL,"Width dependence of vto"), +IOP( "wvtho", BSIM3v1A_MOD_WVTH0, IF_REAL,"Width dependence of vto"), +IOP( "wua", BSIM3v1A_MOD_WUA, IF_REAL, "Width dependence of ua"), +IOP( "wua1", BSIM3v1A_MOD_WUA1, IF_REAL, "Width dependence of ua1"), +IOP( "wub", BSIM3v1A_MOD_WUB, IF_REAL, "Width dependence of ub"), +IOP( "wub1", BSIM3v1A_MOD_WUB1, IF_REAL, "Width dependence of ub1"), +IOP( "wuc", BSIM3v1A_MOD_WUC, IF_REAL, "Width dependence of uc"), +IOP( "wuc1", BSIM3v1A_MOD_WUC1, IF_REAL, "Width dependence of uc1"), +IOP( "wu0", BSIM3v1A_MOD_WU0, IF_REAL, "Width dependence of u0"), +IOP( "wute", BSIM3v1A_MOD_WUTE, IF_REAL, "Width dependence of ute"), +IOP( "wvoff", BSIM3v1A_MOD_WVOFF, IF_REAL, "Width dependence of voff"), +IOP( "welm", BSIM3v1A_MOD_WELM, IF_REAL, "Width dependence of elm"), +IOP( "wdelta", BSIM3v1A_MOD_WDELTA, IF_REAL, "Width dependence of delta"), +IOP( "wrdsw", BSIM3v1A_MOD_WRDSW, IF_REAL, "Width dependence of rdsw "), + +IOP( "wprwg", BSIM3v1A_MOD_WPRWG, IF_REAL, "Width dependence of prwg "), +IOP( "wprwb", BSIM3v1A_MOD_WPRWB, IF_REAL, "Width dependence of prwb "), + +IOP( "wprt", BSIM3v1A_MOD_WPRT, IF_REAL, "Width dependence of prt"), +IOP( "weta0", BSIM3v1A_MOD_WETA0, IF_REAL, "Width dependence of eta0"), +IOP( "wetab", BSIM3v1A_MOD_WETAB, IF_REAL, "Width dependence of etab"), +IOP( "wpclm", BSIM3v1A_MOD_WPCLM, IF_REAL, "Width dependence of pclm"), +IOP( "wpdiblc1", BSIM3v1A_MOD_WPDIBL1, IF_REAL, "Width dependence of pdiblc1"), +IOP( "wpdiblc2", BSIM3v1A_MOD_WPDIBL2, IF_REAL, "Width dependence of pdiblc2"), +IOP( "wpdiblcb", BSIM3v1A_MOD_WPDIBLB, IF_REAL, "Width dependence of pdiblcb"), +IOP( "wpscbe1", BSIM3v1A_MOD_WPSCBE1, IF_REAL, "Width dependence of pscbe1"), +IOP( "wpscbe2", BSIM3v1A_MOD_WPSCBE2, IF_REAL, "Width dependence of pscbe2"), +IOP( "wpvag", BSIM3v1A_MOD_WPVAG, IF_REAL, "Width dependence of pvag"), +IOP( "wwr", BSIM3v1A_MOD_WWR, IF_REAL, "Width dependence of wr"), +IOP( "wdwg", BSIM3v1A_MOD_WDWG, IF_REAL, "Width dependence of dwg"), +IOP( "wdwb", BSIM3v1A_MOD_WDWB, IF_REAL, "Width dependence of dwb"), +IOP( "wb0", BSIM3v1A_MOD_WB0, IF_REAL, "Width dependence of b0"), +IOP( "wb1", BSIM3v1A_MOD_WB1, IF_REAL, "Width dependence of b1"), +IOP( "wcgsl", BSIM3v1A_MOD_WCGSL, IF_REAL, "Width dependence of cgsl"), +IOP( "wcgdl", BSIM3v1A_MOD_WCGDL, IF_REAL, "Width dependence of cgdl"), +IOP( "wckappa", BSIM3v1A_MOD_WCKAPPA, IF_REAL, "Width dependence of ckappa"), +IOP( "wcf", BSIM3v1A_MOD_WCF, IF_REAL, "Width dependence of cf"), +IOP( "wclc", BSIM3v1A_MOD_WCLC, IF_REAL, "Width dependence of clc"), +IOP( "wcle", BSIM3v1A_MOD_WCLE, IF_REAL, "Width dependence of cle"), +IOP( "walpha0", BSIM3v1A_MOD_WALPHA0, IF_REAL, "Width dependence of alpha0"), +IOP( "wbeta0", BSIM3v1A_MOD_WBETA0, IF_REAL, "Width dependence of beta0"), + +IOP( "pcdsc", BSIM3v1A_MOD_PCDSC, IF_REAL, "Cross-term dependence of cdsc"), +IOP( "pcdscb", BSIM3v1A_MOD_PCDSCB, IF_REAL, "Cross-term dependence of cdscb"), +IOP( "pcdscd", BSIM3v1A_MOD_PCDSCD, IF_REAL, "Cross-term dependence of cdscd"), +IOP( "pcit", BSIM3v1A_MOD_PCIT, IF_REAL, "Cross-term dependence of cit"), +IOP( "pnfactor", BSIM3v1A_MOD_PNFACTOR, IF_REAL, "Cross-term dependence of nfactor"), +IOP( "pxj", BSIM3v1A_MOD_PXJ, IF_REAL, "Cross-term dependence of xj"), +IOP( "pvsat", BSIM3v1A_MOD_PVSAT, IF_REAL, "Cross-term dependence of vsat"), +IOP( "pat", BSIM3v1A_MOD_PAT, IF_REAL, "Cross-term dependence of at"), +IOP( "pa0", BSIM3v1A_MOD_PA0, IF_REAL, "Cross-term dependence of a0"), +IOP( "pags", BSIM3v1A_MOD_PAGS, IF_REAL, "Cross-term dependence of ags"), +IOP( "pa1", BSIM3v1A_MOD_PA1, IF_REAL, "Cross-term dependence of a1"), +IOP( "pa2", BSIM3v1A_MOD_PA2, IF_REAL, "Cross-term dependence of a2"), +IOP( "pketa", BSIM3v1A_MOD_PKETA, IF_REAL, "Cross-term dependence of keta"), +IOP( "pnsub", BSIM3v1A_MOD_PNSUB, IF_REAL, "Cross-term dependence of nsub"), +IOP( "pnch", BSIM3v1A_MOD_PNPEAK, IF_REAL, "Cross-term dependence of nch"), +IOP( "pngate", BSIM3v1A_MOD_PNGATE, IF_REAL, "Cross-term dependence of ngate"), +IOP( "pgamma1", BSIM3v1A_MOD_PGAMMA1, IF_REAL, "Cross-term dependence of gamma1"), +IOP( "pgamma2", BSIM3v1A_MOD_PGAMMA2, IF_REAL, "Cross-term dependence of gamma2"), +IOP( "pvbx", BSIM3v1A_MOD_PVBX, IF_REAL, "Cross-term dependence of vbx"), +IOP( "pvbm", BSIM3v1A_MOD_PVBM, IF_REAL, "Cross-term dependence of vbm"), +IOP( "pxt", BSIM3v1A_MOD_PXT, IF_REAL, "Cross-term dependence of xt"), +IOP( "pk1", BSIM3v1A_MOD_PK1, IF_REAL, "Cross-term dependence of k1"), +IOP( "pkt1", BSIM3v1A_MOD_PKT1, IF_REAL, "Cross-term dependence of kt1"), +IOP( "pkt1l", BSIM3v1A_MOD_PKT1L, IF_REAL, "Cross-term dependence of kt1l"), +IOP( "pkt2", BSIM3v1A_MOD_PKT2, IF_REAL, "Cross-term dependence of kt2"), +IOP( "pk2", BSIM3v1A_MOD_PK2, IF_REAL, "Cross-term dependence of k2"), +IOP( "pk3", BSIM3v1A_MOD_PK3, IF_REAL, "Cross-term dependence of k3"), +IOP( "pk3b", BSIM3v1A_MOD_PK3B, IF_REAL, "Cross-term dependence of k3b"), +IOP( "pw0", BSIM3v1A_MOD_PW0, IF_REAL, "Cross-term dependence of w0"), +IOP( "pnlx", BSIM3v1A_MOD_PNLX, IF_REAL, "Cross-term dependence of nlx"), +IOP( "pdvt0", BSIM3v1A_MOD_PDVT0, IF_REAL, "Cross-term dependence of dvt0"), +IOP( "pdvt1", BSIM3v1A_MOD_PDVT1, IF_REAL, "Cross-term dependence of dvt1"), +IOP( "pdvt2", BSIM3v1A_MOD_PDVT2, IF_REAL, "Cross-term dependence of dvt2"), +IOP( "pdvt0w", BSIM3v1A_MOD_PDVT0W, IF_REAL, "Cross-term dependence of dvt0w"), +IOP( "pdvt1w", BSIM3v1A_MOD_PDVT1W, IF_REAL, "Cross-term dependence of dvt1w"), +IOP( "pdvt2w", BSIM3v1A_MOD_PDVT2W, IF_REAL, "Cross-term dependence of dvt2w"), +IOP( "pdrout", BSIM3v1A_MOD_PDROUT, IF_REAL, "Cross-term dependence of drout"), +IOP( "pdsub", BSIM3v1A_MOD_PDSUB, IF_REAL, "Cross-term dependence of dsub"), +IOP( "pvth0", BSIM3v1A_MOD_PVTH0, IF_REAL,"Cross-term dependence of vto"), +IOP( "pvtho", BSIM3v1A_MOD_PVTH0, IF_REAL,"Cross-term dependence of vto"), +IOP( "pua", BSIM3v1A_MOD_PUA, IF_REAL, "Cross-term dependence of ua"), +IOP( "pua1", BSIM3v1A_MOD_PUA1, IF_REAL, "Cross-term dependence of ua1"), +IOP( "pub", BSIM3v1A_MOD_PUB, IF_REAL, "Cross-term dependence of ub"), +IOP( "pub1", BSIM3v1A_MOD_PUB1, IF_REAL, "Cross-term dependence of ub1"), +IOP( "puc", BSIM3v1A_MOD_PUC, IF_REAL, "Cross-term dependence of uc"), +IOP( "puc1", BSIM3v1A_MOD_PUC1, IF_REAL, "Cross-term dependence of uc1"), +IOP( "pu0", BSIM3v1A_MOD_PU0, IF_REAL, "Cross-term dependence of u0"), +IOP( "pute", BSIM3v1A_MOD_PUTE, IF_REAL, "Cross-term dependence of ute"), +IOP( "pvoff", BSIM3v1A_MOD_PVOFF, IF_REAL, "Cross-term dependence of voff"), +IOP( "pelm", BSIM3v1A_MOD_PELM, IF_REAL, "Cross-term dependence of elm"), +IOP( "pdelta", BSIM3v1A_MOD_PDELTA, IF_REAL, "Cross-term dependence of delta"), +IOP( "prdsw", BSIM3v1A_MOD_PRDSW, IF_REAL, "Cross-term dependence of rdsw "), + +IOP( "pprwg", BSIM3v1A_MOD_PPRWG, IF_REAL, "Cross-term dependence of prwg "), +IOP( "pprwb", BSIM3v1A_MOD_PPRWB, IF_REAL, "Cross-term dependence of prwb "), + +IOP( "pprt", BSIM3v1A_MOD_PPRT, IF_REAL, "Cross-term dependence of prt "), +IOP( "peta0", BSIM3v1A_MOD_PETA0, IF_REAL, "Cross-term dependence of eta0"), +IOP( "petab", BSIM3v1A_MOD_PETAB, IF_REAL, "Cross-term dependence of etab"), +IOP( "ppclm", BSIM3v1A_MOD_PPCLM, IF_REAL, "Cross-term dependence of pclm"), +IOP( "ppdiblc1", BSIM3v1A_MOD_PPDIBL1, IF_REAL, "Cross-term dependence of pdiblc1"), +IOP( "ppdiblc2", BSIM3v1A_MOD_PPDIBL2, IF_REAL, "Cross-term dependence of pdiblc2"), +IOP( "ppdiblcb", BSIM3v1A_MOD_PPDIBLB, IF_REAL, "Cross-term dependence of pdiblcb"), +IOP( "ppscbe1", BSIM3v1A_MOD_PPSCBE1, IF_REAL, "Cross-term dependence of pscbe1"), +IOP( "ppscbe2", BSIM3v1A_MOD_PPSCBE2, IF_REAL, "Cross-term dependence of pscbe2"), +IOP( "ppvag", BSIM3v1A_MOD_PPVAG, IF_REAL, "Cross-term dependence of pvag"), +IOP( "pwr", BSIM3v1A_MOD_PWR, IF_REAL, "Cross-term dependence of wr"), +IOP( "pdwg", BSIM3v1A_MOD_PDWG, IF_REAL, "Cross-term dependence of dwg"), +IOP( "pdwb", BSIM3v1A_MOD_PDWB, IF_REAL, "Cross-term dependence of dwb"), +IOP( "pb0", BSIM3v1A_MOD_PB0, IF_REAL, "Cross-term dependence of b0"), +IOP( "pb1", BSIM3v1A_MOD_PB1, IF_REAL, "Cross-term dependence of b1"), +IOP( "pcgsl", BSIM3v1A_MOD_PCGSL, IF_REAL, "Cross-term dependence of cgsl"), +IOP( "pcgdl", BSIM3v1A_MOD_PCGDL, IF_REAL, "Cross-term dependence of cgdl"), +IOP( "pckappa", BSIM3v1A_MOD_PCKAPPA, IF_REAL, "Cross-term dependence of ckappa"), +IOP( "pcf", BSIM3v1A_MOD_PCF, IF_REAL, "Cross-term dependence of cf"), +IOP( "pclc", BSIM3v1A_MOD_PCLC, IF_REAL, "Cross-term dependence of clc"), +IOP( "pcle", BSIM3v1A_MOD_PCLE, IF_REAL, "Cross-term dependence of cle"), +IOP( "palpha0", BSIM3v1A_MOD_PALPHA0, IF_REAL, "Cross-term dependence of alpha0"), +IOP( "pbeta0", BSIM3v1A_MOD_PBETA0, IF_REAL, "Cross-term dependence of beta0"), + +IOP( "noia", BSIM3v1A_MOD_NOIA, IF_REAL, "Flicker noise parameter"), +IOP( "noib", BSIM3v1A_MOD_NOIB, IF_REAL, "Flicker noise parameter"), +IOP( "noic", BSIM3v1A_MOD_NOIC, IF_REAL, "Flicker noise parameter"), +IOP( "em", BSIM3v1A_MOD_EM, IF_REAL, "Flicker noise parameter"), +IOP( "ef", BSIM3v1A_MOD_EF, IF_REAL, "Flicker noise frequency exponent"), +IOP( "af", BSIM3v1A_MOD_AF, IF_REAL, "Flicker noise exponent"), +IOP( "kf", BSIM3v1A_MOD_KF, IF_REAL, "Flicker noise coefficient"), + +IP( "nmos", BSIM3v1A_MOD_NMOS, IF_FLAG, "Flag to indicate NMOS"), +IP( "pmos", BSIM3v1A_MOD_PMOS, IF_FLAG, "Flag to indicate PMOS"), +}; + +char *BSIM3v1Anames[] = { + "Drain", + "Gate", + "Source", + "Bulk", + "Charge" +}; + +int BSIM3v1AnSize = NUMELEMS(BSIM3v1Anames); +int BSIM3v1ApTSize = NUMELEMS(BSIM3v1ApTable); +int BSIM3v1AmPTSize = NUMELEMS(BSIM3v1AmPTable); +int BSIM3v1AiSize = sizeof(BSIM3v1Ainstance); +int BSIM3v1AmSize = sizeof(BSIM3v1Amodel); + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1aacld.c b/src/spicelib/devices/bsim3v1a/b3v1aacld.c new file mode 100644 index 000000000..d446e1ce0 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1aacld.c @@ -0,0 +1,184 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1aacld.c +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + + +int +BSIM3v1AacLoad(GENmodel *inModel, CKTcircuit *ckt) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; +double xcggb, xcgdb, xcgsb, xcbgb, xcbdb, xcbsb, xcddb, xcssb, xcdgb; +double gdpr, gspr, gds, gbd, gbs, capbd, capbs, xcsgb, xcdsb, xcsdb; +double cggb, cgdb, cgsb, cbgb, cbdb, cbsb, cddb, cdgb, cdsb, omega; +double GSoverlapCap, GDoverlapCap, GBoverlapCap, FwdSum, RevSum, Gm, Gmbs; + +double dxpart, sxpart, cqgb, cqdb, cqsb, cqbb, xcqgb, xcqdb, xcqsb, xcqbb; + +double m; + + omega = ckt->CKTomega; + for (; model != NULL; model = model->BSIM3v1AnextModel) + { + + + for (here = model->BSIM3v1Ainstances; here!= NULL; + here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + if (here->BSIM3v1Amode >= 0) + { Gm = here->BSIM3v1Agm; + Gmbs = here->BSIM3v1Agmbs; + FwdSum = Gm + Gmbs; + RevSum = 0.0; + cggb = here->BSIM3v1Acggb; + cgsb = here->BSIM3v1Acgsb; + cgdb = here->BSIM3v1Acgdb; + + cbgb = here->BSIM3v1Acbgb; + cbsb = here->BSIM3v1Acbsb; + cbdb = here->BSIM3v1Acbdb; + + cdgb = here->BSIM3v1Acdgb; + cdsb = here->BSIM3v1Acdsb; + cddb = here->BSIM3v1Acddb; + + cqgb = here->BSIM3v1Acqgb; + cqdb = here->BSIM3v1Acqdb; + cqsb = here->BSIM3v1Acqsb; + cqbb = here->BSIM3v1Acqbb; + sxpart = 0.6; + dxpart = 0.4; + + } + else + { Gm = -here->BSIM3v1Agm; + Gmbs = -here->BSIM3v1Agmbs; + FwdSum = 0.0; + RevSum = -Gm - Gmbs; + cggb = here->BSIM3v1Acggb; + cgsb = here->BSIM3v1Acgdb; + cgdb = here->BSIM3v1Acgsb; + + cbgb = here->BSIM3v1Acbgb; + cbsb = here->BSIM3v1Acbdb; + cbdb = here->BSIM3v1Acbsb; + + cdgb = -(here->BSIM3v1Acdgb + cggb + cbgb); + cdsb = -(here->BSIM3v1Acddb + cgsb + cbsb); + cddb = -(here->BSIM3v1Acdsb + cgdb + cbdb); + + cqgb = here->BSIM3v1Acqgb; + cqdb = here->BSIM3v1Acqsb; + cqsb = here->BSIM3v1Acqdb; + cqbb = here->BSIM3v1Acqbb; + sxpart = 0.4; + dxpart = 0.6; + } + + gdpr=here->BSIM3v1AdrainConductance; + gspr=here->BSIM3v1AsourceConductance; + gds= here->BSIM3v1Agds; + gbd= here->BSIM3v1Agbd; + gbs= here->BSIM3v1Agbs; + capbd= here->BSIM3v1Acapbd; + capbs= here->BSIM3v1Acapbs; + + GSoverlapCap = here->BSIM3v1Acgso; + GDoverlapCap = here->BSIM3v1Acgdo; + GBoverlapCap = here->pParam->BSIM3v1Acgbo; + + xcdgb = (cdgb - GDoverlapCap) * omega; + xcddb = (cddb + capbd + GDoverlapCap) * omega; + xcdsb = cdsb * omega; + xcsgb = -(cggb + cbgb + cdgb + GSoverlapCap) * omega; + xcsdb = -(cgdb + cbdb + cddb) * omega; + xcssb = (capbs + GSoverlapCap - (cgsb + cbsb + cdsb)) * omega; + xcggb = (cggb + GDoverlapCap + GSoverlapCap + GBoverlapCap) + * omega; + xcgdb = (cgdb - GDoverlapCap ) * omega; + xcgsb = (cgsb - GSoverlapCap) * omega; + xcbgb = (cbgb - GBoverlapCap) * omega; + xcbdb = (cbdb - capbd ) * omega; + xcbsb = (cbsb - capbs ) * omega; + xcqgb = cqgb * omega; + xcqdb = cqdb * omega; + xcqsb = cqsb * omega; + xcqbb = cqbb * omega; + + m = here->BSIM3v1Am; + + *(here->BSIM3v1AGgPtr +1) += m * xcggb; + *(here->BSIM3v1ABbPtr +1) -= m * (xcbgb + xcbdb + xcbsb); + *(here->BSIM3v1ADPdpPtr +1) += m * xcddb; + *(here->BSIM3v1ASPspPtr +1) += m * xcssb; + *(here->BSIM3v1AGbPtr +1) -= m * (xcggb + xcgdb + xcgsb); + *(here->BSIM3v1AGdpPtr +1) += m * xcgdb; + *(here->BSIM3v1AGspPtr +1) += m * xcgsb; + *(here->BSIM3v1ABgPtr +1) += m * xcbgb; + *(here->BSIM3v1ABdpPtr +1) += m * xcbdb; + *(here->BSIM3v1ABspPtr +1) += m * xcbsb; + *(here->BSIM3v1ADPgPtr +1) += m * xcdgb; + *(here->BSIM3v1ADPbPtr +1) -= m * (xcdgb + xcddb + xcdsb); + *(here->BSIM3v1ADPspPtr +1) += m * xcdsb; + *(here->BSIM3v1ASPgPtr +1) += m * xcsgb; + *(here->BSIM3v1ASPbPtr +1) -= m * (xcsgb + xcsdb + xcssb); + *(here->BSIM3v1ASPdpPtr +1) += m * xcsdb; + + *(here->BSIM3v1AQqPtr +1) += m * omega; + + *(here->BSIM3v1AQgPtr +1) -= m * xcqgb; + *(here->BSIM3v1AQdpPtr +1) -= m * xcqdb; + *(here->BSIM3v1AQspPtr +1) -= m * xcqsb; + *(here->BSIM3v1AQbPtr +1) -= m * xcqbb; + + *(here->BSIM3v1ADdPtr) += m * gdpr; + *(here->BSIM3v1ASsPtr) += m * gspr; + *(here->BSIM3v1ABbPtr) += m * (gbd + gbs); + *(here->BSIM3v1ADPdpPtr) += m*(gdpr+gds+gbd+RevSum+dxpart*here->BSIM3v1Agtd); + *(here->BSIM3v1ASPspPtr) += m*(gspr+gds+gbs+FwdSum+sxpart*here->BSIM3v1Agts); + *(here->BSIM3v1ADdpPtr) -= m * gdpr; + *(here->BSIM3v1ASspPtr) -= m * gspr; + *(here->BSIM3v1ABdpPtr) -= m * gbd; + *(here->BSIM3v1ABspPtr) -= m * gbs; + *(here->BSIM3v1ADPdPtr) -= m * gdpr; + *(here->BSIM3v1ADPgPtr) += m * (Gm + dxpart * here->BSIM3v1Agtg); + *(here->BSIM3v1ADPbPtr) -= m * (gbd-Gmbs - dxpart * here->BSIM3v1Agtb); + *(here->BSIM3v1ADPspPtr) -= m * (gds+FwdSum-dxpart * here->BSIM3v1Agts); + *(here->BSIM3v1ASPgPtr) -= m * (Gm - sxpart * here->BSIM3v1Agtg); + *(here->BSIM3v1ASPsPtr) -= m * gspr; + *(here->BSIM3v1ASPbPtr) -= m * (gbs+Gmbs - sxpart * here->BSIM3v1Agtg); + *(here->BSIM3v1ASPdpPtr) -= m * (gds+RevSum-sxpart * here->BSIM3v1Agtd); + *(here->BSIM3v1AGgPtr) -= m * here->BSIM3v1Agtg; + *(here->BSIM3v1AGbPtr) -= m * here->BSIM3v1Agtb; + *(here->BSIM3v1AGdpPtr) -= m * here->BSIM3v1Agtd; + *(here->BSIM3v1AGspPtr) -= m * here->BSIM3v1Agts; + + *(here->BSIM3v1AQqPtr) += m * here->BSIM3v1Agtau; + + *(here->BSIM3v1ADPqPtr) += m * dxpart * here->BSIM3v1Agtau; + *(here->BSIM3v1ASPqPtr) += m * sxpart * here->BSIM3v1Agtau; + *(here->BSIM3v1AGqPtr) -= m * here->BSIM3v1Agtau; + + *(here->BSIM3v1AQgPtr) += m * here->BSIM3v1Agtg; + *(here->BSIM3v1AQdpPtr) += m * here->BSIM3v1Agtd; + *(here->BSIM3v1AQspPtr) += m * here->BSIM3v1Agts; + *(here->BSIM3v1AQbPtr) += m * here->BSIM3v1Agtb; + + } + } + return(OK); +} + diff --git a/src/spicelib/devices/bsim3v1a/b3v1aask.c b/src/spicelib/devices/bsim3v1a/b3v1aask.c new file mode 100644 index 000000000..d4126bda1 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1aask.c @@ -0,0 +1,223 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1aask.c +**********/ + +#include "ngspice.h" +#include "ifsim.h" +#include "cktdefs.h" +#include "devdefs.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + +int +BSIM3v1Aask(CKTcircuit *ckt, GENinstance *inst, int which, IFvalue *value, + IFvalue *select) + +{ +BSIM3v1Ainstance *here = (BSIM3v1Ainstance*)inst; + + switch(which) + { case BSIM3v1A_L: + value->rValue = here->BSIM3v1Al; + return(OK); + case BSIM3v1A_W: + value->rValue = here->BSIM3v1Aw; + return(OK); + case BSIM3v1A_M: + value->rValue = here->BSIM3v1Am; + return(OK); + case BSIM3v1A_AS: + value->rValue = here->BSIM3v1AsourceArea; + return(OK); + case BSIM3v1A_AD: + value->rValue = here->BSIM3v1AdrainArea; + return(OK); + case BSIM3v1A_PS: + value->rValue = here->BSIM3v1AsourcePerimeter; + return(OK); + case BSIM3v1A_PD: + value->rValue = here->BSIM3v1AdrainPerimeter; + return(OK); + case BSIM3v1A_NRS: + value->rValue = here->BSIM3v1AsourceSquares; + return(OK); + case BSIM3v1A_NRD: + value->rValue = here->BSIM3v1AdrainSquares; + return(OK); + case BSIM3v1A_OFF: + value->rValue = here->BSIM3v1Aoff; + return(OK); + case BSIM3v1A_NQSMOD: + value->iValue = here->BSIM3v1AnqsMod; + return(OK); + case BSIM3v1A_IC_VBS: + value->rValue = here->BSIM3v1AicVBS; + return(OK); + case BSIM3v1A_IC_VDS: + value->rValue = here->BSIM3v1AicVDS; + return(OK); + case BSIM3v1A_IC_VGS: + value->rValue = here->BSIM3v1AicVGS; + return(OK); + case BSIM3v1A_DNODE: + value->iValue = here->BSIM3v1AdNode; + return(OK); + case BSIM3v1A_GNODE: + value->iValue = here->BSIM3v1AgNode; + return(OK); + case BSIM3v1A_SNODE: + value->iValue = here->BSIM3v1AsNode; + return(OK); + case BSIM3v1A_BNODE: + value->iValue = here->BSIM3v1AbNode; + return(OK); + case BSIM3v1A_DNODEPRIME: + value->iValue = here->BSIM3v1AdNodePrime; + return(OK); + case BSIM3v1A_SNODEPRIME: + value->iValue = here->BSIM3v1AsNodePrime; + return(OK); + case BSIM3v1A_SOURCECONDUCT: + value->rValue = here->BSIM3v1AsourceConductance; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_DRAINCONDUCT: + value->rValue = here->BSIM3v1AdrainConductance; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_VBD: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Avbd); + return(OK); + case BSIM3v1A_VBS: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Avbs); + return(OK); + case BSIM3v1A_VGS: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Avgs); + return(OK); + case BSIM3v1A_VDS: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Avds); + return(OK); + case BSIM3v1A_CD: + value->rValue = here->BSIM3v1Acd; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CBS: + value->rValue = here->BSIM3v1Acbs; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CBD: + value->rValue = here->BSIM3v1Acbd; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_GM: + value->rValue = here->BSIM3v1Agm; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_GDS: + value->rValue = here->BSIM3v1Agds; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_GMBS: + value->rValue = here->BSIM3v1Agmbs; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_GBD: + value->rValue = here->BSIM3v1Agbd; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_GBS: + value->rValue = here->BSIM3v1Agbs; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_QB: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Aqb); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CQB: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Acqb); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_QG: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Aqg); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CQG: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Acqg); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_QD: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Aqd); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CQD: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Acqd); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CGG: + value->rValue = here->BSIM3v1Acggb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CGD: + value->rValue = here->BSIM3v1Acgdb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CGS: + value->rValue = here->BSIM3v1Acgsb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CDG: + value->rValue = here->BSIM3v1Acdgb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CDD: + value->rValue = here->BSIM3v1Acddb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CDS: + value->rValue = here->BSIM3v1Acdsb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CBG: + value->rValue = here->BSIM3v1Acbgb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CBDB: + value->rValue = here->BSIM3v1Acbdb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CBSB: + value->rValue = here->BSIM3v1Acbsb; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CAPBD: + value->rValue = here->BSIM3v1Acapbd; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_CAPBS: + value->rValue = here->BSIM3v1Acapbs; + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_VON: + value->rValue = here->BSIM3v1Avon; + return(OK); + case BSIM3v1A_VDSAT: + value->rValue = here->BSIM3v1Avdsat; + return(OK); + case BSIM3v1A_QBS: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Aqbs); + value->rValue *= here->BSIM3v1Am; + return(OK); + case BSIM3v1A_QBD: + value->rValue = *(ckt->CKTstate0 + here->BSIM3v1Aqbd); + value->rValue *= here->BSIM3v1Am; + return(OK); + default: + return(E_BADPARM); + } + /* NOTREACHED */ +} + diff --git a/src/spicelib/devices/bsim3v1a/b3v1acvtest.c b/src/spicelib/devices/bsim3v1a/b3v1acvtest.c new file mode 100644 index 000000000..01bbad06f --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1acvtest.c @@ -0,0 +1,91 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1acvtest.c +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "trandefs.h" +#include "const.h" +#include "devdefs.h" +#include "sperror.h" +#include "suffix.h" + + +int +BSIM3v1AconvTest(GENmodel *inModel, CKTcircuit *ckt) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; +double delvbd, delvbs, delvds, delvgd, delvgs, vbd, vbs, vds; +double cbd, cbhat, cbs, cd, cdhat, tol, vgd, vgdo, vgs; + + /* loop through all the BSIM3v1A device models */ + for (; model != NULL; model = model->BSIM3v1AnextModel) + { /* loop through all the instances of the model */ + for (here = model->BSIM3v1Ainstances; here != NULL ; + here=here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + vbs = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld+here->BSIM3v1AbNode) + - *(ckt->CKTrhsOld+here->BSIM3v1AsNodePrime)); + vgs = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld+here->BSIM3v1AgNode) + - *(ckt->CKTrhsOld+here->BSIM3v1AsNodePrime)); + vds = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld+here->BSIM3v1AdNodePrime) + - *(ckt->CKTrhsOld+here->BSIM3v1AsNodePrime)); + vbd = vbs - vds; + vgd = vgs - vds; + vgdo = *(ckt->CKTstate0 + here->BSIM3v1Avgs) + - *(ckt->CKTstate0 + here->BSIM3v1Avds); + delvbs = vbs - *(ckt->CKTstate0 + here->BSIM3v1Avbs); + delvbd = vbd - *(ckt->CKTstate0 + here->BSIM3v1Avbd); + delvgs = vgs - *(ckt->CKTstate0 + here->BSIM3v1Avgs); + delvds = vds - *(ckt->CKTstate0 + here->BSIM3v1Avds); + delvgd = vgd-vgdo; + + cd = here->BSIM3v1Acd; + if (here->BSIM3v1Amode >= 0) + { cdhat = cd - here->BSIM3v1Agbd * delvbd + + here->BSIM3v1Agmbs * delvbs + here->BSIM3v1Agm * delvgs + + here->BSIM3v1Agds * delvds; + } + else + { cdhat = cd - (here->BSIM3v1Agbd - here->BSIM3v1Agmbs) * delvbd + - here->BSIM3v1Agm * delvgd + here->BSIM3v1Agds * delvds; + } + + /* + * check convergence + */ + if ((here->BSIM3v1Aoff == 0) || (!(ckt->CKTmode & MODEINITFIX))) + { tol = ckt->CKTreltol * MAX(fabs(cdhat), fabs(cd)) + + ckt->CKTabstol; + if (fabs(cdhat - cd) >= tol) + { ckt->CKTnoncon++; + return(OK); + } + cbs = here->BSIM3v1Acbs; + cbd = here->BSIM3v1Acbd; + cbhat = cbs + cbd + here->BSIM3v1Agbd * delvbd + + here->BSIM3v1Agbs * delvbs; + tol = ckt->CKTreltol * MAX(fabs(cbhat), fabs(cbs + cbd)) + + ckt->CKTabstol; + if (fabs(cbhat - (cbs + cbd)) > tol) + { ckt->CKTnoncon++; + return(OK); + } + } + } + } + return(OK); +} + diff --git a/src/spicelib/devices/bsim3v1a/b3v1adel.c b/src/spicelib/devices/bsim3v1a/b3v1adel.c new file mode 100644 index 000000000..171f9c499 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1adel.c @@ -0,0 +1,39 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1adel.c +**********/ +/* + */ + +#include "ngspice.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "gendefs.h" +#include "suffix.h" + + +int +BSIM3v1Adelete(GENmodel *inModel, IFuid name, GENinstance **inInst) +{ +BSIM3v1Ainstance **fast = (BSIM3v1Ainstance**)inInst; +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance **prev = NULL; +BSIM3v1Ainstance *here; + + for (; model ; model = model->BSIM3v1AnextModel) + { prev = &(model->BSIM3v1Ainstances); + for (here = *prev; here ; here = *prev) + { if (here->BSIM3v1Aname == name || (fast && here==*fast)) + { *prev= here->BSIM3v1AnextInstance; + FREE(here); + return(OK); + } + prev = &(here->BSIM3v1AnextInstance); + } + } + return(E_NODEV); +} + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1adest.c b/src/spicelib/devices/bsim3v1a/b3v1adest.c new file mode 100644 index 000000000..b01395c90 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1adest.c @@ -0,0 +1,37 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1adest.c +**********/ + +#include "ngspice.h" +#include "bsim3v1adef.h" +#include "suffix.h" + +void +BSIM3v1Adestroy(GENmodel **inModel) +{ +BSIM3v1Amodel **model = (BSIM3v1Amodel**)inModel; +BSIM3v1Ainstance *here; +BSIM3v1Ainstance *prev = NULL; +BSIM3v1Amodel *mod = *model; +BSIM3v1Amodel *oldmod = NULL; + + for (; mod ; mod = mod->BSIM3v1AnextModel) + { if(oldmod) FREE(oldmod); + oldmod = mod; + prev = (BSIM3v1Ainstance *)NULL; + for (here = mod->BSIM3v1Ainstances; here; here = here->BSIM3v1AnextInstance) + { if(prev) FREE(prev); + prev = here; + } + if(prev) FREE(prev); + } + if(oldmod) FREE(oldmod); + *model = NULL; + return; +} + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1agetic.c b/src/spicelib/devices/bsim3v1a/b3v1agetic.c new file mode 100644 index 000000000..6a2055bcf --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1agetic.c @@ -0,0 +1,45 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1agetic.c +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + + +int +BSIM3v1Agetic(GENmodel *inModel, CKTcircuit *ckt) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; + + for (; model ; model = model->BSIM3v1AnextModel) + { for (here = model->BSIM3v1Ainstances; here; here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + if(!here->BSIM3v1AicVBSGiven) + { here->BSIM3v1AicVBS = *(ckt->CKTrhs + here->BSIM3v1AbNode) + - *(ckt->CKTrhs + here->BSIM3v1AsNode); + } + if (!here->BSIM3v1AicVDSGiven) + { here->BSIM3v1AicVDS = *(ckt->CKTrhs + here->BSIM3v1AdNode) + - *(ckt->CKTrhs + here->BSIM3v1AsNode); + } + if (!here->BSIM3v1AicVGSGiven) + { here->BSIM3v1AicVGS = *(ckt->CKTrhs + here->BSIM3v1AgNode) + - *(ckt->CKTrhs + here->BSIM3v1AsNode); + } + } + } + return(OK); +} + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1ald.c b/src/spicelib/devices/bsim3v1a/b3v1ald.c new file mode 100644 index 000000000..491b7e423 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1ald.c @@ -0,0 +1,1947 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1991 JianHui Huang and Min-Chie Jeng. +File: b3v1ald.c 1/3/92 +Modified by Mansun Chan (1995) +Modified by Paolo Nenzi 2002 +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "trandefs.h" +#include "const.h" +#include "sperror.h" +#include "devdefs.h" +#include "suffix.h" + +#define MAX_EXP 5.834617425e14 +#define MIN_EXP 1.713908431e-15 +#define EXP_THRESHOLD 34.0 +#define EPSOX 3.453133e-11 +#define EPSSI 1.03594e-10 +#define Charge_q 1.60219e-19 +#define DELTA_1 0.02 +#define DELTA_2 0.02 +#define DELTA_3 0.02 +#define DELTA_4 0.02 + + +int +BSIM3v1Aload(GENmodel *inModel, CKTcircuit *ckt) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; +double SourceSatCurrent, DrainSatCurrent; +double ag0, qgd, qgs, qgb, von, cbhat, VgstNVt, ExpVgst; +double cdrain, cdhat, cdreq, ceqbd, ceqbs, ceqqb, ceqqd, ceqqg, ceq, geq; +double czbd, czbdsw, czbs, czbssw, evbd, evbs, arg, sarg; +double delvbd, delvbs, delvds, delvgd, delvgs; +double Vfbeff, dVfbeff_dVg, dVfbeff_dVd, dVfbeff_dVb, V3, V4; +double gcbdb, gcbgb, gcbsb, gcddb, gcdgb, gcdsb, gcgdb, gcggb, gcgsb, gcsdb; +double gcsgb, gcssb, tol, PhiB, PhiBSW, MJ, MJSW; +double vbd, vbs, vds, vgb, vgd, vgs, vgdo, xfact; +double qgate, qbulk, qdrn, qsrc, cqgate, cqbulk, cqdrn; +double Vds, Vgs, Vbs, Gmbs, FwdSum, RevSum; +double Vgs_eff, Vfb, dVfb_dVb, dVfb_dVd, dVbs_dVb; +double Phis, dPhis_dVb, sqrtPhis, dsqrtPhis_dVb, Vth, dVth_dVb, dVth_dVd; +double Vgst, dVgs_eff_dVg; +double Vgdt, Vgsaddvth, Vgsaddvth2, Vgsaddvth1o3, n, dn_dVb, Vtm; +double ExpArg, ExpArg1; +double Denomi, dDenomi_dVg, dDenomi_dVd, dDenomi_dVb; +double ueff, dueff_dVg, dueff_dVd, dueff_dVb; +double Esat, dEsat_dVg, dEsat_dVd, dEsat_dVb, Vdsat, Vdsat0; +double EsatL, dEsatL_dVg, dEsatL_dVd, dEsatL_dVb; +double Ilimit, Iexp, dIexp_dVg, dIexp_dVd, dIexp_dVb; +double dVdsat_dVg, dVdsat_dVb, dVdsat_dVd, Vasat, dAlphaz_dVg, dAlphaz_dVb; +double dVasat_dVg, dVasat_dVb, dVasat_dVd, Va, Va2, dVa_dVd, dVa_dVg, dVa_dVb; +double Vbseff, dVbseff_dVb, VbseffCV, dVbseffCV_dVb; +double Arg1, Arg2, One_Third_CoxWL, Two_Third_CoxWL, Alphaz, CoxWL; +double dqbulk_dVb, dVgdt_dVg, dVgdt_dVd, dVgdt_dVb; +double T0, dT0_dVg, dT0_dVd, dT0_dVb; +double T1, dT1_dVg, dT1_dVd, dT1_dVb; +double T2, dT2_dVg, dT2_dVd, dT2_dVb; +double T3, dT3_dVg, dT3_dVd, dT3_dVb; +double T4, dT4_dVg, dT4_dVd, dT4_dVb; +double T5, dT5_dVg, dT5_dVd, dT5_dVb; +double T6, dT6_dVg, dT6_dVd, dT6_dVb; +double T7, dT7_dVg, dT7_dVd, dT7_dVb; +double T8, dT8_dVg, dT8_dVd, dT8_dVb; +double T9, dT9_dVg, dT9_dVd, dT9_dVb; +double T10, dT10_dVg, dT10_dVb, dT10_dVd; +double tmp, Abulk, dAbulk_dVb, Abulk0, dAbulk0_dVb; +double T100, T101; +double VACLM, dVACLM_dVg, dVACLM_dVd, dVACLM_dVb; +double VADIBL, dVADIBL_dVg, dVADIBL_dVd, dVADIBL_dVb; +double VAHCE, dVAHCE_dVg, dVAHCE_dVd, dVAHCE_dVb; +double Xdep, dXdep_dVb, lt1, dlt1_dVb, ltw, dltw_dVb, Delt_vth, dDelt_vth_dVb; +double Theta0, dTheta0_dVb, Theta1, dTheta1_dVb; +double Thetarout, dThetarout_dVb, TempRatio, tmp1, tmp2, tmp3, tmp4; +double DIBL_Sft, dDIBL_Sft_dVd, DIBL_fact, Pmos_factor; +double Rout_Vgs_factor, dRout_Vgs_factor_dVg, dRout_Vgs_factor_dVb; +double dRout_Vgs_factor_dVd; +double tempv, a1; + +double Vgsteff, dVgsteff_dVg, dVgsteff_dVd, dVgsteff_dVb; +double Vdseff, dVdseff_dVg, dVdseff_dVd, dVdseff_dVb; +double VdseffCV, dVdseffCV_dVg, dVdseffCV_dVd, dVdseffCV_dVb; +double diffVds, diffVdsCV; +double dAbulk_dVg, dn_dVd ; +double beta, dbeta_dVg, dbeta_dVd, dbeta_dVb; +double gche, dgche_dVg, dgche_dVd, dgche_dVb; +double fgche1, dfgche1_dVg, dfgche1_dVd, dfgche1_dVb; +double fgche2, dfgche2_dVg, dfgche2_dVd, dfgche2_dVb; +double Idl, dIdl_dVg, dIdl_dVd, dIdl_dVb; +double Idsa, dIdsa_dVg, dIdsa_dVd, dIdsa_dVb; +double Ids, Gm, Gds, Gmb; +double Isub, Isubd, Isubs, Gbd, Gbg, Gbb; +double VASCBE, dVASCBE_dVg, dVASCBE_dVd, dVASCBE_dVb; +double CoxWovL; +double Rds, dRds_dVg, dRds_dVb, WVCox, WVCoxRds; +double Vgst2Vtm, VdsatCV, dVdsatCV_dVd, dVdsatCV_dVg, dVdsatCV_dVb; +double Leff, Weff, dWeff_dVg, dWeff_dVb; +double AbulkCV, dAbulkCV_dVb; +double qgdo, qgso, cgdo, cgso; + +double qcheq, qdef, gqdef, cqdef, cqcheq, gtau_diff, gtau_drift, csreq; +double gcqdb,gcqsb,gcqgb,gcqbb,vss; +double dxpart, sxpart; + +double gbspsp, gbbdp, gbbsp, gbspg, gbspb, gbspdp; +double gbdpdp, gbdpg, gbdpb, gbdpsp; +double Cgg, Cgd, Cgs, Cgb, Cdg, Cdd, Cds, Cdb, Qg, Qd; +double Csg, Csd, Css, Csb, Cbg, Cbd, Cbs, Cbb, Qs, Qb; +double Cgg1, Cgb1, Cgd1, Cbg1, Cbb1, Cbd1, Csg1, Csd1, Csb1, Qac0, Qsub0; +double dQac0_dVg, dQac0_dVd, dQac0_dVb, dQsub0_dVg, dQsub0_dVd, dQsub0_dVb; + +double m; + +struct bsim3v1aSizeDependParam *pParam; +int ByPass, Check, ChargeComputationNeeded, J, error, I; +double junk[50]; + +for (; model != NULL; model = model->BSIM3v1AnextModel) +{ for (here = model->BSIM3v1Ainstances; here != NULL; + here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + + Check = 1; + ByPass = 0; + pParam = here->pParam; + if ((ckt->CKTmode & MODEINITSMSIG)) + { vbs = *(ckt->CKTstate0 + here->BSIM3v1Avbs); + vgs = *(ckt->CKTstate0 + here->BSIM3v1Avgs); + vds = *(ckt->CKTstate0 + here->BSIM3v1Avds); + qdef = *(ckt->CKTstate0 + here->BSIM3v1Aqcdump); + } + else if ((ckt->CKTmode & MODEINITTRAN)) + { vbs = *(ckt->CKTstate1 + here->BSIM3v1Avbs); + vgs = *(ckt->CKTstate1 + here->BSIM3v1Avgs); + vds = *(ckt->CKTstate1 + here->BSIM3v1Avds); + qdef = *(ckt->CKTstate1 + here->BSIM3v1Aqcdump); + } + else if ((ckt->CKTmode & MODEINITJCT) && !here->BSIM3v1Aoff) + { vds = model->BSIM3v1Atype * here->BSIM3v1AicVDS; + vgs = model->BSIM3v1Atype * here->BSIM3v1AicVGS; + vbs = model->BSIM3v1Atype * here->BSIM3v1AicVBS; + qdef = 0.0; + + if ((vds == 0.0) && (vgs == 0.0) && (vbs == 0.0) && + ((ckt->CKTmode & (MODETRAN | MODEAC|MODEDCOP | + MODEDCTRANCURVE)) || (!(ckt->CKTmode & MODEUIC)))) + { vbs = 0.0; + vgs = pParam->BSIM3v1Avth0 + 0.1; + vds = 0.1; + } + } + else if ((ckt->CKTmode & (MODEINITJCT | MODEINITFIX)) && + (here->BSIM3v1Aoff)) + { qdef = vbs = vgs = vds = 0.0; + } + else + { +#ifndef PREDICTOR + if ((ckt->CKTmode & MODEINITPRED)) + { xfact = ckt->CKTdelta / ckt->CKTdeltaOld[1]; + *(ckt->CKTstate0 + here->BSIM3v1Avbs) = + *(ckt->CKTstate1 + here->BSIM3v1Avbs); + vbs = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v1Avbs)) + - (xfact * (*(ckt->CKTstate2 + here->BSIM3v1Avbs))); + *(ckt->CKTstate0 + here->BSIM3v1Avgs) = + *(ckt->CKTstate1 + here->BSIM3v1Avgs); + vgs = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v1Avgs)) + - (xfact * (*(ckt->CKTstate2 + here->BSIM3v1Avgs))); + *(ckt->CKTstate0 + here->BSIM3v1Avds) = + *(ckt->CKTstate1 + here->BSIM3v1Avds); + vds = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v1Avds)) + - (xfact * (*(ckt->CKTstate2 + here->BSIM3v1Avds))); + *(ckt->CKTstate0 + here->BSIM3v1Avbd) = + *(ckt->CKTstate0 + here->BSIM3v1Avbs) + - *(ckt->CKTstate0 + here->BSIM3v1Avds); + qdef = (1.0 + xfact)* (*(ckt->CKTstate1 + here->BSIM3v1Aqcdump)) + -(xfact * (*(ckt->CKTstate2 + here->BSIM3v1Aqcdump))); + } + else + { +#endif /* PREDICTOR */ + vbs = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld + here->BSIM3v1AbNode) + - *(ckt->CKTrhsOld + here->BSIM3v1AsNodePrime)); + vgs = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld + here->BSIM3v1AgNode) + - *(ckt->CKTrhsOld + here->BSIM3v1AsNodePrime)); + vds = model->BSIM3v1Atype + * (*(ckt->CKTrhsOld + here->BSIM3v1AdNodePrime) + - *(ckt->CKTrhsOld + here->BSIM3v1AsNodePrime)); + qdef = *(ckt->CKTrhsOld + here->BSIM3v1AqNode); +#ifndef PREDICTOR + } +#endif /* PREDICTOR */ + + vbd = vbs - vds; + vgd = vgs - vds; + vgdo = *(ckt->CKTstate0 + here->BSIM3v1Avgs) + - *(ckt->CKTstate0 + here->BSIM3v1Avds); + delvbs = vbs - *(ckt->CKTstate0 + here->BSIM3v1Avbs); + delvbd = vbd - *(ckt->CKTstate0 + here->BSIM3v1Avbd); + delvgs = vgs - *(ckt->CKTstate0 + here->BSIM3v1Avgs); + delvds = vds - *(ckt->CKTstate0 + here->BSIM3v1Avds); + delvgd = vgd - vgdo; + + if (here->BSIM3v1Amode >= 0) + { cdhat = here->BSIM3v1Acd - here->BSIM3v1Agbd * delvbd + + here->BSIM3v1Agmbs * delvbs + here->BSIM3v1Agm * delvgs + + here->BSIM3v1Agds * delvds; + } + else + { cdhat = here->BSIM3v1Acd - (here->BSIM3v1Agbd - here->BSIM3v1Agmbs) + * delvbd - here->BSIM3v1Agm * delvgd + + here->BSIM3v1Agds * delvds; + + } + cbhat = here->BSIM3v1Acbs + here->BSIM3v1Acbd + here->BSIM3v1Agbd + * delvbd + here->BSIM3v1Agbs * delvbs; + +#ifndef NOBYPASS + /* following should be one big if connected by && all over + * the place, but some C compilers can't handle that, so + * we split it up here to let them digest it in stages + */ + + if ((!(ckt->CKTmode & MODEINITPRED)) && (ckt->CKTbypass)) + if ((fabs(delvbs) < (ckt->CKTreltol * MAX(fabs(vbs), + fabs(*(ckt->CKTstate0+here->BSIM3v1Avbs))) + ckt->CKTvoltTol))) + if ((fabs(delvbd) < (ckt->CKTreltol * MAX(fabs(vbd), + fabs(*(ckt->CKTstate0+here->BSIM3v1Avbd))) + ckt->CKTvoltTol))) + if ((fabs(delvgs) < (ckt->CKTreltol * MAX(fabs(vgs), + fabs(*(ckt->CKTstate0+here->BSIM3v1Avgs))) + ckt->CKTvoltTol))) + if ((fabs(delvds) < (ckt->CKTreltol * MAX(fabs(vds), + fabs(*(ckt->CKTstate0+here->BSIM3v1Avds))) + ckt->CKTvoltTol))) + if ((fabs(cdhat - here->BSIM3v1Acd) < ckt->CKTreltol + * MAX(fabs(cdhat),fabs(here->BSIM3v1Acd)) + ckt->CKTabstol)) + { tempv = MAX(fabs(cbhat),fabs(here->BSIM3v1Acbs + + here->BSIM3v1Acbd)) + ckt->CKTabstol; + if ((fabs(cbhat - (here->BSIM3v1Acbs + here->BSIM3v1Acbd)) + < ckt->CKTreltol * tempv)) + { /* bypass code */ + vbs = *(ckt->CKTstate0 + here->BSIM3v1Avbs); + vbd = *(ckt->CKTstate0 + here->BSIM3v1Avbd); + vgs = *(ckt->CKTstate0 + here->BSIM3v1Avgs); + vds = *(ckt->CKTstate0 + here->BSIM3v1Avds); + qcheq = *(ckt->CKTstate0 + here->BSIM3v1Aqcheq); + + vgd = vgs - vds; + vgb = vgs - vbs; + + cdrain = here->BSIM3v1Amode * (here->BSIM3v1Acd + + here->BSIM3v1Acbd); + if ((ckt->CKTmode & (MODETRAN | MODEAC)) || + ((ckt->CKTmode & MODETRANOP) && + (ckt->CKTmode & MODEUIC))) + { ByPass = 1; + goto line755; + } + else + { goto line850; + } + } + } + +#endif /*NOBYPASS*/ + von = here->BSIM3v1Avon; + if (*(ckt->CKTstate0 + here->BSIM3v1Avds) >= 0.0) + { vgs = DEVfetlim(vgs, *(ckt->CKTstate0+here->BSIM3v1Avgs), von); + vds = vgs - vgd; + vds = DEVlimvds(vds, *(ckt->CKTstate0 + here->BSIM3v1Avds)); + vgd = vgs - vds; + + } + else + { vgd = DEVfetlim(vgd, vgdo, von); + vds = vgs - vgd; + vds = -DEVlimvds(-vds, -(*(ckt->CKTstate0+here->BSIM3v1Avds))); + vgs = vgd + vds; + } + + if (vds >= 0.0) + { vbs = DEVpnjlim(vbs, *(ckt->CKTstate0 + here->BSIM3v1Avbs), + CONSTvt0, model->BSIM3v1Avcrit, &Check); + vbd = vbs - vds; + + } + else + { vbd = DEVpnjlim(vbd, *(ckt->CKTstate0 + here->BSIM3v1Avbd), + CONSTvt0, model->BSIM3v1Avcrit, &Check); + vbs = vbd + vds; + } + } + + /* determine DC current and derivatives */ + vbd = vbs - vds; + vgd = vgs - vds; + vgb = vgs - vbs; + + m=here->BSIM3v1Am; + + SourceSatCurrent = here->BSIM3v1AsourceArea*model->BSIM3v1AjctSatCurDensity; + if (here->BSIM3v1AsourceArea <= 0.0) + SourceSatCurrent = 1.0e-14; + if (SourceSatCurrent <= 0.0) + { here->BSIM3v1Agbs = ckt->CKTgmin/m; + here->BSIM3v1Acbs = here->BSIM3v1Agbs * vbs; + } + + else if (vbs <= -3*CONSTvt0) + { arg=3*CONSTvt0/(vbs*CONSTe); + arg = arg * arg * arg; + here->BSIM3v1Acbs = -SourceSatCurrent*(1+arg)+(ckt->CKTgmin/m)*vbs; + here->BSIM3v1Agbs = SourceSatCurrent*3*arg/vbs+(ckt->CKTgmin/m); + } + + else if (vbs < 0.5) + { evbs = exp(vbs / CONSTvt0); + here->BSIM3v1Agbs = SourceSatCurrent * evbs / CONSTvt0 + + (ckt->CKTgmin/m); + + here->BSIM3v1Acbs = SourceSatCurrent * (evbs - 1.0) + + (ckt->CKTgmin/m) * vbs; + + } + else + { evbs = exp(0.5 / CONSTvt0); + here->BSIM3v1Agbs = SourceSatCurrent * evbs / CONSTvt0 + + (ckt->CKTgmin/m); + + here->BSIM3v1Acbs = SourceSatCurrent * (evbs - 1.0) + + (ckt->CKTgmin/m) * 0.5; + + + here->BSIM3v1Acbs += here->BSIM3v1Agbs * (vbs - 0.5); + + } + + DrainSatCurrent = here->BSIM3v1AdrainArea * model->BSIM3v1AjctSatCurDensity; + if (here->BSIM3v1AdrainArea <= 0.0) + DrainSatCurrent = 1.0e-14; + if (DrainSatCurrent <= 0.0) + { here->BSIM3v1Agbd = ckt->CKTgmin/m; + + here->BSIM3v1Acbd = here->BSIM3v1Agbd * vbd; + } + + else if (vbd <= -3*CONSTvt0) + { arg=3*CONSTvt0/(vbd*CONSTe); + arg = arg * arg * arg; + + here->BSIM3v1Acbd = -DrainSatCurrent*(1+arg)+(ckt->CKTgmin/m)*vbd; + here->BSIM3v1Agbd = DrainSatCurrent*3*arg/vbd+(ckt->CKTgmin/m); + + } + + else if (vbd < 0.5) + { evbd = exp(vbd/CONSTvt0); + here->BSIM3v1Agbd = DrainSatCurrent * evbd / CONSTvt0 + + (ckt->CKTgmin/m); + + here->BSIM3v1Acbd = DrainSatCurrent * (evbd - 1.0) + + (ckt->CKTgmin/m) * vbd; + + } + else + { evbd = exp(0.5/CONSTvt0); + here->BSIM3v1Agbd = DrainSatCurrent * evbd / CONSTvt0 + + (ckt->CKTgmin/m); + + here->BSIM3v1Acbd = DrainSatCurrent * (evbd - 1.0) + + (ckt->CKTgmin/m) * 0.5; + + + here->BSIM3v1Acbd += here->BSIM3v1Agbd * (vbd - 0.5); + + } + + if (vds >= 0.0) + { /* normal mode */ + here->BSIM3v1Amode = 1; + Vds = vds; + Vgs = vgs; + Vbs = vbs; + } + else + { /* inverse mode */ + here->BSIM3v1Amode = -1; + Vds = -vds; + Vgs = vgd; + Vbs = vbd; + } + + ChargeComputationNeeded = + ((ckt->CKTmode & (MODEAC | MODETRAN | MODEINITSMSIG)) || + ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC))) + ? 1 : 0; + + T0 = Vbs - pParam->BSIM3v1Avbsc - 0.001; + T1 = sqrt(T0 * T0 - 0.004 * pParam->BSIM3v1Avbsc); + Vbseff = pParam->BSIM3v1Avbsc + 0.5 * (T0 + T1); + dVbseff_dVb = 0.5 * (1.0 + T0 / T1); + + if (Vbseff > 0.0) + { T0 = pParam->BSIM3v1Aphi / (pParam->BSIM3v1Aphi + Vbseff); + Phis = pParam->BSIM3v1Aphi * T0; + dPhis_dVb = -T0 * T0; + sqrtPhis = pParam->BSIM3v1Aphis3 / (pParam->BSIM3v1Aphi + 0.5 * Vbseff); + dsqrtPhis_dVb = -0.5 * sqrtPhis * sqrtPhis / pParam->BSIM3v1Aphis3; + } + else + { Phis = pParam->BSIM3v1Aphi - Vbseff; + dPhis_dVb = -1.0; + sqrtPhis = sqrt(Phis); + dsqrtPhis_dVb = -0.5 / sqrtPhis; + } + Xdep = pParam->BSIM3v1AXdep0 * sqrtPhis / pParam->BSIM3v1AsqrtPhi; + dXdep_dVb = (pParam->BSIM3v1AXdep0 / pParam->BSIM3v1AsqrtPhi) + * dsqrtPhis_dVb; + + Leff = pParam->BSIM3v1Aleff; +/* Vth Calculation */ + if ((T1 = 1.0 + pParam->BSIM3v1Advt2 * Vbseff) < 1.0e-10) + T1 = 1.0E-10; + if ((T2 = 1.0 + pParam->BSIM3v1Advt2w * Vbseff) < 1.0E-10) + T2 = 1.0E-10; + + T3 = sqrt(Xdep); + lt1 = model->BSIM3v1Afactor1 * T3 * T1; + dlt1_dVb = model->BSIM3v1Afactor1 * (0.5 / T3 * T1 * dXdep_dVb + + T3 * pParam->BSIM3v1Advt2); + + ltw = model->BSIM3v1Afactor1 * T3 * T2; + dltw_dVb = model->BSIM3v1Afactor1 * (0.5 / T3 * T2 * dXdep_dVb + + T3 * pParam->BSIM3v1Advt2w); + + T0 = -0.5 * pParam->BSIM3v1Advt1 * Leff / lt1; + if (T0 > -EXP_THRESHOLD) + { T1 = exp(T0); + dT1_dVb = -T0 / lt1 * T1 * dlt1_dVb; + } + else + { T1 = MIN_EXP; + dT1_dVb = 0.0; + } + + Theta0 = T1 * (1.0 + 2.0 * T1); + dTheta0_dVb = (1.0 + 4.0 * T1) * dT1_dVb; + + here->BSIM3v1Athetavth = pParam->BSIM3v1Advt0 * Theta0; + T0 = pParam->BSIM3v1Avbi - pParam->BSIM3v1Aphi; + Delt_vth = here->BSIM3v1Athetavth * T0; + dDelt_vth_dVb = pParam->BSIM3v1Advt0 * dTheta0_dVb * T0; + + T0 = -0.5 * pParam->BSIM3v1Advt1w * pParam->BSIM3v1Aweff * Leff / ltw; + if (T0 > -EXP_THRESHOLD) + { T1 = exp(T0); + dT1_dVb = -T0 / ltw * T1 * dltw_dVb; + } + else + { T1 = MIN_EXP; + dT1_dVb = 0.0; + } + + T2 = T1 * (1.0 + 2.0 * T1); + dT2_dVb = (1.0 + 4.0 * T1) * dT1_dVb; + + T0 = pParam->BSIM3v1Advt0w * T2; + T1 = pParam->BSIM3v1Avbi - pParam->BSIM3v1Aphi; + T2 = T0 * T1; + dT2_dVb = pParam->BSIM3v1Advt0w * dT2_dVb * T1; + + TempRatio = ckt->CKTtemp / model->BSIM3v1Atnom - 1.0; + T0 = sqrt(1.0 + pParam->BSIM3v1Anlx / Leff); + T1 = pParam->BSIM3v1Ak1 * (T0 - 1.0) * pParam->BSIM3v1AsqrtPhi + + (pParam->BSIM3v1Akt1 + pParam->BSIM3v1Akt1l / Leff + + pParam->BSIM3v1Akt2 * Vbseff) * TempRatio; + tmp2 = model->BSIM3v1Atox / (pParam->BSIM3v1Aweff + + pParam->BSIM3v1Aw0) * pParam->BSIM3v1Aphi; + + dDIBL_Sft_dVd = (pParam->BSIM3v1Aeta0 + pParam->BSIM3v1Aetab + * Vbseff) * pParam->BSIM3v1Atheta0vb0; + DIBL_Sft = dDIBL_Sft_dVd * Vds; + + Vth = model->BSIM3v1Atype * pParam->BSIM3v1Avth0 + pParam->BSIM3v1Ak1 + * (sqrtPhis - pParam->BSIM3v1AsqrtPhi) - pParam->BSIM3v1Ak2 + * Vbseff - Delt_vth - T2 + (pParam->BSIM3v1Ak3 + pParam->BSIM3v1Ak3b + * Vbseff) * tmp2 + T1 - DIBL_Sft; + + here->BSIM3v1Avon = Vth; + + dVth_dVb = pParam->BSIM3v1Ak1 * dsqrtPhis_dVb - pParam->BSIM3v1Ak2 + - dDelt_vth_dVb - dT2_dVb + pParam->BSIM3v1Ak3b * tmp2 + - pParam->BSIM3v1Aetab * Vds * pParam->BSIM3v1Atheta0vb0 + + pParam->BSIM3v1Akt2 * TempRatio; + dVth_dVd = -dDIBL_Sft_dVd; + +/* Calculate n */ + tmp2 = pParam->BSIM3v1Anfactor * EPSSI / Xdep; + tmp3 = pParam->BSIM3v1Acdsc + pParam->BSIM3v1Acdscb * Vbseff + + pParam->BSIM3v1Acdscd * Vds; + n = 1.0 + (tmp2 + tmp3 * Theta0 + pParam->BSIM3v1Acit) / model->BSIM3v1Acox; + if (n > 1.0) + { dn_dVb = (-tmp2 / Xdep * dXdep_dVb + tmp3 * dTheta0_dVb + + pParam->BSIM3v1Acdscb * Theta0) / model->BSIM3v1Acox; + dn_dVd = pParam->BSIM3v1Acdscd * Theta0 / model->BSIM3v1Acox; + } + else + { n = 1.0; + dn_dVb = dn_dVd = 0.0; + } + +/* Poly Gate Si Depletion Effect */ + T0 = pParam->BSIM3v1Avfb + pParam->BSIM3v1Aphi; + if (model->BSIM3v1AngateGiven && (Vgs > T0)) + { T1 = 1.0e6 * Charge_q * EPSSI * pParam->BSIM3v1Angate + / (model->BSIM3v1Acox * model->BSIM3v1Acox); + T4 = sqrt(1.0 + 2.0 * (Vgs - T0) / T1); + T2 = T1 * (T4 - 1.0); + T3 = 0.5 * T2 * T2 / T1; + + if (T3 < 1.12) + { Vgs_eff = T0 + T2; + dVgs_eff_dVg = 1.0 / T4; + } + else + { Vgs_eff = Vgs - 1.12; + dVgs_eff_dVg = 1.0; + } + } + else + { Vgs_eff = Vgs; + dVgs_eff_dVg = 1.0; + } + Vgst = Vgs_eff - Vth; + +/* Effective Vgst (Vgsteff) Calculation */ + Vtm = model->BSIM3v1Avtm; + + T10 = 2.0 * n * Vtm; + VgstNVt = Vgst / T10; + if (VgstNVt < -EXP_THRESHOLD) + { T1 = T10 * MIN_EXP; + dT1_dVg = dT1_dVd = dT1_dVb = 0.0; + } + else if (VgstNVt > EXP_THRESHOLD) + { T1 = Vgst; + dT1_dVg = dVgs_eff_dVg; + dT1_dVd = -dVth_dVd; + dT1_dVb = -dVth_dVb; + } + else + { ExpVgst = exp(VgstNVt); + T1 = T10 * log(1.0 + ExpVgst); + dT1_dVg = ExpVgst / (1.0 + ExpVgst); + dT1_dVb = -dT1_dVg * (dVth_dVb + Vgst / n * dn_dVb) + + T1 / n * dn_dVb; + dT1_dVd = -dT1_dVg * (dVth_dVd + Vgst / n * dn_dVd) + + T1 / n * dn_dVd; + dT1_dVg *= dVgs_eff_dVg; + } + + T2 = model->BSIM3v1Atox / (pParam->BSIM3v1Aweff + pParam->BSIM3v1Aw0); + ExpArg = (2.0 * pParam->BSIM3v1Avoff - Vgst) / T10; + if (ExpArg < -EXP_THRESHOLD) + { T2 = 1.0; + dT2_dVg = dT2_dVd = dT2_dVb = 0.0; + + } + else if (ExpArg > EXP_THRESHOLD) + { T2 = 1.0 + 2.0 * n * model->BSIM3v1Acox / pParam->BSIM3v1Acdep0 + * MAX_EXP; + dT2_dVg = dT2_dVd = dT2_dVb = 0.0; + } + else + { dT2_dVg = -model->BSIM3v1Acox / Vtm / pParam->BSIM3v1Acdep0 + * exp(ExpArg); + T2 = 1.0 - T10 * dT2_dVg; + dT2_dVd = -dT2_dVg * (dVth_dVd - 2.0 * Vtm + * ExpArg * dn_dVd) + (T2 - 1.0) / n * dn_dVd; + dT2_dVb = -dT2_dVg * (dVth_dVb - 2.0 * Vtm + * ExpArg * dn_dVb) + (T2 - 1.0) / n * dn_dVb; + dT2_dVg *= dVgs_eff_dVg; + } + + Vgsteff = T1 / T2; + dVgsteff_dVg = (T2 * dT1_dVg - T1 * dT2_dVg) / (T2 * T2); + dVgsteff_dVd = (T2 * dT1_dVd - T1 * dT2_dVd) / (T2 * T2); + dVgsteff_dVb = (T2 * dT1_dVb - T1 * dT2_dVb) / (T2 * T2); + +/* Calculate Effective Channel Geometry */ + Weff = pParam->BSIM3v1Aweff - 2.0 * (pParam->BSIM3v1Adwg * Vgsteff + + pParam->BSIM3v1Adwb * (sqrtPhis - pParam->BSIM3v1AsqrtPhi)); + dWeff_dVg = -2.0 * pParam->BSIM3v1Adwg; + dWeff_dVb = -2.0 * pParam->BSIM3v1Adwb * dsqrtPhis_dVb; + + if (Weff < 1.0e-8) + { Weff = 1.0e-8; + dWeff_dVg = dWeff_dVb = 0; + } + + Rds = pParam->BSIM3v1Ards0 * (1.0 + pParam->BSIM3v1Aprwg * Vgsteff + + pParam->BSIM3v1Aprwb * (sqrtPhis - pParam->BSIM3v1AsqrtPhi)); + if (Rds > 0.0) + { dRds_dVg = pParam->BSIM3v1Ards0 * pParam->BSIM3v1Aprwg; + dRds_dVb = pParam->BSIM3v1Ards0 * pParam->BSIM3v1Aprwb * dsqrtPhis_dVb; + } + else + { Rds = dRds_dVg = dRds_dVb = 0.0; + } + + WVCox = Weff * pParam->BSIM3v1Avsattemp * model->BSIM3v1Acox; + WVCoxRds = WVCox * Rds; + +/* Calculate Abulk */ + T0 = 1.0 / (1.0 + pParam->BSIM3v1Aketa * Vbseff); + dT0_dVb = -pParam->BSIM3v1Aketa * T0 * T0; + + T1 = 0.5 * pParam->BSIM3v1Ak1 / sqrtPhis; + dT1_dVb = -T1 / sqrtPhis * dsqrtPhis_dVb; + + tmp1 = Leff + 2.0 * sqrt(pParam->BSIM3v1Axj * Xdep); + T5 = Leff / tmp1; + tmp2 = pParam->BSIM3v1Aa0 *T5; + tmp3 = pParam->BSIM3v1Aweff + pParam->BSIM3v1Ab1; + tmp4 = pParam->BSIM3v1Ab0 / tmp3; + T2 = tmp2 + tmp4; + dT2_dVb = -tmp2 / tmp1 * sqrt(pParam->BSIM3v1Axj / Xdep) * dXdep_dVb; + T6 = T5 * T5; + T7 = T5 * T6; + Abulk0 = T0 * (1.0 + T1 * T2); + if (Abulk0 < 0.01) + Abulk0= 0.01; + T8 = pParam->BSIM3v1Aags * pParam->BSIM3v1Aa0 * T7; + dAbulk_dVg = -T1 * T0 * T8; + Abulk = Abulk0 + dAbulk_dVg * Vgsteff; + if (Abulk < 0.01) + Abulk= 0.01; + + dAbulk0_dVb = T0 * T1 * dT2_dVb + T0 * T2 * dT1_dVb + + (1.0 + T1 * T2) * dT0_dVb; + dAbulk_dVb = dAbulk0_dVb - T8 * Vgsteff * (T1 * (3.0 * T0 * dT2_dVb + / tmp2 + dT0_dVb) + T0 * dT1_dVb); +/* Mobility calculation */ + + if (model->BSIM3v1AmobMod == 1) + { T0 = Vgsteff + Vth + Vth; + T2 = pParam->BSIM3v1Aua + pParam->BSIM3v1Auc * Vbseff; + T3 = T0 / model->BSIM3v1Atox; + Denomi = 1.0 + T3 * (T2 + + pParam->BSIM3v1Aub * T3); + T1 = T2 / model->BSIM3v1Atox + 2.0 * pParam->BSIM3v1Aub * T3 + / model->BSIM3v1Atox; + dDenomi_dVg = T1; + dDenomi_dVd = T1 * 2.0 * dVth_dVd; + dDenomi_dVb = T1 * 2.0 * dVth_dVb + pParam->BSIM3v1Auc * T3; + } + else if (model->BSIM3v1AmobMod == 2) + { Denomi = 1.0 + Vgsteff / model->BSIM3v1Atox * (pParam->BSIM3v1Aua + + pParam->BSIM3v1Auc * Vbseff + pParam->BSIM3v1Aub * Vgsteff + / model->BSIM3v1Atox); + T1 = (pParam->BSIM3v1Aua + pParam->BSIM3v1Auc * Vbseff) / model->BSIM3v1Atox + + 2.0 * pParam->BSIM3v1Aub / (model->BSIM3v1Atox * model->BSIM3v1Atox) + * Vgsteff; + dDenomi_dVg = T1; + dDenomi_dVd = 0.0; + dDenomi_dVb = Vgsteff * pParam->BSIM3v1Auc / model->BSIM3v1Atox; + } + else + { T0 = Vgsteff + Vth + Vth; + T2 = 1.0 + pParam->BSIM3v1Auc * Vbseff; + T3 = T0 / model->BSIM3v1Atox; + T4 = T3 * (pParam->BSIM3v1Aua + pParam->BSIM3v1Aub * T3); + Denomi = 1.0 + T4 * T2; + + T1 = (pParam->BSIM3v1Aua / model->BSIM3v1Atox + 2.0 * pParam->BSIM3v1Aub + * T3 / model->BSIM3v1Atox) * T2; + dDenomi_dVg = T1; + dDenomi_dVd = T1 * 2.0 * dVth_dVd; + dDenomi_dVb = T1 * 2.0 * dVth_dVb + pParam->BSIM3v1Auc * T4; + } + + here->BSIM3v1Aueff = ueff = pParam->BSIM3v1Au0temp / Denomi; + dueff_dVg = -ueff / Denomi * dDenomi_dVg; + dueff_dVd = -ueff / Denomi * dDenomi_dVd; + dueff_dVb = -ueff / Denomi * dDenomi_dVb; + + +/* Saturation Drain Voltage Vdsat */ + Esat = 2.0 * pParam->BSIM3v1Avsattemp / ueff; + EsatL = Esat * Leff; + T0 = -EsatL /ueff; + dEsatL_dVg = T0 * dueff_dVg; + dEsatL_dVd = T0 * dueff_dVd; + dEsatL_dVb = T0 * dueff_dVb; + + a1 = pParam->BSIM3v1Aa1; + if ((Pmos_factor = a1 * Vgsteff + pParam->BSIM3v1Aa2) > 1.0) + { Pmos_factor = 1.0; + a1 = 0.0; + } + + Vgst2Vtm = Vgsteff + 2.0 * Vtm; + if ((Rds == 0.0) && (Pmos_factor == 1.0)) + { T0 = 1.0 / (Abulk * EsatL + Vgst2Vtm); + here->BSIM3v1Avdsat = Vdsat = EsatL * Vgst2Vtm * T0; + + dT0_dVg = -(Abulk * dEsatL_dVg +EsatL*dAbulk_dVg+ 1.0) * T0 * T0; + dT0_dVd = -(Abulk * dEsatL_dVd) * T0 * T0; + dT0_dVb = -(Abulk * dEsatL_dVb + dAbulk_dVb * EsatL) * T0 * T0; + + dVdsat_dVg = EsatL * Vgst2Vtm * dT0_dVg + EsatL * T0 + + Vgst2Vtm * T0 * dEsatL_dVg; + dVdsat_dVd = EsatL * Vgst2Vtm * dT0_dVd + + Vgst2Vtm * T0 * dEsatL_dVd; + dVdsat_dVb = EsatL * Vgst2Vtm * dT0_dVb + + Vgst2Vtm * T0 * dEsatL_dVb; + } + else + { tmp1 = a1 / (Pmos_factor * Pmos_factor); + if (Rds > 0) + { tmp2 = dRds_dVg / Rds + dWeff_dVg / Weff; + tmp3 = dRds_dVb / Rds + dWeff_dVb / Weff; + } + else + { tmp2 = dWeff_dVg / Weff; + tmp3 = dWeff_dVb / Weff; + } + + T0 = 2.0 * Abulk * (Abulk * WVCoxRds - 1.0 + 1.0 / Pmos_factor); + dT0_dVg = 2.0 * (Abulk * Abulk * WVCoxRds * tmp2 - Abulk * tmp1 + + (2.0 * WVCoxRds * Abulk + 1.0 / Pmos_factor - 1.0) + * dAbulk_dVg); + + dT0_dVb = 2.0 * (Abulk * Abulk * WVCoxRds * (2.0 / Abulk + * dAbulk_dVb + tmp3) + (1.0 / Pmos_factor - 1.0) + * dAbulk_dVb); + dT0_dVd= 0.0; + T1 = Vgst2Vtm * (2.0 / Pmos_factor - 1.0) + Abulk + * EsatL + 3.0 * Abulk * Vgst2Vtm * WVCoxRds; + + dT1_dVg = (2.0 / Pmos_factor - 1.0) - 2.0 * Vgst2Vtm * tmp1 + + Abulk * dEsatL_dVg + EsatL * dAbulk_dVg + 3.0 * (Abulk + * WVCoxRds + Abulk * Vgst2Vtm * WVCoxRds * tmp2 + Vgst2Vtm + * WVCoxRds * dAbulk_dVg); + dT1_dVb = Abulk * dEsatL_dVb + EsatL * dAbulk_dVb + + 3.0 * (Vgst2Vtm * WVCoxRds * dAbulk_dVb + + Abulk * Vgst2Vtm * WVCoxRds * tmp3); + dT1_dVd = Abulk * dEsatL_dVd; + + T2 = Vgst2Vtm * (EsatL + 2.0 * Vgst2Vtm * WVCoxRds); + dT2_dVg = EsatL + Vgst2Vtm * dEsatL_dVg + Vgst2Vtm * WVCoxRds + * (4.0 + 2.0 * Vgst2Vtm * tmp2); + dT2_dVb = Vgst2Vtm * dEsatL_dVb + 2.0 * Vgst2Vtm * WVCoxRds + * Vgst2Vtm * tmp3; + dT2_dVd = Vgst2Vtm * dEsatL_dVd; + + T3 = sqrt(T1 * T1 - 2.0 * T0 * T2); + here->BSIM3v1Avdsat = Vdsat = (T1 - T3) / T0; + + dT3_dVg = (T1 * dT1_dVg - 2.0 * (T0 * dT2_dVg + T2 * dT0_dVg)) + / T3; + dT3_dVd = (T1 * dT1_dVd - 2.0 * (T0 * dT2_dVd + T2 * dT0_dVd)) + / T3; + dT3_dVb = (T1 * dT1_dVb - 2.0 * (T0 * dT2_dVb + T2 * dT0_dVb)) + / T3; + + T4 = T1 - T3; + dT4_dVg = - dT1_dVg - dT3_dVg; + dT4_dVd = - dT1_dVd - dT3_dVd; + dT4_dVb = - dT1_dVb - dT3_dVb; + + dVdsat_dVg = (dT1_dVg - (T1 * dT1_dVg - dT0_dVg * T2 + - T0 * dT2_dVg) / T3 - Vdsat * dT0_dVg) / T0; + dVdsat_dVb = (dT1_dVb - (T1 * dT1_dVb - dT0_dVb * T2 + - T0 * dT2_dVb) / T3 - Vdsat * dT0_dVb) / T0; + dVdsat_dVd = (dT1_dVd - (T1 * dT1_dVd - T0 * dT2_dVd) / T3) / T0; + } + +/* Effective Vds (Vdseff) Calculation */ + T1 = Vdsat - Vds - pParam->BSIM3v1Adelta; + dT1_dVg = dVdsat_dVg; + dT1_dVd = dVdsat_dVd - 1.0; + dT1_dVb = dVdsat_dVb; + + T2 = sqrt(T1 * T1 + 4.0 * pParam->BSIM3v1Adelta * Vdsat); + T0 = T1 / T2; + T3 = 2.0 * pParam->BSIM3v1Adelta / T2; + dT2_dVg = T0 * dT1_dVg + T3 * dVdsat_dVg; + dT2_dVd = T0 * dT1_dVd + T3 * dVdsat_dVd; + dT2_dVb = T0 * dT1_dVb + T3 * dVdsat_dVb; + + Vdseff = Vdsat - 0.5 * (T1 + T2); + dVdseff_dVg = dVdsat_dVg - 0.5 * (dT1_dVg + dT2_dVg); + dVdseff_dVd = dVdsat_dVd - 0.5 * (dT1_dVd + dT2_dVd); + dVdseff_dVb = dVdsat_dVb - 0.5 * (dT1_dVb + dT2_dVb); + +/* Calculate VAsat */ + tmp1 = a1 / (Pmos_factor * Pmos_factor); + if (Rds > 0) + { tmp2 = dRds_dVg / Rds + dWeff_dVg / Weff; + tmp3 = dRds_dVb / Rds + dWeff_dVb / Weff; + } + else + { tmp2 = dWeff_dVg / Weff; + tmp3 = dWeff_dVb / Weff; + } + tmp4 = 1.0 - 0.5 * Abulk * Vdsat / Vgst2Vtm; + T0 = EsatL + Vdsat + 2.0 * WVCoxRds * Vgsteff * tmp4; + + dT0_dVg = dEsatL_dVg + dVdsat_dVg + 2.0 * WVCoxRds * tmp4 + * (1.0 + tmp2 * Vgsteff) - WVCoxRds * Vgsteff / Vgst2Vtm + * (Abulk * dVdsat_dVg - Abulk * Vdsat / Vgst2Vtm + + Vdsat * dAbulk_dVg); + + dT0_dVb = dEsatL_dVb + dVdsat_dVb + 2.0 * WVCoxRds * tmp4 * tmp3 + * Vgsteff - WVCoxRds * Vgsteff / Vgst2Vtm * (dAbulk_dVb + * Vdsat + Abulk * dVdsat_dVb); + dT0_dVd = dEsatL_dVd + dVdsat_dVd - WVCoxRds * Vgsteff / Vgst2Vtm + * Abulk * dVdsat_dVd; + + T1 = 2.0 / Pmos_factor - 1.0 + WVCoxRds * Abulk; + dT1_dVg = -2.0 * tmp1 + WVCoxRds *(Abulk * tmp2+ dAbulk_dVg); + dT1_dVb = dAbulk_dVb * WVCoxRds + Abulk * WVCoxRds * tmp3; + + Vasat = T0 / T1; + dVasat_dVg = (dT0_dVg - T0 / T1 * dT1_dVg) / T1; + dVasat_dVb = (dT0_dVb - T0 / T1 * dT1_dVb) / T1; + dVasat_dVd = dT0_dVd / T1; + + diffVds = Vds - Vdseff; +/* Calculate VACLM */ + if (pParam->BSIM3v1Apclm > 0.0) + { T0 = 1.0 / (pParam->BSIM3v1Apclm * Abulk * pParam->BSIM3v1Alitl); + dT0_dVb = -T0 / Abulk * dAbulk_dVb; + dT0_dVg= - T0/Abulk*dAbulk_dVg; + + T2 = Vgsteff / EsatL; + T1 = Leff * (Abulk + T2); + dT1_dVg = Leff * ((1.0 - T2 * dEsatL_dVg) / EsatL+dAbulk_dVg); + dT1_dVb = Leff * (dAbulk_dVb - T2 * dEsatL_dVb / EsatL); + dT1_dVd = -T2 * dEsatL_dVd / Esat; + + VACLM = T0 * T1 * diffVds; + dVACLM_dVg = T0 * dT1_dVg * diffVds - T0 * T1 * dVdseff_dVg + + T1 * diffVds * dT0_dVg; + dVACLM_dVb = (dT0_dVb * T1 + T0 * dT1_dVb) * diffVds + - T0 * T1 * dVdseff_dVb; + dVACLM_dVd = T0 * dT1_dVd * diffVds + + T0 * T1 * (1.0 - dVdseff_dVd); + } + else + { VACLM = MAX_EXP; + dVACLM_dVd = dVACLM_dVg = dVACLM_dVb = 0.0; + } + +/* Calculate VADIBL */ + if (pParam->BSIM3v1AthetaRout > 0.0) + { T0 = Vgst2Vtm * Abulk * Vdsat; + dT0_dVg = Vgst2Vtm * Abulk * dVdsat_dVg + Abulk * Vdsat + + Vgst2Vtm * Vdsat * dAbulk_dVg; + dT0_dVb = Vgst2Vtm * (dAbulk_dVb * Vdsat + Abulk * dVdsat_dVb); + dT0_dVd = Vgst2Vtm * Abulk * dVdsat_dVd; + + T1 = Vgst2Vtm + Abulk * Vdsat; + dT1_dVg = 1.0 + Abulk * dVdsat_dVg + Vdsat * dAbulk_dVg; + dT1_dVb = Abulk * dVdsat_dVb + dAbulk_dVb * Vdsat; + dT1_dVd = Abulk * dVdsat_dVd; + + T2 = pParam->BSIM3v1AthetaRout * (1.0 + pParam->BSIM3v1Apdiblb * Vbseff); + VADIBL = (Vgst2Vtm - T0 / T1) / T2; + dVADIBL_dVg = (1.0 - dT0_dVg / T1 + T0 * dT1_dVg / (T1 * T1)) / T2; + dVADIBL_dVb = ((-dT0_dVb / T1 + T0 * dT1_dVb / (T1 * T1)) - VADIBL + * pParam->BSIM3v1AthetaRout * pParam->BSIM3v1Apdiblb) / T2; + dVADIBL_dVd = (-dT0_dVd / T1 + T0 * dT1_dVd / (T1 * T1)) / T2; + } + else + { VADIBL = MAX_EXP; + dVADIBL_dVd = dVADIBL_dVg = dVADIBL_dVb = 0.0; + } + +/* Calculate VA */ + T0 = 1.0 + pParam->BSIM3v1Apvag * Vgsteff / EsatL; + dT0_dVg = pParam->BSIM3v1Apvag * (1.0 - Vgsteff * dEsatL_dVg + / EsatL) / EsatL; + dT0_dVb = -pParam->BSIM3v1Apvag * Vgsteff * dEsatL_dVb + / EsatL / EsatL; + dT0_dVd = -pParam->BSIM3v1Apvag * Vgsteff * dEsatL_dVd + / EsatL / EsatL; + + tmp1 = VACLM * VACLM; + tmp2 = VADIBL * VADIBL; + tmp3 = VACLM + VADIBL; + + T1 = VACLM * VADIBL / tmp3; + tmp3 *= tmp3; + dT1_dVg = (tmp1 * dVADIBL_dVg + tmp2 * dVACLM_dVg) / tmp3; + dT1_dVd = (tmp1 * dVADIBL_dVd + tmp2 * dVACLM_dVd) / tmp3; + dT1_dVb = (tmp1 * dVADIBL_dVb + tmp2 * dVACLM_dVb) / tmp3; + + Va = Vasat + T0 * T1; + dVa_dVg = dVasat_dVg + T1 * dT0_dVg + T0 * dT1_dVg; + dVa_dVd = dVasat_dVd + T1 * dT0_dVd + T0 * dT1_dVd; + dVa_dVb = dVasat_dVb + T1 * dT0_dVb + T0 * dT1_dVb; + +/* Calculate VASCBE */ + if ((diffVds) && ((T0 = pParam->BSIM3v1Apscbe1 * pParam->BSIM3v1Alitl + / diffVds) > 0.0) && (T0 < EXP_THRESHOLD)) + { VASCBE = Leff * exp(T0) / pParam->BSIM3v1Apscbe2; + T1 = T0 * VASCBE / diffVds; + dVASCBE_dVg = T1 * dVdseff_dVg; + dVASCBE_dVd = -T1 * (1.0 - dVdseff_dVd); + dVASCBE_dVb = T1 * dVdseff_dVb; + } + else + { VASCBE = MAX_EXP*Leff/pParam->BSIM3v1Apscbe2; + dVASCBE_dVg = dVASCBE_dVd = dVASCBE_dVb = 0.0; + } + +/* Calculate Ids */ + CoxWovL = model->BSIM3v1Acox * Weff / Leff; + beta = ueff * CoxWovL; + dbeta_dVg = CoxWovL * dueff_dVg + beta * dWeff_dVg / Weff; + dbeta_dVd = CoxWovL * dueff_dVd; + dbeta_dVb = CoxWovL * dueff_dVb + beta * dWeff_dVb / Weff; + + T0 = 1.0 - 0.5 * Abulk * Vdseff / Vgst2Vtm; + dT0_dVg = -0.5 * (Abulk * dVdseff_dVg + - Abulk * Vdseff / Vgst2Vtm+Vdseff*dAbulk_dVg) / Vgst2Vtm; + dT0_dVd = -0.5 * Abulk * dVdseff_dVd / Vgst2Vtm; + dT0_dVb = -0.5 * (Abulk * dVdseff_dVb + dAbulk_dVb * Vdseff) + / Vgst2Vtm; + + fgche1 = Vgsteff * T0; + dfgche1_dVg = Vgsteff * dT0_dVg + T0; + dfgche1_dVd = Vgsteff * dT0_dVd; + dfgche1_dVb = Vgsteff * dT0_dVb; + + fgche2 = 1.0 + Vdseff / EsatL; + dfgche2_dVg = (dVdseff_dVg - Vdseff / EsatL * dEsatL_dVg) / EsatL; + dfgche2_dVd = (dVdseff_dVd - Vdseff / EsatL * dEsatL_dVd) / EsatL; + dfgche2_dVb = (dVdseff_dVb - Vdseff / EsatL * dEsatL_dVb) / EsatL; + + gche = beta * fgche1 / fgche2; + dgche_dVg = (beta * dfgche1_dVg + fgche1 * dbeta_dVg + - gche * dfgche2_dVg) / fgche2; + dgche_dVd = (beta * dfgche1_dVd + fgche1 * dbeta_dVd + - gche * dfgche2_dVd) / fgche2; + dgche_dVb = (beta * dfgche1_dVb + fgche1 * dbeta_dVb + - gche * dfgche2_dVb) / fgche2; + + T0 = 1.0 + gche * Rds; + Idl = gche * Vdseff / T0; + + dIdl_dVg = (gche * dVdseff_dVg + Vdseff * dgche_dVg / T0) / T0 + - Idl * gche / T0 * dRds_dVg ; + + dIdl_dVd = (gche * dVdseff_dVd + Vdseff * dgche_dVd / T0) / T0; + dIdl_dVb = (gche * dVdseff_dVb + Vdseff * dgche_dVb / T0 + - Idl * dRds_dVb * gche) / T0; + + T0 = 1.0 + diffVds / Va; + Idsa = Idl * T0; + dIdsa_dVg = T0 * dIdl_dVg - Idl * (dVdseff_dVg + diffVds / Va + * dVa_dVg) / Va; + dIdsa_dVd = T0 * dIdl_dVd + Idl * (1.0 - dVdseff_dVd - diffVds / Va + * dVa_dVd) / Va; + dIdsa_dVb = T0 * dIdl_dVb - Idl * (dVdseff_dVb + diffVds / Va + * dVa_dVb) / Va; + + T0 = 1.0 + diffVds / VASCBE; + Ids = Idsa * T0; + + Gm = T0 * dIdsa_dVg - Idsa * (dVdseff_dVg + diffVds / VASCBE + * dVASCBE_dVg) / VASCBE; + Gds = T0 * dIdsa_dVd + Idsa * (1.0 - dVdseff_dVd - diffVds / VASCBE + * dVASCBE_dVd) / VASCBE; + Gmb = T0 * dIdsa_dVb - Idsa * (dVdseff_dVb + diffVds / VASCBE + * dVASCBE_dVb) / VASCBE; + + Gds += Gm * dVgsteff_dVd; + Gmb += Gm * dVgsteff_dVb; + Gm *= dVgsteff_dVg; + Gmb *= dVbseff_dVb; + +/* calculate substrate current Isub */ + if ((pParam->BSIM3v1Aalpha0 <= 0.0) || (pParam->BSIM3v1Abeta0 <= 0.0)) + { Isub = Gbd = Gbb = Gbg = 0.0; + } + else + { T2 = pParam->BSIM3v1Aalpha0 / Leff; + if (diffVds<0.0) { + diffVds=0.0; + Vdseff=Vds; + } /* added to avoid the hardwrae problem + when Vds=0 */ + + if ((diffVds != 0.0) && ((T0 = -pParam->BSIM3v1Abeta0 / diffVds) + > -EXP_THRESHOLD)) + { T1 = T2 * diffVds * exp(T0); + dT1_dVg = T1 / diffVds * (T0 - 1.0) * dVdseff_dVg; + dT1_dVd = T1 / diffVds * (1.0 - T0) * (1.0 - dVdseff_dVd); + dT1_dVb = T1 / diffVds * (T0 - 1.0) * dVdseff_dVb; + } + else + { T1 = T2 * diffVds * MIN_EXP; + dT1_dVg = -T2 * MIN_EXP * dVdseff_dVg; + dT1_dVd = T2 * MIN_EXP * (1.0 - dVdseff_dVd); + dT1_dVb = -T2 * MIN_EXP * dVdseff_dVb; + } + Isub = T1 * Idsa; + Gbg = T1 * dIdsa_dVg + Idsa * dT1_dVg; + Gbd = T1 * dIdsa_dVd + Idsa * dT1_dVd; + Gbb = T1 * dIdsa_dVb + Idsa * dT1_dVb; + + Gbd += Gbg * dVgsteff_dVd; + Gbb += Gbg * dVgsteff_dVb; + Gbg *= dVgsteff_dVg; + Gbg *= dVbseff_dVb; + } + + cdrain = Ids; + here->BSIM3v1Agds = Gds; + here->BSIM3v1Agm = Gm; + here->BSIM3v1Agmbs = Gmb; + + here->BSIM3v1Agbbs = Gbb; + here->BSIM3v1Agbgs = Gbg; + here->BSIM3v1Agbds = Gbd; + + here->BSIM3v1Acsub = Isub - (Gbb * Vbseff + Gbd * Vds + Gbg * Vgs); + +/* Calculate Qinv for Noise analysis */ + + T1 = Vgsteff * (1.0 - 0.5 * Abulk * Vdseff / Vgst2Vtm); + here->BSIM3v1Aqinv = -model->BSIM3v1Acox * Weff * Leff * T1; + + if ((model->BSIM3v1Axpart < 0) || (!ChargeComputationNeeded)) + { qgate = qdrn = qsrc = qbulk = 0.0; + here->BSIM3v1Acggb = here->BSIM3v1Acgsb = here->BSIM3v1Acgdb = 0.0; + here->BSIM3v1Acdgb = here->BSIM3v1Acdsb = here->BSIM3v1Acddb = 0.0; + here->BSIM3v1Acbgb = here->BSIM3v1Acbsb = here->BSIM3v1Acbdb = 0.0; + here->BSIM3v1Acqdb = here->BSIM3v1Acqsb = here->BSIM3v1Acqgb + = here->BSIM3v1Acqbb = 0.0; + here->BSIM3v1Agtau = 0.0; + goto finished; + } + else + { if (Vbseff < 0.0) + { VbseffCV = Vbseff; + dVbseffCV_dVb = 1.0; + } + else + { VbseffCV = pParam->BSIM3v1Aphi - Phis; + dVbseffCV_dVb = -dPhis_dVb; + } + + CoxWL = model->BSIM3v1Acox * pParam->BSIM3v1AweffCV + * pParam->BSIM3v1AleffCV; + Vfb = Vth - pParam->BSIM3v1Aphi - pParam->BSIM3v1Ak1 * sqrtPhis; + + dVfb_dVb = dVth_dVb - pParam->BSIM3v1Ak1 * dsqrtPhis_dVb; + dVfb_dVd = dVth_dVd; + + if ((VgstNVt > -EXP_THRESHOLD) && (VgstNVt < EXP_THRESHOLD)) + { ExpVgst *= ExpVgst; + Vgsteff = n * Vtm * log(1.0 + ExpVgst); + dVgsteff_dVg = ExpVgst / (1.0 + ExpVgst); + dVgsteff_dVd = -dVgsteff_dVg * (dVth_dVd + (Vgs_eff - Vth) + / n * dn_dVd) + Vgsteff / n * dn_dVd; + dVgsteff_dVb = -dVgsteff_dVg * (dVth_dVb + (Vgs_eff - Vth) + / n * dn_dVb) + Vgsteff / n * dn_dVb; + dVgsteff_dVg *= dVgs_eff_dVg; + } + + if (model->BSIM3v1AcapMod == 1) + { Arg1 = Vgs_eff - VbseffCV - Vfb; + + if (Arg1 <= 0.0) + { qgate = CoxWL * (Arg1 - Vgsteff); + Cgg = CoxWL * (dVgs_eff_dVg - dVgsteff_dVg); + Cgd = -CoxWL * (dVfb_dVd + dVgsteff_dVd); + Cgb = -CoxWL * (dVfb_dVb + dVbseffCV_dVb + dVgsteff_dVb); + } + else + { T0 = 0.5 * pParam->BSIM3v1Ak1; + T1 = sqrt(T0 * T0 + Arg1 - Vgsteff); + qgate = CoxWL * pParam->BSIM3v1Ak1 * (T1 - T0); + + T2 = CoxWL * T0 / T1; + Cgg = T2 * (dVgs_eff_dVg - dVgsteff_dVg); + Cgd = -T2 * (dVfb_dVd + dVgsteff_dVd); + Cgb = -T2 * (dVfb_dVb + dVbseffCV_dVb + dVgsteff_dVb); + } + qbulk = -qgate; + Cbg = -Cgg; + Cbd = -Cgd; + Cbb = -Cgb; + + One_Third_CoxWL = CoxWL / 3.0; + Two_Third_CoxWL = 2.0 * One_Third_CoxWL; + AbulkCV = Abulk0 * pParam->BSIM3v1AabulkCVfactor; + dAbulkCV_dVb = pParam->BSIM3v1AabulkCVfactor * dAbulk0_dVb; + VdsatCV = Vgsteff / AbulkCV; + if (VdsatCV <= Vds) + { dVdsatCV_dVg = 1.0 / AbulkCV; + dVdsatCV_dVb = -VdsatCV * dAbulkCV_dVb / AbulkCV; + T0 = Vgsteff - VdsatCV / 3.0; + dT0_dVg = 1.0 - dVdsatCV_dVg / 3.0; + dT0_dVb = -dVdsatCV_dVb / 3.0; + qgate += CoxWL * T0; + Cgg1 = CoxWL * dT0_dVg; + Cgb1 = CoxWL * dT0_dVb + Cgg1 * dVgsteff_dVb; + Cgd1 = Cgg1 * dVgsteff_dVd; + Cgg1 *= dVgsteff_dVg; + Cgg += Cgg1; + Cgb += Cgb1; + Cgd += Cgd1; + + T0 = VdsatCV - Vgsteff; + dT0_dVg = dVdsatCV_dVg - 1.0; + dT0_dVb = dVdsatCV_dVb; + qbulk += One_Third_CoxWL * T0; + Cbg1 = One_Third_CoxWL * dT0_dVg; + Cbb1 = One_Third_CoxWL * dT0_dVb + Cbg1 * dVgsteff_dVb; + Cbd1 = Cbg1 * dVgsteff_dVd; + Cbg1 *= dVgsteff_dVg; + Cbg += Cbg1; + Cbb += Cbb1; + Cbd += Cbd1; + + if (model->BSIM3v1Axpart > 0.5) + T0 = -Two_Third_CoxWL; + else if (model->BSIM3v1Axpart < 0.5) + T0 = -0.4 * CoxWL; + else + T0 = -One_Third_CoxWL; + + qsrc = T0 * Vgsteff; + Csg = T0 * dVgsteff_dVg; + Csb = T0 * dVgsteff_dVb; + Csd = T0 * dVgsteff_dVd; + Cgb *= dVbseff_dVb; + Cbb *= dVbseff_dVb; + Csb *= dVbseff_dVb; + } + else + { T0 = AbulkCV * Vds; + T1 = 12.0 * (Vgsteff - 0.5 * T0); + T2 = Vds / T1; + T3 = T0 * T2; + dT3_dVg = -12.0 * T2 * T2 * AbulkCV; + dT3_dVd = 6.0 * T0 * (4.0 * Vgsteff - T0) / T1 / T1 - 0.5; + dT3_dVb = 12.0 * T2 * T2 * dAbulkCV_dVb * Vgsteff; + + qgate += CoxWL * (Vgsteff - 0.5 * Vds + T3); + Cgg1 = CoxWL * (1.0 + dT3_dVg); + Cgb1 = CoxWL * dT3_dVb + Cgg1 * dVgsteff_dVb; + Cgd1 = CoxWL * dT3_dVd + Cgg1 * dVgsteff_dVd; + Cgg1 *= dVgsteff_dVg; + Cgg += Cgg1; + Cgb += Cgb1; + Cgd += Cgd1; + + qbulk += CoxWL * (1.0 - AbulkCV) * (0.5 * Vds - T3); + Cbg1 = -CoxWL * ((1.0 - AbulkCV) * dT3_dVg); + Cbb1 = -CoxWL * ((1.0 - AbulkCV) * dT3_dVb + + (0.5 * Vds - T3) * dAbulkCV_dVb) + + Cbg1 * dVgsteff_dVb; + Cbd1 = -CoxWL * (1.0 - AbulkCV) * dT3_dVd + + Cbg1 * dVgsteff_dVd; + Cbg1 *= dVgsteff_dVg; + Cbg += Cbg1; + Cbb += Cbb1; + Cbd += Cbd1; + + if (model->BSIM3v1Axpart > 0.5) + { /* 0/100 Charge petition model */ + T1 = T1 + T1; + qsrc = -CoxWL * (0.5 * Vgsteff + 0.25 * T0 + - T0 * T0 / T1); + Csg = -CoxWL * (0.5 + 24.0 * T0 * Vds / T1 / T1 + * AbulkCV); + Csb = -CoxWL * (0.25 * Vds * dAbulkCV_dVb + - 12.0 * T0 * Vds / T1 / T1 * (4.0 * Vgsteff - T0) + * dAbulkCV_dVb) + Csg * dVgsteff_dVb; + Csd = -CoxWL * (0.25 * AbulkCV - 12.0 * AbulkCV * T0 + / T1 / T1 * (4.0 * Vgsteff - T0)) + + Csg * dVgsteff_dVd; + Csg *= dVgsteff_dVg; + } + else if (model->BSIM3v1Axpart < 0.5) + { /* 40/60 Charge petition model */ + T1 = T1 / 12.0; + T2 = 0.5 * CoxWL / (T1 * T1); + T3 = Vgsteff * (2.0 * T0 * T0 / 3.0 + Vgsteff + * (Vgsteff - 4.0 * T0 / 3.0)) + - 2.0 * T0 * T0 * T0 / 15.0; + qsrc = -T2 * T3; + T4 = 4.0 / 3.0 * Vgsteff * (Vgsteff - T0) + + 0.4 * T0 * T0; + Csg = -2.0 * qsrc / T1 - T2 * (Vgsteff * (3.0 + * Vgsteff - 8.0 * T0 / 3.0) + + 2.0 * T0 * T0 / 3.0); + Csb = (qsrc / T1 * Vds + T2 * T4 * Vds) * dAbulkCV_dVb + + Csg * dVgsteff_dVb; + Csd = (qsrc / T1 + T2 * T4) * AbulkCV + + Csg * dVgsteff_dVd; + Csg *= dVgsteff_dVg; + } + else + { /* 50/50 Charge petition model */ + qsrc = -0.5 * (qgate + qbulk); + Csg = -0.5 * (Cgg1 + Cbg1); + Csb = -0.5 * (Cgb1 + Cbb1); + Csd = -0.5 * (Cgd1 + Cbd1); + } + Cgb *= dVbseff_dVb; + Cbb *= dVbseff_dVb; + Csb *= dVbseff_dVb; + } + qdrn = -(qgate + qbulk + qsrc); + here->BSIM3v1Acggb = Cgg; + here->BSIM3v1Acgsb = -(Cgg + Cgd + Cgb); + here->BSIM3v1Acgdb = Cgd; + here->BSIM3v1Acdgb = -(Cgg + Cbg + Csg); + here->BSIM3v1Acdsb = (Cgg + Cgd + Cgb + Cbg + Cbd + Cbb + + Csg + Csd + Csb); + here->BSIM3v1Acddb = -(Cgd + Cbd + Csd); + here->BSIM3v1Acbgb = Cbg; + here->BSIM3v1Acbsb = -(Cbg + Cbd + Cbb); + here->BSIM3v1Acbdb = Cbd; + } + else + { V3 = Vfb - Vgs_eff + VbseffCV - DELTA_3; + if (Vfb <= 0.0) + { T0 = sqrt(V3 * V3 - 4.0 * DELTA_3 * Vfb); + T2 = -DELTA_3 / T0; + } + else + { T0 = sqrt(V3 * V3 + 4.0 * DELTA_3 * Vfb); + T2 = DELTA_3 / T0; + } + + T1 = 0.5 * (1.0 + V3 / T0); + Vfbeff = Vfb - 0.5 * (V3 + T0); + dVfbeff_dVd = (1.0 - T1 - T2) * dVfb_dVd; + dVfbeff_dVg = T1 * dVgs_eff_dVg; + dVfbeff_dVb = (1.0 - T1 - T2) * dVfb_dVb + - T1 * dVbseffCV_dVb; + Qac0 = CoxWL * (Vfbeff - Vfb); + dQac0_dVg = CoxWL * dVfbeff_dVg; + dQac0_dVd = CoxWL * (dVfbeff_dVd - dVfb_dVd); + dQac0_dVb = CoxWL * (dVfbeff_dVb - dVfb_dVb); + + T0 = 0.5 * pParam->BSIM3v1Ak1; + T1 = sqrt(T0 * T0 + Vgs_eff - Vfbeff - VbseffCV - Vgsteff); + + Qsub0 = CoxWL * pParam->BSIM3v1Ak1 * (T1 - T0); + + T2 = CoxWL * T0 / T1; + dQsub0_dVg = T2 * (dVgs_eff_dVg - dVfbeff_dVg - dVgsteff_dVg); + dQsub0_dVd = -T2 * (dVfbeff_dVd + dVgsteff_dVd); + dQsub0_dVb = -T2 * (dVfbeff_dVb + dVbseffCV_dVb + + dVgsteff_dVb); + + One_Third_CoxWL = CoxWL / 3.0; + Two_Third_CoxWL = 2.0 * One_Third_CoxWL; + AbulkCV = Abulk0 * pParam->BSIM3v1AabulkCVfactor; + dAbulkCV_dVb = pParam->BSIM3v1AabulkCVfactor * dAbulk0_dVb; + VdsatCV = Vgsteff / AbulkCV; + + V4 = VdsatCV - Vds - DELTA_4; + T0 = sqrt(V4 * V4 + 4.0 * DELTA_4 * VdsatCV); + VdseffCV = VdsatCV - 0.5 * (V4 + T0); + T1 = 0.5 * (1.0 + V4 / T0); + T2 = DELTA_4 / T0; + T3 = (1.0 - T1 - T2) / AbulkCV; + dVdseffCV_dVg = T3; + dVdseffCV_dVd = T1; + dVdseffCV_dVb = -T3 * VdsatCV * dAbulkCV_dVb; + + T0 = AbulkCV * VdseffCV; + T1 = 12.0 * (Vgsteff - 0.5 * T0 + 1e-20); + T2 = VdseffCV / T1; + T3 = T0 * T2; + + T4 = (1.0 - 12.0 * T2 * T2 * AbulkCV); + T5 = (6.0 * T0 * (4.0 * Vgsteff - T0) / (T1 * T1) - 0.5); + T6 = 12.0 * T2 * T2 * Vgsteff; + + qgate = CoxWL * (Vgsteff - 0.5 * VdseffCV + T3); + Cgg1 = CoxWL * (T4 + T5 * dVdseffCV_dVg); + Cgd1 = CoxWL * T5 * dVdseffCV_dVd + Cgg1 * dVgsteff_dVd; + Cgb1 = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb) + + Cgg1 * dVgsteff_dVb; + Cgg1 *= dVgsteff_dVg; + + T7 = 1.0 - AbulkCV; + qbulk = CoxWL * T7 * (0.5 * VdseffCV - T3); + T4 = -T7 * (T4 - 1.0); + T5 = -T7 * T5; + T6 = -(T7 * T6 + (0.5 * VdseffCV - T3)); + Cbg1 = CoxWL * (T4 + T5 * dVdseffCV_dVg); + Cbd1 = CoxWL * T5 * dVdseffCV_dVd + Cbg1 * dVgsteff_dVd; + Cbb1 = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb) + + Cbg1 * dVgsteff_dVb; + Cbg1 *= dVgsteff_dVg; + + if (model->BSIM3v1Axpart > 0.5) + { /* 0/100 Charge petition model */ + T1 = T1 + T1; + qsrc = -CoxWL * (0.5 * Vgsteff + 0.25 * T0 + - T0 * T0 / T1); + T7 = (4.0 * Vgsteff - T0) / (T1 * T1); + T4 = -(0.5 + 24.0 * T0 * T0 / (T1 * T1)); + T5 = -(0.25 * AbulkCV - 12.0 * AbulkCV * T0 * T7); + T6 = -(0.25 * VdseffCV - 12.0 * T0 * VdseffCV * T7); + Csg = CoxWL * (T4 + T5 * dVdseffCV_dVg); + Csd = CoxWL * T5 * dVdseffCV_dVd + Csg * dVgsteff_dVd; + Csb = CoxWL * (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb) + + Csg * dVgsteff_dVb; + Csg *= dVgsteff_dVg; + } + else if (model->BSIM3v1Axpart < 0.5) + { /* 40/60 Charge petition model */ + T1 = T1 / 12.0; + T2 = 0.5 * CoxWL / (T1 * T1); + T3 = Vgsteff * (2.0 * T0 * T0 / 3.0 + Vgsteff + * (Vgsteff - 4.0 * T0 / 3.0)) + - 2.0 * T0 * T0 * T0 / 15.0; + qsrc = -T2 * T3; + T7 = 4.0 / 3.0 * Vgsteff * (Vgsteff - T0) + + 0.4 * T0 * T0; + T4 = -2.0 * qsrc / T1 - T2 * (Vgsteff * (3.0 + * Vgsteff - 8.0 * T0 / 3.0) + + 2.0 * T0 * T0 / 3.0); + T5 = (qsrc / T1 + T2 * T7) * AbulkCV; + T6 = (qsrc / T1 * VdseffCV + T2 * T7 * VdseffCV); + Csg = (T4 + T5 * dVdseffCV_dVg); + Csd = T5 * dVdseffCV_dVd + Csg * dVgsteff_dVd; + Csb = (T5 * dVdseffCV_dVb + T6 * dAbulkCV_dVb) + + Csg * dVgsteff_dVb; + Csg *= dVgsteff_dVg; + } + else + { /* 50/50 Charge petition model */ + qsrc = -0.5 * (qgate + qbulk); + Csg = -0.5 * (Cgg1 + Cbg1); + Csb = -0.5 * (Cgb1 + Cbb1); + Csd = -0.5 * (Cgd1 + Cbd1); + } + + qgate += Qac0 + Qsub0; + qbulk -= (Qac0 + Qsub0); + qdrn = -(qgate + qbulk + qsrc); + + Cgg = dQac0_dVg + dQsub0_dVg + Cgg1; + Cgd = dQac0_dVd + dQsub0_dVd + Cgd1; + Cgb = dQac0_dVb + dQsub0_dVb + Cgb1; + + Cbg = Cbg1 - dQac0_dVg - dQsub0_dVg; + Cbd = Cbd1 - dQac0_dVd - dQsub0_dVd; + Cbb = Cbb1 - dQac0_dVb - dQsub0_dVb; + + Cgb *= dVbseff_dVb; + Cbb *= dVbseff_dVb; + Csb *= dVbseff_dVb; + + here->BSIM3v1Acggb = Cgg; + here->BSIM3v1Acgsb = -(Cgg + Cgd + Cgb); + here->BSIM3v1Acgdb = Cgd; + here->BSIM3v1Acdgb = -(Cgg + Cbg + Csg); + here->BSIM3v1Acdsb = (Cgg + Cgd + Cgb + Cbg + Cbd + Cbb + + Csg + Csd + Csb); + here->BSIM3v1Acddb = -(Cgd + Cbd + Csd); + here->BSIM3v1Acbgb = Cbg; + here->BSIM3v1Acbsb = -(Cbg + Cbd + Cbb); + here->BSIM3v1Acbdb = Cbd; + + } + +/* Non-quasi-static Model */ + + if (here->BSIM3v1AnqsMod) + { + qcheq = -qbulk - qgate; + qbulk = qgate = qdrn = qsrc = 0.0; + + here->BSIM3v1Acqgb = -(here->BSIM3v1Acggb + here->BSIM3v1Acbgb); + here->BSIM3v1Acqdb = -(here->BSIM3v1Acgdb + here->BSIM3v1Acbdb); + here->BSIM3v1Acqsb = -(here->BSIM3v1Acgsb + here->BSIM3v1Acbsb); + here->BSIM3v1Acqbb = here->BSIM3v1Acggb + here->BSIM3v1Acgdb + + here->BSIM3v1Acgsb + here->BSIM3v1Acbgb + + here->BSIM3v1Acbdb + here->BSIM3v1Acbsb; + + here->BSIM3v1Acggb = here->BSIM3v1Acgsb = here->BSIM3v1Acgdb = 0.0; + here->BSIM3v1Acdgb = here->BSIM3v1Acdsb = here->BSIM3v1Acddb = 0.0; + here->BSIM3v1Acbgb = here->BSIM3v1Acbsb = here->BSIM3v1Acbdb = 0.0; + + T0 = pParam->BSIM3v1AleffCV * pParam->BSIM3v1AleffCV; + here->BSIM3v1Atconst = pParam->BSIM3v1Au0temp * pParam->BSIM3v1Aelm + / CoxWL / T0; + + if (qcheq == 0.0) + here->BSIM3v1Atconst = 0.0; + else if (qcheq < 0.0) + here->BSIM3v1Atconst = -here->BSIM3v1Atconst; + + gtau_drift = fabs(here->BSIM3v1Atconst * qcheq); + gtau_diff = 16.0 * pParam->BSIM3v1Au0temp * model->BSIM3v1Avtm / T0; + + here->BSIM3v1Agtau = gtau_drift + gtau_diff; + + *(ckt->CKTstate0 + here->BSIM3v1Aqcheq) = qcheq; + + if (ckt->CKTmode & MODEINITTRAN) + *(ckt->CKTstate1 + here->BSIM3v1Aqcheq) = + *(ckt->CKTstate0 + here->BSIM3v1Aqcheq); + + error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v1Aqcheq); + if (error) return (error); + } + else + { here->BSIM3v1Acqgb = here->BSIM3v1Acqdb = here->BSIM3v1Acqsb + = here->BSIM3v1Acqbb = 0.0; + here->BSIM3v1Agtau = 0.0; + } + } + +finished: /* returning Values to Calling Routine */ + /* + * COMPUTE EQUIVALENT DRAIN CURRENT SOURCE + */ + here->BSIM3v1Acd = here->BSIM3v1Amode * cdrain - here->BSIM3v1Acbd; + if (ChargeComputationNeeded) + { /* charge storage elements + * bulk-drain and bulk-source depletion capacitances + * czbd : zero bias drain junction capacitance + * czbs : zero bias source junction capacitance + * czbdsw:zero bias drain junction sidewall capacitance + * czbssw:zero bias source junction sidewall capacitance + */ + + czbd = model->BSIM3v1AunitAreaJctCap * here->BSIM3v1AdrainArea; + czbs = model->BSIM3v1AunitAreaJctCap * here->BSIM3v1AsourceArea; + czbdsw = model->BSIM3v1AunitLengthSidewallJctCap + * here->BSIM3v1AdrainPerimeter; + czbssw = model->BSIM3v1AunitLengthSidewallJctCap + * here->BSIM3v1AsourcePerimeter; + PhiB = model->BSIM3v1AbulkJctPotential; + PhiBSW = model->BSIM3v1AsidewallJctPotential; + MJ = model->BSIM3v1AbulkJctBotGradingCoeff; + MJSW = model->BSIM3v1AbulkJctSideGradingCoeff; + + /* Source Bulk Junction */ + if (vbs == 0.0) + { *(ckt->CKTstate0 + here->BSIM3v1Aqbs) = 0.0; + here->BSIM3v1Acapbs = czbs + czbssw; + } + else if (vbs < 0.0) + { if (czbs > 0.0) + { arg = 1.0 - vbs / PhiB; + if (MJ == 0.5) + sarg = 1.0 / sqrt(arg); + else + sarg = exp(-MJ * log(arg)); + *(ckt->CKTstate0 + here->BSIM3v1Aqbs) = PhiB * czbs + * (1.0 - arg * sarg) / (1.0 - MJ); + here->BSIM3v1Acapbs = czbs * sarg; + } + else + { *(ckt->CKTstate0 + here->BSIM3v1Aqbs) = 0.0; + here->BSIM3v1Acapbs = 0.0; + } + if (czbssw > 0.0) + { arg = 1.0 - vbs / PhiBSW; + if (MJSW == 0.5) + sarg = 1.0 / sqrt(arg); + else + sarg = exp(-MJSW * log(arg)); + *(ckt->CKTstate0 + here->BSIM3v1Aqbs) += PhiBSW * czbssw + * (1.0 - arg * sarg) / (1.0 - MJSW); + here->BSIM3v1Acapbs += czbssw * sarg; + } + } + else + { *(ckt->CKTstate0+here->BSIM3v1Aqbs) = vbs * (czbs + czbssw) + + vbs * vbs * (czbs * MJ * 0.5 / PhiB + + czbssw * MJSW * 0.5 / PhiBSW); + here->BSIM3v1Acapbs = czbs + czbssw + vbs * (czbs * MJ /PhiB + + czbssw * MJSW / PhiBSW ); + } + + /* Drain Bulk Junction */ + if (vbd == 0.0) + { *(ckt->CKTstate0 + here->BSIM3v1Aqbd) = 0.0; + here->BSIM3v1Acapbd = czbd + czbdsw; + } + else if (vbd < 0.0) + { if (czbd > 0.0) + { arg = 1.0 - vbd / PhiB; + if (MJ == 0.5) + sarg = 1.0 / sqrt(arg); + else + sarg = exp(-MJ * log(arg)); + *(ckt->CKTstate0 + here->BSIM3v1Aqbd) = PhiB * czbd + * (1.0 - arg * sarg) / (1.0 - MJ); + here->BSIM3v1Acapbd = czbd * sarg; + } + else + { *(ckt->CKTstate0 + here->BSIM3v1Aqbd) = 0.0; + here->BSIM3v1Acapbd = 0.0; + } + if (czbdsw > 0.0) + { arg = 1.0 - vbd / PhiBSW; + if (MJSW == 0.5) + sarg = 1.0 / sqrt(arg); + else + sarg = exp(-MJSW * log(arg)); + *(ckt->CKTstate0 + here->BSIM3v1Aqbd) += PhiBSW * czbdsw + * (1.0 - arg * sarg) / (1.0 - MJSW); + here->BSIM3v1Acapbd += czbdsw * sarg; + } + } + else + { *(ckt->CKTstate0+here->BSIM3v1Aqbd) = vbd * (czbd + czbdsw) + + vbd * vbd * (czbd * MJ * 0.5 / PhiB + + czbdsw * MJSW * 0.5 / PhiBSW); + here->BSIM3v1Acapbd = czbd + czbdsw + vbd * (czbd * MJ / PhiB + + czbdsw * MJSW / PhiBSW ); + } + } + + /* + * check convergence + */ + if ((here->BSIM3v1Aoff == 0) || (!(ckt->CKTmode & MODEINITFIX))) + { if (Check == 1) + { ckt->CKTnoncon++; + } + } + *(ckt->CKTstate0 + here->BSIM3v1Avbs) = vbs; + *(ckt->CKTstate0 + here->BSIM3v1Avbd) = vbd; + *(ckt->CKTstate0 + here->BSIM3v1Avgs) = vgs; + *(ckt->CKTstate0 + here->BSIM3v1Avds) = vds; + + /* bulk and channel charge plus overlaps */ + + if (!ChargeComputationNeeded) + goto line850; + +line755: + ag0 = ckt->CKTag[0]; + + if (model->BSIM3v1AcapMod == 1) + { if (vgd < 0.0) + { T1 = sqrt(1.0 - 4.0 * vgd / pParam->BSIM3v1Ackappa); + cgdo = pParam->BSIM3v1Acgdo + pParam->BSIM3v1AweffCV + * pParam->BSIM3v1Acgdl / T1; + qgdo = pParam->BSIM3v1Acgdo * vgd - pParam->BSIM3v1AweffCV * 0.5 + * pParam->BSIM3v1Acgdl * pParam->BSIM3v1Ackappa * (T1 - 1.0); + } + else + { cgdo = pParam->BSIM3v1Acgdo + pParam->BSIM3v1AweffCV + * pParam->BSIM3v1Acgdl; + qgdo = (pParam->BSIM3v1AweffCV * pParam->BSIM3v1Acgdl + + pParam->BSIM3v1Acgdo) * vgd; + } + + if (vgs < 0.0) + { T1 = sqrt(1.0 - 4.0 * vgs / pParam->BSIM3v1Ackappa); + cgso = pParam->BSIM3v1Acgso + pParam->BSIM3v1AweffCV + * pParam->BSIM3v1Acgsl / T1; + qgso = pParam->BSIM3v1Acgso * vgs - pParam->BSIM3v1AweffCV * 0.5 + * pParam->BSIM3v1Acgsl * pParam->BSIM3v1Ackappa * (T1 - 1.0); + } + else + { cgso = pParam->BSIM3v1Acgso + pParam->BSIM3v1AweffCV + * pParam->BSIM3v1Acgsl; + qgso = (pParam->BSIM3v1AweffCV * pParam->BSIM3v1Acgsl + + pParam->BSIM3v1Acgso) * vgs; + } + } + else + { T0 = vgd + DELTA_1; + T1 = sqrt(T0 * T0 + 4.0 * DELTA_1); + T2 = 0.5 * (T0 - T1); + + T3 = pParam->BSIM3v1AweffCV * pParam->BSIM3v1Acgdl; + T4 = sqrt(1.0 - 4.0 * T2 / pParam->BSIM3v1Ackappa); + cgdo = pParam->BSIM3v1Acgdo + T3 - T3 * (1.0 - 1.0 / T4) + * (0.5 - 0.5 * T0 / T1); + qgdo = (pParam->BSIM3v1Acgdo + T3) * vgd - T3 * (T2 + + 0.5 * pParam->BSIM3v1Ackappa * (T4 - 1.0)); + + T0 = vgs + DELTA_1; + T1 = sqrt(T0 * T0 + 4.0 * DELTA_1); + T2 = 0.5 * (T0 - T1); + T3 = pParam->BSIM3v1AweffCV * pParam->BSIM3v1Acgsl; + T4 = sqrt(1.0 - 4.0 * T2 / pParam->BSIM3v1Ackappa); + cgso = pParam->BSIM3v1Acgso + T3 - T3 * (1.0 - 1.0 / T4) + * (0.5 - 0.5 * T0 / T1); + qgso = (pParam->BSIM3v1Acgso + T3) * vgs - T3 * (T2 + + 0.5 * pParam->BSIM3v1Ackappa * (T4 - 1.0)); + } + + if (here->BSIM3v1Amode > 0) + { gcdgb = (here->BSIM3v1Acdgb - cgdo) * ag0; + gcddb = (here->BSIM3v1Acddb + here->BSIM3v1Acapbd + cgdo) * ag0; + gcdsb = here->BSIM3v1Acdsb * ag0; + gcsgb = -(here->BSIM3v1Acggb + here->BSIM3v1Acbgb + here->BSIM3v1Acdgb + + cgso) * ag0; + gcsdb = -(here->BSIM3v1Acgdb + here->BSIM3v1Acbdb + here->BSIM3v1Acddb) + * ag0; + gcssb = (here->BSIM3v1Acapbs + cgso - (here->BSIM3v1Acgsb + + here->BSIM3v1Acbsb + here->BSIM3v1Acdsb)) * ag0; + gcggb = (here->BSIM3v1Acggb + cgdo + cgso + pParam->BSIM3v1Acgbo ) * ag0; + gcgdb = (here->BSIM3v1Acgdb - cgdo) * ag0; + gcgsb = (here->BSIM3v1Acgsb - cgso) * ag0; + gcbgb = (here->BSIM3v1Acbgb - pParam->BSIM3v1Acgbo) * ag0; + gcbdb = (here->BSIM3v1Acbdb - here->BSIM3v1Acapbd) * ag0; + gcbsb = (here->BSIM3v1Acbsb - here->BSIM3v1Acapbs) * ag0; + + gcqgb = here->BSIM3v1Acqgb * ag0; + gcqdb = here->BSIM3v1Acqdb * ag0; + gcqsb = here->BSIM3v1Acqsb * ag0; + gcqbb = here->BSIM3v1Acqbb * ag0; + + T0 = here->BSIM3v1Atconst * qdef; + here->BSIM3v1Agtg = T0 * here->BSIM3v1Acqgb; + here->BSIM3v1Agtb = T0 * here->BSIM3v1Acqbb; + here->BSIM3v1Agtd = T0 * here->BSIM3v1Acqdb; + here->BSIM3v1Agts = T0 * here->BSIM3v1Acqsb; + + sxpart = 0.6; + dxpart = 0.4; + + /* compute total terminal charge */ + qgd = qgdo; + qgs = qgso; + qgb = pParam->BSIM3v1Acgbo * vgb; + qgate += qgd + qgs + qgb; + qbulk -= qgb; + qdrn -= qgd; + qsrc = -(qgate + qbulk + qdrn); + } + else + { gcsgb = (here->BSIM3v1Acdgb - cgso) * ag0; + gcsdb = here->BSIM3v1Acdsb * ag0; + gcssb = (here->BSIM3v1Acddb + here->BSIM3v1Acapbs + cgso) * ag0; + + gcdgb = -(here->BSIM3v1Acggb + here->BSIM3v1Acbgb + here->BSIM3v1Acdgb + + cgdo) * ag0; + gcdsb = -(here->BSIM3v1Acgdb + here->BSIM3v1Acbdb + here->BSIM3v1Acddb) + * ag0; + gcddb = (here->BSIM3v1Acapbd + cgdo - (here->BSIM3v1Acgsb + + here->BSIM3v1Acbsb + here->BSIM3v1Acdsb)) * ag0; + gcggb = (here->BSIM3v1Acggb + cgdo + cgso + pParam->BSIM3v1Acgbo ) * ag0; + gcgdb = (here->BSIM3v1Acgsb - cgdo) * ag0; + gcgsb = (here->BSIM3v1Acgdb - cgso) * ag0; + gcbgb = (here->BSIM3v1Acbgb - pParam->BSIM3v1Acgbo) * ag0; + gcbdb = (here->BSIM3v1Acbsb - here->BSIM3v1Acapbd) * ag0; + gcbsb = (here->BSIM3v1Acbdb - here->BSIM3v1Acapbs) * ag0; + + gcqgb = here->BSIM3v1Acqgb * ag0; + gcqdb = here->BSIM3v1Acqsb * ag0; + gcqsb = here->BSIM3v1Acqdb * ag0; + gcqbb = here->BSIM3v1Acqbb * ag0; + + T0 = here->BSIM3v1Atconst * qdef; + here->BSIM3v1Agtg = T0 * here->BSIM3v1Acqgb; + here->BSIM3v1Agtb = T0 * here->BSIM3v1Acqbb; + here->BSIM3v1Agtd = T0 * here->BSIM3v1Acqdb; + here->BSIM3v1Agts = T0 * here->BSIM3v1Acqsb; + + dxpart = 0.6; + sxpart = 0.4; + + /* compute total terminal charge */ + qgd = qgdo; + qgs = qgso; + qgb = pParam->BSIM3v1Acgbo * vgb; + qgate += qgd + qgs + qgb; + qbulk -= qgb; + qsrc = qdrn - qgs; + qdrn = -(qgate + qbulk + qsrc); + } + + here->BSIM3v1Acgdo = cgdo; + here->BSIM3v1Acgso = cgso; + +/* added by Mansun 11/1/93 */ + + + if (here->BSIM3v1AnqsMod) + { *(ckt->CKTstate0 + here->BSIM3v1Aqcdump) = qdef; + + if (ckt->CKTmode & MODEINITTRAN) + *(ckt->CKTstate1 + here->BSIM3v1Aqcdump) = + *(ckt->CKTstate0 + here->BSIM3v1Aqcdump); + + error = NIintegrate(ckt, &gqdef, &cqdef, 1.0, here->BSIM3v1Aqcdump); + if (error) return (error); + } + else + { gqdef = cqdef = 0.0; + } + + if (ByPass) goto line860; + +/* End added by Mansun 11/1/93 */ + + *(ckt->CKTstate0 + here->BSIM3v1Aqg) = qgate; + *(ckt->CKTstate0 + here->BSIM3v1Aqd) = qdrn + - *(ckt->CKTstate0 + here->BSIM3v1Aqbd); + *(ckt->CKTstate0 + here->BSIM3v1Aqb) = qbulk + + *(ckt->CKTstate0 + here->BSIM3v1Aqbd) + + *(ckt->CKTstate0 + here->BSIM3v1Aqbs); + + /* store small signal parameters */ + if (ckt->CKTmode & MODEINITSMSIG) + { goto line1000; + } + if (!ChargeComputationNeeded) + goto line850; + + if (ckt->CKTmode & MODEINITTRAN) + { *(ckt->CKTstate1 + here->BSIM3v1Aqb) = + *(ckt->CKTstate0 + here->BSIM3v1Aqb); + *(ckt->CKTstate1 + here->BSIM3v1Aqg) = + *(ckt->CKTstate0 + here->BSIM3v1Aqg); + *(ckt->CKTstate1 + here->BSIM3v1Aqd) = + *(ckt->CKTstate0 + here->BSIM3v1Aqd); + } + + error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v1Aqb); + if (error) + return(error); + error = NIintegrate(ckt, &geq, &ceq, 0.0, here->BSIM3v1Aqg); + if (error) + return(error); + error = NIintegrate(ckt,&geq, &ceq, 0.0, here->BSIM3v1Aqd); + if (error) + return(error); + + goto line860; + +line850: + /* initialize to zero charge conductance and current */ + ceqqg = ceqqb = ceqqd = 0.0; + + cqcheq = cqdef = 0.0; + + gcdgb = gcddb = gcdsb = 0.0; + gcsgb = gcsdb = gcssb = 0.0; + gcggb = gcgdb = gcgsb = 0.0; + gcbgb = gcbdb = gcbsb = 0.0; + + gcqgb = gcqdb = gcqsb = gcqbb = 0.0; + here->BSIM3v1Agtg = here->BSIM3v1Agtd = here->BSIM3v1Agts = here->BSIM3v1Agtb = 0.0; + gqdef = 0.0; + sxpart = (1.0 - (dxpart = (here->BSIM3v1Amode > 0) ? 0.4 : 0.6)); + if (here->BSIM3v1AnqsMod) + here->BSIM3v1Agtau = 16.0 * pParam->BSIM3v1Au0temp * model->BSIM3v1Avtm + / Leff / Leff; + else + here->BSIM3v1Agtau = 0.0; + + goto line900; + +line860: + /* evaluate equivalent charge current */ + + cqgate = *(ckt->CKTstate0 + here->BSIM3v1Acqg); + cqbulk = *(ckt->CKTstate0 + here->BSIM3v1Acqb); + cqdrn = *(ckt->CKTstate0 + here->BSIM3v1Acqd); + + ceqqg = cqgate - gcggb * vgb + gcgdb * vbd + gcgsb * vbs + + (here->BSIM3v1Agtg * vgb - here->BSIM3v1Agtd * vbd - here->BSIM3v1Agts * vbs); + ceqqb = cqbulk - gcbgb * vgb + gcbdb * vbd + gcbsb * vbs; + ceqqd = cqdrn - gcdgb * vgb + gcddb * vbd + gcdsb * vbs + - dxpart * (here->BSIM3v1Agtg * vgb - here->BSIM3v1Agtd * vbd + - here->BSIM3v1Agts * vbs); + + cqcheq = *(ckt->CKTstate0 + here->BSIM3v1Acqcheq) + - (gcqgb * vgb - gcqdb * vbd - gcqsb * vbs) + + (here->BSIM3v1Agtg * vgb - here->BSIM3v1Agtd * vbd - here->BSIM3v1Agts * vbs); + + if (ckt->CKTmode & MODEINITTRAN) + { *(ckt->CKTstate1 + here->BSIM3v1Acqb) = + *(ckt->CKTstate0 + here->BSIM3v1Acqb); + *(ckt->CKTstate1 + here->BSIM3v1Acqg) = + *(ckt->CKTstate0 + here->BSIM3v1Acqg); + *(ckt->CKTstate1 + here->BSIM3v1Acqd) = + *(ckt->CKTstate0 + here->BSIM3v1Acqd); + *(ckt->CKTstate1 + here->BSIM3v1Acqcheq) = + *(ckt->CKTstate0 + here->BSIM3v1Acqcheq); + *(ckt->CKTstate1 + here->BSIM3v1Acqcdump) = + *(ckt->CKTstate0 + here->BSIM3v1Acqcdump); + } + + /* + * load current vector + */ +line900: + + if (here->BSIM3v1Amode >= 0) + { Gm = here->BSIM3v1Agm; + Gmbs = here->BSIM3v1Agmbs; + FwdSum = Gm + Gmbs; + RevSum = 0.0; + cdreq = model->BSIM3v1Atype * (cdrain - here->BSIM3v1Agds * vds + - Gm * vgs - Gmbs * vbs); + ceqbs = -here->BSIM3v1Acsub; + ceqbd = 0.0; + + gbspsp = -here->BSIM3v1Agbds - here->BSIM3v1Agbgs - here->BSIM3v1Agbbs; + gbbdp = -here->BSIM3v1Agbds; + gbbsp = here->BSIM3v1Agbds + here->BSIM3v1Agbgs + here->BSIM3v1Agbbs; + gbspg = here->BSIM3v1Agbgs; + gbspb = here->BSIM3v1Agbbs; + gbspdp = here->BSIM3v1Agbds; + gbdpdp = 0.0; + gbdpg = 0.0; + gbdpb = 0.0; + gbdpsp = 0.0; + } + else + { Gm = -here->BSIM3v1Agm; + Gmbs = -here->BSIM3v1Agmbs; + FwdSum = 0.0; + RevSum = -(Gm + Gmbs); + cdreq = -model->BSIM3v1Atype * (cdrain + here->BSIM3v1Agds * vds + + Gm * vgd + Gmbs * vbd); + ceqbs = 0.0; + ceqbd = -here->BSIM3v1Acsub; + + gbspsp = 0.0; + gbbdp = here->BSIM3v1Agbds + here->BSIM3v1Agbgs + here->BSIM3v1Agbbs; + gbbsp = -here->BSIM3v1Agbds; + gbspg = 0.0; + gbspb = 0.0; + gbspdp = 0.0; + gbdpdp = -here->BSIM3v1Agbds - here->BSIM3v1Agbgs - here->BSIM3v1Agbbs; + gbdpg = here->BSIM3v1Agbgs; + gbdpb = here->BSIM3v1Agbbs; + gbdpsp = here->BSIM3v1Agbds; + } + + if (model->BSIM3v1Atype > 0) + { ceqbs += (here->BSIM3v1Acbs - (here->BSIM3v1Agbs) * vbs); + ceqbd += (here->BSIM3v1Acbd - (here->BSIM3v1Agbd) * vbd); + + ceqqg = ceqqg; + ceqqb = ceqqb; + ceqqd = ceqqd; + cqcheq = cqcheq; + } + else + { ceqbs = -ceqbs - (here->BSIM3v1Acbs - (here->BSIM3v1Agbs) * vbs); + + + ceqbd = -ceqbd - (here->BSIM3v1Acbd - (here->BSIM3v1Agbd) * vbd); + + ceqqg = -ceqqg; + ceqqb = -ceqqb; + ceqqd = -ceqqd; + cqcheq = -cqcheq; + } + + + (*(ckt->CKTrhs + here->BSIM3v1AgNode) -= m * ceqqg); + (*(ckt->CKTrhs + here->BSIM3v1AbNode) -= m * (ceqbs + ceqbd + ceqqb)); + (*(ckt->CKTrhs + here->BSIM3v1AdNodePrime) += m * (ceqbd - cdreq - ceqqd)); + (*(ckt->CKTrhs + here->BSIM3v1AsNodePrime) += m * (cdreq + ceqbs + ceqqg + + ceqqb + ceqqd)); + + *(ckt->CKTrhs + here->BSIM3v1AqNode) += m * (cqcheq - cqdef); + + /* + * load y matrix + */ + + (*(here->BSIM3v1ADdPtr) += m * here->BSIM3v1AdrainConductance); + (*(here->BSIM3v1AGgPtr) += m * (gcggb - here->BSIM3v1Agtg)); + (*(here->BSIM3v1ASsPtr) += m * here->BSIM3v1AsourceConductance); + (*(here->BSIM3v1ABbPtr) += m * ((here->BSIM3v1Agbd + here->BSIM3v1Agbs + - gcbgb - gcbdb - gcbsb) - here->BSIM3v1Agbbs)); + (*(here->BSIM3v1ADPdpPtr) += m * ((here->BSIM3v1AdrainConductance + + here->BSIM3v1Agds + here->BSIM3v1Agbd + + RevSum + gcddb) + dxpart * here->BSIM3v1Agtd + gbdpdp)); + (*(here->BSIM3v1ASPspPtr) += m * ((here->BSIM3v1AsourceConductance + + here->BSIM3v1Agds + here->BSIM3v1Agbs + + FwdSum + gcssb) + sxpart * here->BSIM3v1Agts + gbspsp)); + (*(here->BSIM3v1ADdpPtr) -= m * here->BSIM3v1AdrainConductance); + (*(here->BSIM3v1AGbPtr) -= m * (gcggb + gcgdb + gcgsb + here->BSIM3v1Agtb)); + (*(here->BSIM3v1AGdpPtr) += m * (gcgdb - here->BSIM3v1Agtd)); + (*(here->BSIM3v1AGspPtr) += m * (gcgsb - here->BSIM3v1Agts)); + (*(here->BSIM3v1ASspPtr) -= m * here->BSIM3v1AsourceConductance); + (*(here->BSIM3v1ABgPtr) += m * (gcbgb - here->BSIM3v1Agbgs)); + (*(here->BSIM3v1ABdpPtr) += m * (gcbdb - here->BSIM3v1Agbd + gbbdp)); + (*(here->BSIM3v1ABspPtr) += m * (gcbsb - here->BSIM3v1Agbs + gbbsp)); + (*(here->BSIM3v1ADPdPtr) -= m * here->BSIM3v1AdrainConductance); + (*(here->BSIM3v1ADPgPtr) += m * ((Gm + gcdgb) + dxpart * here->BSIM3v1Agtg + gbdpg)); + (*(here->BSIM3v1ADPbPtr) -= m * ((here->BSIM3v1Agbd - Gmbs + gcdgb + gcddb + + gcdsb - dxpart * here->BSIM3v1Agtb) - gbdpb)); + (*(here->BSIM3v1ADPspPtr) -= m * ((here->BSIM3v1Agds + FwdSum - gcdsb + - 0.5 * here->BSIM3v1Agts) - gbdpsp)); + (*(here->BSIM3v1ASPgPtr) += m * (gcsgb - Gm + sxpart * here->BSIM3v1Agtg + gbspg)); + (*(here->BSIM3v1ASPsPtr) -= m * here->BSIM3v1AsourceConductance); + (*(here->BSIM3v1ASPbPtr) -= m * ((here->BSIM3v1Agbs + Gmbs + gcsgb + gcsdb + + gcssb - sxpart * here->BSIM3v1Agtg) - gbspb)); + (*(here->BSIM3v1ASPdpPtr) -= m * ((here->BSIM3v1Agds + RevSum - gcsdb + - sxpart * here->BSIM3v1Agtd - here->BSIM3v1Agbd) - gbspdp)); + + *(here->BSIM3v1AQqPtr) += m * (gqdef + here->BSIM3v1Agtau); + + *(here->BSIM3v1ADPqPtr) += m * (dxpart * here->BSIM3v1Agtau); + *(here->BSIM3v1ASPqPtr) += m * (sxpart * here->BSIM3v1Agtau); + *(here->BSIM3v1AGqPtr) -= m * here->BSIM3v1Agtau; + + *(here->BSIM3v1AQgPtr) += m * (-gcqgb + here->BSIM3v1Agtg); + *(here->BSIM3v1AQdpPtr) += m * (-gcqdb + here->BSIM3v1Agtd); + *(here->BSIM3v1AQspPtr) += m * (-gcqsb + here->BSIM3v1Agts); + *(here->BSIM3v1AQbPtr) += m * (-gcqbb + here->BSIM3v1Agtb); + +line1000: ; + + } /* End of Mosfet Instance */ +} /* End of Model Instance */ + +return(OK); +} + + + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1amask.c b/src/spicelib/devices/bsim3v1a/b3v1amask.c new file mode 100644 index 000000000..7409ed069 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1amask.c @@ -0,0 +1,1087 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1amask.c +**********/ + +#include "ngspice.h" +#include "ifsim.h" +#include "cktdefs.h" +#include "devdefs.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + +int +BSIM3v1AmAsk(CKTcircuit *ckt, GENmodel *inst, int which, IFvalue *value) +{ + BSIM3v1Amodel *model = (BSIM3v1Amodel *)inst; + switch(which) + { case BSIM3v1A_MOD_MOBMOD: + value->iValue = model->BSIM3v1AmobMod; + return(OK); + case BSIM3v1A_MOD_BINUNIT: + value->iValue = model->BSIM3v1AbinUnit; + return(OK); + case BSIM3v1A_MOD_CAPMOD: + value->iValue = model->BSIM3v1AcapMod; + return(OK); + case BSIM3v1A_MOD_NQSMOD: + value->iValue = model->BSIM3v1AnqsMod; + return(OK); + case BSIM3v1A_MOD_NOIMOD: + value->iValue = model->BSIM3v1AnoiMod; + return(OK); + case BSIM3v1A_MOD_TOX : + value->rValue = model->BSIM3v1Atox; + return(OK); + case BSIM3v1A_MOD_CDSC : + value->rValue = model->BSIM3v1Acdsc; + return(OK); + case BSIM3v1A_MOD_CDSCB : + value->rValue = model->BSIM3v1Acdscb; + return(OK); + + case BSIM3v1A_MOD_CDSCD : + value->rValue = model->BSIM3v1Acdscd; + return(OK); + + case BSIM3v1A_MOD_CIT : + value->rValue = model->BSIM3v1Acit; + return(OK); + case BSIM3v1A_MOD_NFACTOR : + value->rValue = model->BSIM3v1Anfactor; + return(OK); + case BSIM3v1A_MOD_XJ: + value->rValue = model->BSIM3v1Axj; + return(OK); + case BSIM3v1A_MOD_VSAT: + value->rValue = model->BSIM3v1Avsat; + return(OK); + case BSIM3v1A_MOD_AT: + value->rValue = model->BSIM3v1Aat; + return(OK); + case BSIM3v1A_MOD_A0: + value->rValue = model->BSIM3v1Aa0; + return(OK); + + case BSIM3v1A_MOD_AGS: + value->rValue = model->BSIM3v1Aags; + return(OK); + + case BSIM3v1A_MOD_A1: + value->rValue = model->BSIM3v1Aa1; + return(OK); + case BSIM3v1A_MOD_A2: + value->rValue = model->BSIM3v1Aa2; + return(OK); + case BSIM3v1A_MOD_KETA: + value->rValue = model->BSIM3v1Aketa; + return(OK); + case BSIM3v1A_MOD_NSUB: + value->rValue = model->BSIM3v1Ansub; + return(OK); + case BSIM3v1A_MOD_NPEAK: + value->rValue = model->BSIM3v1Anpeak; + return(OK); + case BSIM3v1A_MOD_NGATE: + value->rValue = model->BSIM3v1Angate; + return(OK); + case BSIM3v1A_MOD_GAMMA1: + value->rValue = model->BSIM3v1Agamma1; + return(OK); + case BSIM3v1A_MOD_GAMMA2: + value->rValue = model->BSIM3v1Agamma2; + return(OK); + case BSIM3v1A_MOD_VBX: + value->rValue = model->BSIM3v1Avbx; + return(OK); + case BSIM3v1A_MOD_VBM: + value->rValue = model->BSIM3v1Avbm; + return(OK); + case BSIM3v1A_MOD_XT: + value->rValue = model->BSIM3v1Axt; + return(OK); + case BSIM3v1A_MOD_K1: + value->rValue = model->BSIM3v1Ak1; + return(OK); + case BSIM3v1A_MOD_KT1: + value->rValue = model->BSIM3v1Akt1; + return(OK); + case BSIM3v1A_MOD_KT1L: + value->rValue = model->BSIM3v1Akt1l; + return(OK); + case BSIM3v1A_MOD_KT2 : + value->rValue = model->BSIM3v1Akt2; + return(OK); + case BSIM3v1A_MOD_K2 : + value->rValue = model->BSIM3v1Ak2; + return(OK); + case BSIM3v1A_MOD_K3: + value->rValue = model->BSIM3v1Ak3; + return(OK); + case BSIM3v1A_MOD_K3B: + value->rValue = model->BSIM3v1Ak3b; + return(OK); + case BSIM3v1A_MOD_W0: + value->rValue = model->BSIM3v1Aw0; + return(OK); + case BSIM3v1A_MOD_NLX: + value->rValue = model->BSIM3v1Anlx; + return(OK); + case BSIM3v1A_MOD_DVT0 : + value->rValue = model->BSIM3v1Advt0; + return(OK); + case BSIM3v1A_MOD_DVT1 : + value->rValue = model->BSIM3v1Advt1; + return(OK); + case BSIM3v1A_MOD_DVT2 : + value->rValue = model->BSIM3v1Advt2; + return(OK); + case BSIM3v1A_MOD_DVT0W : + value->rValue = model->BSIM3v1Advt0w; + return(OK); + case BSIM3v1A_MOD_DVT1W : + value->rValue = model->BSIM3v1Advt1w; + return(OK); + case BSIM3v1A_MOD_DVT2W : + value->rValue = model->BSIM3v1Advt2w; + return(OK); + case BSIM3v1A_MOD_DROUT : + value->rValue = model->BSIM3v1Adrout; + return(OK); + case BSIM3v1A_MOD_DSUB : + value->rValue = model->BSIM3v1Adsub; + return(OK); + case BSIM3v1A_MOD_VTH0: + value->rValue = model->BSIM3v1Avth0; + return(OK); + case BSIM3v1A_MOD_UA: + value->rValue = model->BSIM3v1Aua; + return(OK); + case BSIM3v1A_MOD_UA1: + value->rValue = model->BSIM3v1Aua1; + return(OK); + case BSIM3v1A_MOD_UB: + value->rValue = model->BSIM3v1Aub; + return(OK); + case BSIM3v1A_MOD_UB1: + value->rValue = model->BSIM3v1Aub1; + return(OK); + case BSIM3v1A_MOD_UC: + value->rValue = model->BSIM3v1Auc; + return(OK); + case BSIM3v1A_MOD_UC1: + value->rValue = model->BSIM3v1Auc1; + return(OK); + case BSIM3v1A_MOD_U0: + value->rValue = model->BSIM3v1Au0; + return(OK); + case BSIM3v1A_MOD_UTE: + value->rValue = model->BSIM3v1Aute; + return(OK); + case BSIM3v1A_MOD_VOFF: + value->rValue = model->BSIM3v1Avoff; + return(OK); + case BSIM3v1A_MOD_DELTA: + value->rValue = model->BSIM3v1Adelta; + return(OK); + case BSIM3v1A_MOD_RDSW: + value->rValue = model->BSIM3v1Ardsw; + return(OK); + case BSIM3v1A_MOD_PRWG: + value->rValue = model->BSIM3v1Aprwg; + return(OK); + case BSIM3v1A_MOD_PRWB: + value->rValue = model->BSIM3v1Aprwb; + return(OK); + case BSIM3v1A_MOD_PRT: + value->rValue = model->BSIM3v1Aprt; + return(OK); + case BSIM3v1A_MOD_ETA0: + value->rValue = model->BSIM3v1Aeta0; + return(OK); + case BSIM3v1A_MOD_ETAB: + value->rValue = model->BSIM3v1Aetab; + return(OK); + case BSIM3v1A_MOD_PCLM: + value->rValue = model->BSIM3v1Apclm; + return(OK); + case BSIM3v1A_MOD_PDIBL1: + value->rValue = model->BSIM3v1Apdibl1; + return(OK); + case BSIM3v1A_MOD_PDIBL2: + value->rValue = model->BSIM3v1Apdibl2; + return(OK); + case BSIM3v1A_MOD_PDIBLB: + value->rValue = model->BSIM3v1Apdiblb; + return(OK); + case BSIM3v1A_MOD_PSCBE1: + value->rValue = model->BSIM3v1Apscbe1; + return(OK); + case BSIM3v1A_MOD_PSCBE2: + value->rValue = model->BSIM3v1Apscbe2; + return(OK); + case BSIM3v1A_MOD_PVAG: + value->rValue = model->BSIM3v1Apvag; + return(OK); + case BSIM3v1A_MOD_WR: + value->rValue = model->BSIM3v1Awr; + return(OK); + case BSIM3v1A_MOD_DWG: + value->rValue = model->BSIM3v1Adwg; + return(OK); + case BSIM3v1A_MOD_DWB: + value->rValue = model->BSIM3v1Adwb; + return(OK); + case BSIM3v1A_MOD_B0: + value->rValue = model->BSIM3v1Ab0; + return(OK); + case BSIM3v1A_MOD_B1: + value->rValue = model->BSIM3v1Ab1; + return(OK); + case BSIM3v1A_MOD_ALPHA0: + value->rValue = model->BSIM3v1Aalpha0; + return(OK); + case BSIM3v1A_MOD_BETA0: + value->rValue = model->BSIM3v1Abeta0; + return(OK); + + case BSIM3v1A_MOD_ELM: + value->rValue = model->BSIM3v1Aelm; + return(OK); + case BSIM3v1A_MOD_CGSL: + value->rValue = model->BSIM3v1Acgsl; + return(OK); + case BSIM3v1A_MOD_CGDL: + value->rValue = model->BSIM3v1Acgdl; + return(OK); + case BSIM3v1A_MOD_CKAPPA: + value->rValue = model->BSIM3v1Ackappa; + return(OK); + case BSIM3v1A_MOD_CF: + value->rValue = model->BSIM3v1Acf; + return(OK); + case BSIM3v1A_MOD_CLC: + value->rValue = model->BSIM3v1Aclc; + return(OK); + case BSIM3v1A_MOD_CLE: + value->rValue = model->BSIM3v1Acle; + return(OK); + case BSIM3v1A_MOD_DWC: + value->rValue = model->BSIM3v1Adwc; + return(OK); + case BSIM3v1A_MOD_DLC: + value->rValue = model->BSIM3v1Adlc; + return(OK); + + /* Length dependence */ + case BSIM3v1A_MOD_LCDSC : + value->rValue = model->BSIM3v1Alcdsc; + return(OK); + case BSIM3v1A_MOD_LCDSCB : + value->rValue = model->BSIM3v1Alcdscb; + return(OK); + case BSIM3v1A_MOD_LCDSCD : + value->rValue = model->BSIM3v1Alcdscd; + return(OK); + case BSIM3v1A_MOD_LCIT : + value->rValue = model->BSIM3v1Alcit; + return(OK); + case BSIM3v1A_MOD_LNFACTOR : + value->rValue = model->BSIM3v1Alnfactor; + return(OK); + case BSIM3v1A_MOD_LXJ: + value->rValue = model->BSIM3v1Alxj; + return(OK); + case BSIM3v1A_MOD_LVSAT: + value->rValue = model->BSIM3v1Alvsat; + return(OK); + case BSIM3v1A_MOD_LAT: + value->rValue = model->BSIM3v1Alat; + return(OK); + case BSIM3v1A_MOD_LA0: + value->rValue = model->BSIM3v1Ala0; + return(OK); + case BSIM3v1A_MOD_LAGS: + value->rValue = model->BSIM3v1Alags; + return(OK); + case BSIM3v1A_MOD_LA1: + value->rValue = model->BSIM3v1Ala1; + return(OK); + case BSIM3v1A_MOD_LA2: + value->rValue = model->BSIM3v1Ala2; + return(OK); + case BSIM3v1A_MOD_LKETA: + value->rValue = model->BSIM3v1Alketa; + return(OK); + case BSIM3v1A_MOD_LNSUB: + value->rValue = model->BSIM3v1Alnsub; + return(OK); + case BSIM3v1A_MOD_LNPEAK: + value->rValue = model->BSIM3v1Alnpeak; + return(OK); + case BSIM3v1A_MOD_LNGATE: + value->rValue = model->BSIM3v1Alngate; + return(OK); + case BSIM3v1A_MOD_LGAMMA1: + value->rValue = model->BSIM3v1Algamma1; + return(OK); + case BSIM3v1A_MOD_LGAMMA2: + value->rValue = model->BSIM3v1Algamma2; + return(OK); + case BSIM3v1A_MOD_LVBX: + value->rValue = model->BSIM3v1Alvbx; + return(OK); + case BSIM3v1A_MOD_LVBM: + value->rValue = model->BSIM3v1Alvbm; + return(OK); + case BSIM3v1A_MOD_LXT: + value->rValue = model->BSIM3v1Alxt; + return(OK); + case BSIM3v1A_MOD_LK1: + value->rValue = model->BSIM3v1Alk1; + return(OK); + case BSIM3v1A_MOD_LKT1: + value->rValue = model->BSIM3v1Alkt1; + return(OK); + case BSIM3v1A_MOD_LKT1L: + value->rValue = model->BSIM3v1Alkt1l; + return(OK); + case BSIM3v1A_MOD_LKT2 : + value->rValue = model->BSIM3v1Alkt2; + return(OK); + case BSIM3v1A_MOD_LK2 : + value->rValue = model->BSIM3v1Alk2; + return(OK); + case BSIM3v1A_MOD_LK3: + value->rValue = model->BSIM3v1Alk3; + return(OK); + case BSIM3v1A_MOD_LK3B: + value->rValue = model->BSIM3v1Alk3b; + return(OK); + case BSIM3v1A_MOD_LW0: + value->rValue = model->BSIM3v1Alw0; + return(OK); + case BSIM3v1A_MOD_LNLX: + value->rValue = model->BSIM3v1Alnlx; + return(OK); + case BSIM3v1A_MOD_LDVT0: + value->rValue = model->BSIM3v1Aldvt0; + return(OK); + case BSIM3v1A_MOD_LDVT1 : + value->rValue = model->BSIM3v1Aldvt1; + return(OK); + case BSIM3v1A_MOD_LDVT2 : + value->rValue = model->BSIM3v1Aldvt2; + return(OK); + case BSIM3v1A_MOD_LDVT0W : + value->rValue = model->BSIM3v1Aldvt0w; + return(OK); + case BSIM3v1A_MOD_LDVT1W : + value->rValue = model->BSIM3v1Aldvt1w; + return(OK); + case BSIM3v1A_MOD_LDVT2W : + value->rValue = model->BSIM3v1Aldvt2w; + return(OK); + case BSIM3v1A_MOD_LDROUT : + value->rValue = model->BSIM3v1Aldrout; + return(OK); + case BSIM3v1A_MOD_LDSUB : + value->rValue = model->BSIM3v1Aldsub; + return(OK); + case BSIM3v1A_MOD_LVTH0: + value->rValue = model->BSIM3v1Alvth0; + return(OK); + case BSIM3v1A_MOD_LUA: + value->rValue = model->BSIM3v1Alua; + return(OK); + case BSIM3v1A_MOD_LUA1: + value->rValue = model->BSIM3v1Alua1; + return(OK); + case BSIM3v1A_MOD_LUB: + value->rValue = model->BSIM3v1Alub; + return(OK); + case BSIM3v1A_MOD_LUB1: + value->rValue = model->BSIM3v1Alub1; + return(OK); + case BSIM3v1A_MOD_LUC: + value->rValue = model->BSIM3v1Aluc; + return(OK); + case BSIM3v1A_MOD_LUC1: + value->rValue = model->BSIM3v1Aluc1; + return(OK); + case BSIM3v1A_MOD_LU0: + value->rValue = model->BSIM3v1Alu0; + return(OK); + case BSIM3v1A_MOD_LUTE: + value->rValue = model->BSIM3v1Alute; + return(OK); + case BSIM3v1A_MOD_LVOFF: + value->rValue = model->BSIM3v1Alvoff; + return(OK); + case BSIM3v1A_MOD_LDELTA: + value->rValue = model->BSIM3v1Aldelta; + return(OK); + case BSIM3v1A_MOD_LRDSW: + value->rValue = model->BSIM3v1Alrdsw; + return(OK); + case BSIM3v1A_MOD_LPRWB: + value->rValue = model->BSIM3v1Alprwb; + return(OK); + case BSIM3v1A_MOD_LPRWG: + value->rValue = model->BSIM3v1Alprwg; + return(OK); + case BSIM3v1A_MOD_LPRT: + value->rValue = model->BSIM3v1Alprt; + return(OK); + case BSIM3v1A_MOD_LETA0: + value->rValue = model->BSIM3v1Aleta0; + return(OK); + case BSIM3v1A_MOD_LETAB: + value->rValue = model->BSIM3v1Aletab; + return(OK); + case BSIM3v1A_MOD_LPCLM: + value->rValue = model->BSIM3v1Alpclm; + return(OK); + case BSIM3v1A_MOD_LPDIBL1: + value->rValue = model->BSIM3v1Alpdibl1; + return(OK); + case BSIM3v1A_MOD_LPDIBL2: + value->rValue = model->BSIM3v1Alpdibl2; + return(OK); + case BSIM3v1A_MOD_LPDIBLB: + value->rValue = model->BSIM3v1Alpdiblb; + return(OK); + case BSIM3v1A_MOD_LPSCBE1: + value->rValue = model->BSIM3v1Alpscbe1; + return(OK); + case BSIM3v1A_MOD_LPSCBE2: + value->rValue = model->BSIM3v1Alpscbe2; + return(OK); + case BSIM3v1A_MOD_LPVAG: + value->rValue = model->BSIM3v1Alpvag; + return(OK); + case BSIM3v1A_MOD_LWR: + value->rValue = model->BSIM3v1Alwr; + return(OK); + case BSIM3v1A_MOD_LDWG: + value->rValue = model->BSIM3v1Aldwg; + return(OK); + case BSIM3v1A_MOD_LDWB: + value->rValue = model->BSIM3v1Aldwb; + return(OK); + case BSIM3v1A_MOD_LB0: + value->rValue = model->BSIM3v1Alb0; + return(OK); + case BSIM3v1A_MOD_LB1: + value->rValue = model->BSIM3v1Alb1; + return(OK); + case BSIM3v1A_MOD_LALPHA0: + value->rValue = model->BSIM3v1Alalpha0; + return(OK); + case BSIM3v1A_MOD_LBETA0: + value->rValue = model->BSIM3v1Albeta0; + return(OK); + + case BSIM3v1A_MOD_LELM: + value->rValue = model->BSIM3v1Alelm; + return(OK); + case BSIM3v1A_MOD_LCGSL: + value->rValue = model->BSIM3v1Alcgsl; + return(OK); + case BSIM3v1A_MOD_LCGDL: + value->rValue = model->BSIM3v1Alcgdl; + return(OK); + case BSIM3v1A_MOD_LCKAPPA: + value->rValue = model->BSIM3v1Alckappa; + return(OK); + case BSIM3v1A_MOD_LCF: + value->rValue = model->BSIM3v1Alcf; + return(OK); + case BSIM3v1A_MOD_LCLC: + value->rValue = model->BSIM3v1Alclc; + return(OK); + case BSIM3v1A_MOD_LCLE: + value->rValue = model->BSIM3v1Alcle; + return(OK); + + /* Width dependence */ + case BSIM3v1A_MOD_WCDSC : + value->rValue = model->BSIM3v1Awcdsc; + return(OK); + case BSIM3v1A_MOD_WCDSCB : + value->rValue = model->BSIM3v1Awcdscb; + return(OK); + case BSIM3v1A_MOD_WCDSCD : + value->rValue = model->BSIM3v1Awcdscd; + return(OK); + case BSIM3v1A_MOD_WCIT : + value->rValue = model->BSIM3v1Awcit; + return(OK); + case BSIM3v1A_MOD_WNFACTOR : + value->rValue = model->BSIM3v1Awnfactor; + return(OK); + case BSIM3v1A_MOD_WXJ: + value->rValue = model->BSIM3v1Awxj; + return(OK); + case BSIM3v1A_MOD_WVSAT: + value->rValue = model->BSIM3v1Awvsat; + return(OK); + case BSIM3v1A_MOD_WAT: + value->rValue = model->BSIM3v1Awat; + return(OK); + case BSIM3v1A_MOD_WA0: + value->rValue = model->BSIM3v1Awa0; + return(OK); + case BSIM3v1A_MOD_WAGS: + value->rValue = model->BSIM3v1Awags; + return(OK); + case BSIM3v1A_MOD_WA1: + value->rValue = model->BSIM3v1Awa1; + return(OK); + case BSIM3v1A_MOD_WA2: + value->rValue = model->BSIM3v1Awa2; + return(OK); + case BSIM3v1A_MOD_WKETA: + value->rValue = model->BSIM3v1Awketa; + return(OK); + case BSIM3v1A_MOD_WNSUB: + value->rValue = model->BSIM3v1Awnsub; + return(OK); + case BSIM3v1A_MOD_WNPEAK: + value->rValue = model->BSIM3v1Awnpeak; + return(OK); + case BSIM3v1A_MOD_WNGATE: + value->rValue = model->BSIM3v1Awngate; + return(OK); + case BSIM3v1A_MOD_WGAMMA1: + value->rValue = model->BSIM3v1Awgamma1; + return(OK); + case BSIM3v1A_MOD_WGAMMA2: + value->rValue = model->BSIM3v1Awgamma2; + return(OK); + case BSIM3v1A_MOD_WVBX: + value->rValue = model->BSIM3v1Awvbx; + return(OK); + case BSIM3v1A_MOD_WVBM: + value->rValue = model->BSIM3v1Awvbm; + return(OK); + case BSIM3v1A_MOD_WXT: + value->rValue = model->BSIM3v1Awxt; + return(OK); + case BSIM3v1A_MOD_WK1: + value->rValue = model->BSIM3v1Awk1; + return(OK); + case BSIM3v1A_MOD_WKT1: + value->rValue = model->BSIM3v1Awkt1; + return(OK); + case BSIM3v1A_MOD_WKT1L: + value->rValue = model->BSIM3v1Awkt1l; + return(OK); + case BSIM3v1A_MOD_WKT2 : + value->rValue = model->BSIM3v1Awkt2; + return(OK); + case BSIM3v1A_MOD_WK2 : + value->rValue = model->BSIM3v1Awk2; + return(OK); + case BSIM3v1A_MOD_WK3: + value->rValue = model->BSIM3v1Awk3; + return(OK); + case BSIM3v1A_MOD_WK3B: + value->rValue = model->BSIM3v1Awk3b; + return(OK); + case BSIM3v1A_MOD_WW0: + value->rValue = model->BSIM3v1Aww0; + return(OK); + case BSIM3v1A_MOD_WNLX: + value->rValue = model->BSIM3v1Awnlx; + return(OK); + case BSIM3v1A_MOD_WDVT0: + value->rValue = model->BSIM3v1Awdvt0; + return(OK); + case BSIM3v1A_MOD_WDVT1 : + value->rValue = model->BSIM3v1Awdvt1; + return(OK); + case BSIM3v1A_MOD_WDVT2 : + value->rValue = model->BSIM3v1Awdvt2; + return(OK); + case BSIM3v1A_MOD_WDVT0W : + value->rValue = model->BSIM3v1Awdvt0w; + return(OK); + case BSIM3v1A_MOD_WDVT1W : + value->rValue = model->BSIM3v1Awdvt1w; + return(OK); + case BSIM3v1A_MOD_WDVT2W : + value->rValue = model->BSIM3v1Awdvt2w; + return(OK); + case BSIM3v1A_MOD_WDROUT : + value->rValue = model->BSIM3v1Awdrout; + return(OK); + case BSIM3v1A_MOD_WDSUB : + value->rValue = model->BSIM3v1Awdsub; + return(OK); + case BSIM3v1A_MOD_WVTH0: + value->rValue = model->BSIM3v1Awvth0; + return(OK); + case BSIM3v1A_MOD_WUA: + value->rValue = model->BSIM3v1Awua; + return(OK); + case BSIM3v1A_MOD_WUA1: + value->rValue = model->BSIM3v1Awua1; + return(OK); + case BSIM3v1A_MOD_WUB: + value->rValue = model->BSIM3v1Awub; + return(OK); + case BSIM3v1A_MOD_WUB1: + value->rValue = model->BSIM3v1Awub1; + return(OK); + case BSIM3v1A_MOD_WUC: + value->rValue = model->BSIM3v1Awuc; + return(OK); + case BSIM3v1A_MOD_WUC1: + value->rValue = model->BSIM3v1Awuc1; + return(OK); + case BSIM3v1A_MOD_WU0: + value->rValue = model->BSIM3v1Awu0; + return(OK); + case BSIM3v1A_MOD_WUTE: + value->rValue = model->BSIM3v1Awute; + return(OK); + case BSIM3v1A_MOD_WVOFF: + value->rValue = model->BSIM3v1Awvoff; + return(OK); + case BSIM3v1A_MOD_WDELTA: + value->rValue = model->BSIM3v1Awdelta; + return(OK); + case BSIM3v1A_MOD_WRDSW: + value->rValue = model->BSIM3v1Awrdsw; + return(OK); + case BSIM3v1A_MOD_WPRWB: + value->rValue = model->BSIM3v1Awprwb; + return(OK); + case BSIM3v1A_MOD_WPRWG: + value->rValue = model->BSIM3v1Awprwg; + return(OK); + case BSIM3v1A_MOD_WPRT: + value->rValue = model->BSIM3v1Awprt; + return(OK); + case BSIM3v1A_MOD_WETA0: + value->rValue = model->BSIM3v1Aweta0; + return(OK); + case BSIM3v1A_MOD_WETAB: + value->rValue = model->BSIM3v1Awetab; + return(OK); + case BSIM3v1A_MOD_WPCLM: + value->rValue = model->BSIM3v1Awpclm; + return(OK); + case BSIM3v1A_MOD_WPDIBL1: + value->rValue = model->BSIM3v1Awpdibl1; + return(OK); + case BSIM3v1A_MOD_WPDIBL2: + value->rValue = model->BSIM3v1Awpdibl2; + return(OK); + case BSIM3v1A_MOD_WPDIBLB: + value->rValue = model->BSIM3v1Awpdiblb; + return(OK); + case BSIM3v1A_MOD_WPSCBE1: + value->rValue = model->BSIM3v1Awpscbe1; + return(OK); + case BSIM3v1A_MOD_WPSCBE2: + value->rValue = model->BSIM3v1Awpscbe2; + return(OK); + case BSIM3v1A_MOD_WPVAG: + value->rValue = model->BSIM3v1Awpvag; + return(OK); + case BSIM3v1A_MOD_WWR: + value->rValue = model->BSIM3v1Awwr; + return(OK); + case BSIM3v1A_MOD_WDWG: + value->rValue = model->BSIM3v1Awdwg; + return(OK); + case BSIM3v1A_MOD_WDWB: + value->rValue = model->BSIM3v1Awdwb; + return(OK); + case BSIM3v1A_MOD_WB0: + value->rValue = model->BSIM3v1Awb0; + return(OK); + case BSIM3v1A_MOD_WB1: + value->rValue = model->BSIM3v1Awb1; + return(OK); + case BSIM3v1A_MOD_WALPHA0: + value->rValue = model->BSIM3v1Awalpha0; + return(OK); + case BSIM3v1A_MOD_WBETA0: + value->rValue = model->BSIM3v1Awbeta0; + return(OK); + + case BSIM3v1A_MOD_WELM: + value->rValue = model->BSIM3v1Awelm; + return(OK); + case BSIM3v1A_MOD_WCGSL: + value->rValue = model->BSIM3v1Awcgsl; + return(OK); + case BSIM3v1A_MOD_WCGDL: + value->rValue = model->BSIM3v1Awcgdl; + return(OK); + case BSIM3v1A_MOD_WCKAPPA: + value->rValue = model->BSIM3v1Awckappa; + return(OK); + case BSIM3v1A_MOD_WCF: + value->rValue = model->BSIM3v1Awcf; + return(OK); + case BSIM3v1A_MOD_WCLC: + value->rValue = model->BSIM3v1Awclc; + return(OK); + case BSIM3v1A_MOD_WCLE: + value->rValue = model->BSIM3v1Awcle; + return(OK); + + /* Cross-term dependence */ + case BSIM3v1A_MOD_PCDSC : + value->rValue = model->BSIM3v1Apcdsc; + return(OK); + case BSIM3v1A_MOD_PCDSCB : + value->rValue = model->BSIM3v1Apcdscb; + return(OK); + case BSIM3v1A_MOD_PCDSCD : + value->rValue = model->BSIM3v1Apcdscd; + return(OK); + case BSIM3v1A_MOD_PCIT : + value->rValue = model->BSIM3v1Apcit; + return(OK); + case BSIM3v1A_MOD_PNFACTOR : + value->rValue = model->BSIM3v1Apnfactor; + return(OK); + case BSIM3v1A_MOD_PXJ: + value->rValue = model->BSIM3v1Apxj; + return(OK); + case BSIM3v1A_MOD_PVSAT: + value->rValue = model->BSIM3v1Apvsat; + return(OK); + case BSIM3v1A_MOD_PAT: + value->rValue = model->BSIM3v1Apat; + return(OK); + case BSIM3v1A_MOD_PA0: + value->rValue = model->BSIM3v1Apa0; + return(OK); + case BSIM3v1A_MOD_PAGS: + value->rValue = model->BSIM3v1Apags; + return(OK); + case BSIM3v1A_MOD_PA1: + value->rValue = model->BSIM3v1Apa1; + return(OK); + case BSIM3v1A_MOD_PA2: + value->rValue = model->BSIM3v1Apa2; + return(OK); + case BSIM3v1A_MOD_PKETA: + value->rValue = model->BSIM3v1Apketa; + return(OK); + case BSIM3v1A_MOD_PNSUB: + value->rValue = model->BSIM3v1Apnsub; + return(OK); + case BSIM3v1A_MOD_PNPEAK: + value->rValue = model->BSIM3v1Apnpeak; + return(OK); + case BSIM3v1A_MOD_PNGATE: + value->rValue = model->BSIM3v1Apngate; + return(OK); + case BSIM3v1A_MOD_PGAMMA1: + value->rValue = model->BSIM3v1Apgamma1; + return(OK); + case BSIM3v1A_MOD_PGAMMA2: + value->rValue = model->BSIM3v1Apgamma2; + return(OK); + case BSIM3v1A_MOD_PVBX: + value->rValue = model->BSIM3v1Apvbx; + return(OK); + case BSIM3v1A_MOD_PVBM: + value->rValue = model->BSIM3v1Apvbm; + return(OK); + case BSIM3v1A_MOD_PXT: + value->rValue = model->BSIM3v1Apxt; + return(OK); + case BSIM3v1A_MOD_PK1: + value->rValue = model->BSIM3v1Apk1; + return(OK); + case BSIM3v1A_MOD_PKT1: + value->rValue = model->BSIM3v1Apkt1; + return(OK); + case BSIM3v1A_MOD_PKT1L: + value->rValue = model->BSIM3v1Apkt1l; + return(OK); + case BSIM3v1A_MOD_PKT2 : + value->rValue = model->BSIM3v1Apkt2; + return(OK); + case BSIM3v1A_MOD_PK2 : + value->rValue = model->BSIM3v1Apk2; + return(OK); + case BSIM3v1A_MOD_PK3: + value->rValue = model->BSIM3v1Apk3; + return(OK); + case BSIM3v1A_MOD_PK3B: + value->rValue = model->BSIM3v1Apk3b; + return(OK); + case BSIM3v1A_MOD_PW0: + value->rValue = model->BSIM3v1Apw0; + return(OK); + case BSIM3v1A_MOD_PNLX: + value->rValue = model->BSIM3v1Apnlx; + return(OK); + case BSIM3v1A_MOD_PDVT0 : + value->rValue = model->BSIM3v1Apdvt0; + return(OK); + case BSIM3v1A_MOD_PDVT1 : + value->rValue = model->BSIM3v1Apdvt1; + return(OK); + case BSIM3v1A_MOD_PDVT2 : + value->rValue = model->BSIM3v1Apdvt2; + return(OK); + case BSIM3v1A_MOD_PDVT0W : + value->rValue = model->BSIM3v1Apdvt0w; + return(OK); + case BSIM3v1A_MOD_PDVT1W : + value->rValue = model->BSIM3v1Apdvt1w; + return(OK); + case BSIM3v1A_MOD_PDVT2W : + value->rValue = model->BSIM3v1Apdvt2w; + return(OK); + case BSIM3v1A_MOD_PDROUT : + value->rValue = model->BSIM3v1Apdrout; + return(OK); + case BSIM3v1A_MOD_PDSUB : + value->rValue = model->BSIM3v1Apdsub; + return(OK); + case BSIM3v1A_MOD_PVTH0: + value->rValue = model->BSIM3v1Apvth0; + return(OK); + case BSIM3v1A_MOD_PUA: + value->rValue = model->BSIM3v1Apua; + return(OK); + case BSIM3v1A_MOD_PUA1: + value->rValue = model->BSIM3v1Apua1; + return(OK); + case BSIM3v1A_MOD_PUB: + value->rValue = model->BSIM3v1Apub; + return(OK); + case BSIM3v1A_MOD_PUB1: + value->rValue = model->BSIM3v1Apub1; + return(OK); + case BSIM3v1A_MOD_PUC: + value->rValue = model->BSIM3v1Apuc; + return(OK); + case BSIM3v1A_MOD_PUC1: + value->rValue = model->BSIM3v1Apuc1; + return(OK); + case BSIM3v1A_MOD_PU0: + value->rValue = model->BSIM3v1Apu0; + return(OK); + case BSIM3v1A_MOD_PUTE: + value->rValue = model->BSIM3v1Apute; + return(OK); + case BSIM3v1A_MOD_PVOFF: + value->rValue = model->BSIM3v1Apvoff; + return(OK); + case BSIM3v1A_MOD_PDELTA: + value->rValue = model->BSIM3v1Apdelta; + return(OK); + case BSIM3v1A_MOD_PRDSW: + value->rValue = model->BSIM3v1Aprdsw; + return(OK); + case BSIM3v1A_MOD_PPRWB: + value->rValue = model->BSIM3v1Apprwb; + return(OK); + case BSIM3v1A_MOD_PPRWG: + value->rValue = model->BSIM3v1Apprwg; + return(OK); + case BSIM3v1A_MOD_PPRT: + value->rValue = model->BSIM3v1Apprt; + return(OK); + case BSIM3v1A_MOD_PETA0: + value->rValue = model->BSIM3v1Apeta0; + return(OK); + case BSIM3v1A_MOD_PETAB: + value->rValue = model->BSIM3v1Apetab; + return(OK); + case BSIM3v1A_MOD_PPCLM: + value->rValue = model->BSIM3v1Appclm; + return(OK); + case BSIM3v1A_MOD_PPDIBL1: + value->rValue = model->BSIM3v1Appdibl1; + return(OK); + case BSIM3v1A_MOD_PPDIBL2: + value->rValue = model->BSIM3v1Appdibl2; + return(OK); + case BSIM3v1A_MOD_PPDIBLB: + value->rValue = model->BSIM3v1Appdiblb; + return(OK); + case BSIM3v1A_MOD_PPSCBE1: + value->rValue = model->BSIM3v1Appscbe1; + return(OK); + case BSIM3v1A_MOD_PPSCBE2: + value->rValue = model->BSIM3v1Appscbe2; + return(OK); + case BSIM3v1A_MOD_PPVAG: + value->rValue = model->BSIM3v1Appvag; + return(OK); + case BSIM3v1A_MOD_PWR: + value->rValue = model->BSIM3v1Apwr; + return(OK); + case BSIM3v1A_MOD_PDWG: + value->rValue = model->BSIM3v1Apdwg; + return(OK); + case BSIM3v1A_MOD_PDWB: + value->rValue = model->BSIM3v1Apdwb; + return(OK); + case BSIM3v1A_MOD_PB0: + value->rValue = model->BSIM3v1Apb0; + return(OK); + case BSIM3v1A_MOD_PB1: + value->rValue = model->BSIM3v1Apb1; + return(OK); + case BSIM3v1A_MOD_PALPHA0: + value->rValue = model->BSIM3v1Apalpha0; + return(OK); + case BSIM3v1A_MOD_PBETA0: + value->rValue = model->BSIM3v1Apbeta0; + return(OK); + + case BSIM3v1A_MOD_PELM: + value->rValue = model->BSIM3v1Apelm; + return(OK); + case BSIM3v1A_MOD_PCGSL: + value->rValue = model->BSIM3v1Apcgsl; + return(OK); + case BSIM3v1A_MOD_PCGDL: + value->rValue = model->BSIM3v1Apcgdl; + return(OK); + case BSIM3v1A_MOD_PCKAPPA: + value->rValue = model->BSIM3v1Apckappa; + return(OK); + case BSIM3v1A_MOD_PCF: + value->rValue = model->BSIM3v1Apcf; + return(OK); + case BSIM3v1A_MOD_PCLC: + value->rValue = model->BSIM3v1Apclc; + return(OK); + case BSIM3v1A_MOD_PCLE: + value->rValue = model->BSIM3v1Apcle; + return(OK); + + case BSIM3v1A_MOD_TNOM : + value->rValue = model->BSIM3v1Atnom; + return(OK); + case BSIM3v1A_MOD_CGSO: + value->rValue = model->BSIM3v1Acgso; + return(OK); + case BSIM3v1A_MOD_CGDO: + value->rValue = model->BSIM3v1Acgdo; + return(OK); + case BSIM3v1A_MOD_CGBO: + value->rValue = model->BSIM3v1Acgbo; + return(OK); + case BSIM3v1A_MOD_XPART: + value->rValue = model->BSIM3v1Axpart; + return(OK); + case BSIM3v1A_MOD_RSH: + value->rValue = model->BSIM3v1AsheetResistance; + return(OK); + case BSIM3v1A_MOD_JS: + value->rValue = model->BSIM3v1AjctSatCurDensity; + return(OK); + case BSIM3v1A_MOD_PB: + value->rValue = model->BSIM3v1AbulkJctPotential; + return(OK); + case BSIM3v1A_MOD_MJ: + value->rValue = model->BSIM3v1AbulkJctBotGradingCoeff; + return(OK); + case BSIM3v1A_MOD_PBSW: + value->rValue = model->BSIM3v1AsidewallJctPotential; + return(OK); + case BSIM3v1A_MOD_MJSW: + value->rValue = model->BSIM3v1AbulkJctSideGradingCoeff; + return(OK); + case BSIM3v1A_MOD_CJ: + value->rValue = model->BSIM3v1AunitAreaJctCap; + return(OK); + case BSIM3v1A_MOD_CJSW: + value->rValue = model->BSIM3v1AunitLengthSidewallJctCap; + return(OK); + case BSIM3v1A_MOD_LINT: + value->rValue = model->BSIM3v1ALint; + return(OK); + case BSIM3v1A_MOD_LL: + value->rValue = model->BSIM3v1ALl; + return(OK); + case BSIM3v1A_MOD_LLN: + value->rValue = model->BSIM3v1ALln; + return(OK); + case BSIM3v1A_MOD_LW: + value->rValue = model->BSIM3v1ALw; + return(OK); + case BSIM3v1A_MOD_LWN: + value->rValue = model->BSIM3v1ALwn; + return(OK); + case BSIM3v1A_MOD_LWL: + value->rValue = model->BSIM3v1ALwl; + return(OK); + case BSIM3v1A_MOD_LMIN: + value->rValue = model->BSIM3v1ALmin; + return(OK); + case BSIM3v1A_MOD_LMAX: + value->rValue = model->BSIM3v1ALmax; + return(OK); + case BSIM3v1A_MOD_WINT: + value->rValue = model->BSIM3v1AWint; + return(OK); + case BSIM3v1A_MOD_WL: + value->rValue = model->BSIM3v1AWl; + return(OK); + case BSIM3v1A_MOD_WLN: + value->rValue = model->BSIM3v1AWln; + return(OK); + case BSIM3v1A_MOD_WW: + value->rValue = model->BSIM3v1AWw; + return(OK); + case BSIM3v1A_MOD_WWN: + value->rValue = model->BSIM3v1AWwn; + return(OK); + case BSIM3v1A_MOD_WWL: + value->rValue = model->BSIM3v1AWwl; + return(OK); + case BSIM3v1A_MOD_WMIN: + value->rValue = model->BSIM3v1AWmin; + return(OK); + case BSIM3v1A_MOD_WMAX: + value->rValue = model->BSIM3v1AWmax; + return(OK); + case BSIM3v1A_MOD_NOIA: + value->rValue = model->BSIM3v1AoxideTrapDensityA; + return(OK); + case BSIM3v1A_MOD_NOIB: + value->rValue = model->BSIM3v1AoxideTrapDensityB; + return(OK); + case BSIM3v1A_MOD_NOIC: + value->rValue = model->BSIM3v1AoxideTrapDensityC; + return(OK); + case BSIM3v1A_MOD_EM: + value->rValue = model->BSIM3v1Aem; + return(OK); + case BSIM3v1A_MOD_EF: + value->rValue = model->BSIM3v1Aef; + return(OK); + case BSIM3v1A_MOD_AF: + value->rValue = model->BSIM3v1Aaf; + return(OK); + case BSIM3v1A_MOD_KF: + value->rValue = model->BSIM3v1Akf; + return(OK); + default: + return(E_BADPARM); + } + /* NOTREACHED */ +} + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1amdel.c b/src/spicelib/devices/bsim3v1a/b3v1amdel.c new file mode 100644 index 000000000..86930caf7 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1amdel.c @@ -0,0 +1,43 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1amdel.c +**********/ + +#include "ngspice.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + +int +BSIM3v1AmDelete(GENmodel **inModel, IFuid modname, GENmodel *kill) +{ +BSIM3v1Amodel **model = (BSIM3v1Amodel**)inModel; +BSIM3v1Amodel *modfast = (BSIM3v1Amodel*)kill; +BSIM3v1Ainstance *here; +BSIM3v1Ainstance *prev = NULL; +BSIM3v1Amodel **oldmod; + + oldmod = model; + for (; *model ; model = &((*model)->BSIM3v1AnextModel)) + { if ((*model)->BSIM3v1AmodName == modname || + (modfast && *model == modfast)) + goto delgot; + oldmod = model; + } + return(E_NOMOD); + +delgot: + *oldmod = (*model)->BSIM3v1AnextModel; /* cut deleted device out of list */ + for (here = (*model)->BSIM3v1Ainstances; here; here = here->BSIM3v1AnextInstance) + { if(prev) FREE(prev); + prev = here; + } + if(prev) FREE(prev); + FREE(*model); + return(OK); +} + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1ampar.c b/src/spicelib/devices/bsim3v1a/b3v1ampar.c new file mode 100644 index 000000000..e79e08a1f --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1ampar.c @@ -0,0 +1,1483 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1ampar.c +**********/ + +#include "ngspice.h" +#include "bsim3v1adef.h" +#include "ifsim.h" +#include "sperror.h" +#include "suffix.h" + + +int +BSIM3v1AmParam(int param, IFvalue *value, GENmodel *inMod) +{ + BSIM3v1Amodel *mod = (BSIM3v1Amodel*)inMod; + switch(param) + { case BSIM3v1A_MOD_MOBMOD : + mod->BSIM3v1AmobMod = value->iValue; + mod->BSIM3v1AmobModGiven = TRUE; + break; + case BSIM3v1A_MOD_BINUNIT : + mod->BSIM3v1AbinUnit = value->iValue; + mod->BSIM3v1AbinUnitGiven = TRUE; + break; + case BSIM3v1A_MOD_CAPMOD : + mod->BSIM3v1AcapMod = value->iValue; + mod->BSIM3v1AcapModGiven = TRUE; + break; + case BSIM3v1A_MOD_NQSMOD : + mod->BSIM3v1AnqsMod = value->iValue; + mod->BSIM3v1AnqsModGiven = TRUE; + break; + case BSIM3v1A_MOD_NOIMOD : + mod->BSIM3v1AnoiMod = value->iValue; + mod->BSIM3v1AnoiModGiven = TRUE; + break; + case BSIM3v1A_MOD_TOX : + mod->BSIM3v1Atox = value->rValue; + mod->BSIM3v1AtoxGiven = TRUE; + break; + + case BSIM3v1A_MOD_CDSC : + mod->BSIM3v1Acdsc = value->rValue; + mod->BSIM3v1AcdscGiven = TRUE; + break; + case BSIM3v1A_MOD_CDSCB : + mod->BSIM3v1Acdscb = value->rValue; + mod->BSIM3v1AcdscbGiven = TRUE; + break; + + case BSIM3v1A_MOD_CDSCD : + mod->BSIM3v1Acdscd = value->rValue; + mod->BSIM3v1AcdscdGiven = TRUE; + break; + + case BSIM3v1A_MOD_CIT : + mod->BSIM3v1Acit = value->rValue; + mod->BSIM3v1AcitGiven = TRUE; + break; + case BSIM3v1A_MOD_NFACTOR : + mod->BSIM3v1Anfactor = value->rValue; + mod->BSIM3v1AnfactorGiven = TRUE; + break; + case BSIM3v1A_MOD_XJ: + mod->BSIM3v1Axj = value->rValue; + mod->BSIM3v1AxjGiven = TRUE; + break; + case BSIM3v1A_MOD_VSAT: + mod->BSIM3v1Avsat = value->rValue; + mod->BSIM3v1AvsatGiven = TRUE; + break; + case BSIM3v1A_MOD_A0: + mod->BSIM3v1Aa0 = value->rValue; + mod->BSIM3v1Aa0Given = TRUE; + break; + + case BSIM3v1A_MOD_AGS: + mod->BSIM3v1Aags= value->rValue; + mod->BSIM3v1AagsGiven = TRUE; + break; + + case BSIM3v1A_MOD_A1: + mod->BSIM3v1Aa1 = value->rValue; + mod->BSIM3v1Aa1Given = TRUE; + break; + case BSIM3v1A_MOD_A2: + mod->BSIM3v1Aa2 = value->rValue; + mod->BSIM3v1Aa2Given = TRUE; + break; + case BSIM3v1A_MOD_AT: + mod->BSIM3v1Aat = value->rValue; + mod->BSIM3v1AatGiven = TRUE; + break; + case BSIM3v1A_MOD_KETA: + mod->BSIM3v1Aketa = value->rValue; + mod->BSIM3v1AketaGiven = TRUE; + break; + case BSIM3v1A_MOD_NSUB: + mod->BSIM3v1Ansub = value->rValue; + mod->BSIM3v1AnsubGiven = TRUE; + break; + case BSIM3v1A_MOD_NPEAK: + mod->BSIM3v1Anpeak = value->rValue; + mod->BSIM3v1AnpeakGiven = TRUE; + if (mod->BSIM3v1Anpeak > 1.0e20) + mod->BSIM3v1Anpeak *= 1.0e-6; + break; + case BSIM3v1A_MOD_NGATE: + mod->BSIM3v1Angate = value->rValue; + mod->BSIM3v1AngateGiven = TRUE; + if (mod->BSIM3v1Angate > 1.0e23) + mod->BSIM3v1Angate *= 1.0e-6; + break; + case BSIM3v1A_MOD_GAMMA1: + mod->BSIM3v1Agamma1 = value->rValue; + mod->BSIM3v1Agamma1Given = TRUE; + break; + case BSIM3v1A_MOD_GAMMA2: + mod->BSIM3v1Agamma2 = value->rValue; + mod->BSIM3v1Agamma2Given = TRUE; + break; + case BSIM3v1A_MOD_VBX: + mod->BSIM3v1Avbx = value->rValue; + mod->BSIM3v1AvbxGiven = TRUE; + break; + case BSIM3v1A_MOD_VBM: + mod->BSIM3v1Avbm = value->rValue; + mod->BSIM3v1AvbmGiven = TRUE; + break; + case BSIM3v1A_MOD_XT: + mod->BSIM3v1Axt = value->rValue; + mod->BSIM3v1AxtGiven = TRUE; + break; + case BSIM3v1A_MOD_K1: + mod->BSIM3v1Ak1 = value->rValue; + mod->BSIM3v1Ak1Given = TRUE; + break; + case BSIM3v1A_MOD_KT1: + mod->BSIM3v1Akt1 = value->rValue; + mod->BSIM3v1Akt1Given = TRUE; + break; + case BSIM3v1A_MOD_KT1L: + mod->BSIM3v1Akt1l = value->rValue; + mod->BSIM3v1Akt1lGiven = TRUE; + break; + case BSIM3v1A_MOD_KT2: + mod->BSIM3v1Akt2 = value->rValue; + mod->BSIM3v1Akt2Given = TRUE; + break; + case BSIM3v1A_MOD_K2: + mod->BSIM3v1Ak2 = value->rValue; + mod->BSIM3v1Ak2Given = TRUE; + break; + case BSIM3v1A_MOD_K3: + mod->BSIM3v1Ak3 = value->rValue; + mod->BSIM3v1Ak3Given = TRUE; + break; + case BSIM3v1A_MOD_K3B: + mod->BSIM3v1Ak3b = value->rValue; + mod->BSIM3v1Ak3bGiven = TRUE; + break; + case BSIM3v1A_MOD_NLX: + mod->BSIM3v1Anlx = value->rValue; + mod->BSIM3v1AnlxGiven = TRUE; + break; + case BSIM3v1A_MOD_W0: + mod->BSIM3v1Aw0 = value->rValue; + mod->BSIM3v1Aw0Given = TRUE; + break; + case BSIM3v1A_MOD_DVT0: + mod->BSIM3v1Advt0 = value->rValue; + mod->BSIM3v1Advt0Given = TRUE; + break; + case BSIM3v1A_MOD_DVT1: + mod->BSIM3v1Advt1 = value->rValue; + mod->BSIM3v1Advt1Given = TRUE; + break; + case BSIM3v1A_MOD_DVT2: + mod->BSIM3v1Advt2 = value->rValue; + mod->BSIM3v1Advt2Given = TRUE; + break; + case BSIM3v1A_MOD_DVT0W: + mod->BSIM3v1Advt0w = value->rValue; + mod->BSIM3v1Advt0wGiven = TRUE; + break; + case BSIM3v1A_MOD_DVT1W: + mod->BSIM3v1Advt1w = value->rValue; + mod->BSIM3v1Advt1wGiven = TRUE; + break; + case BSIM3v1A_MOD_DVT2W: + mod->BSIM3v1Advt2w = value->rValue; + mod->BSIM3v1Advt2wGiven = TRUE; + break; + case BSIM3v1A_MOD_DROUT: + mod->BSIM3v1Adrout = value->rValue; + mod->BSIM3v1AdroutGiven = TRUE; + break; + case BSIM3v1A_MOD_DSUB: + mod->BSIM3v1Adsub = value->rValue; + mod->BSIM3v1AdsubGiven = TRUE; + break; + case BSIM3v1A_MOD_VTH0: + mod->BSIM3v1Avth0 = value->rValue; + mod->BSIM3v1Avth0Given = TRUE; + break; + case BSIM3v1A_MOD_UA: + mod->BSIM3v1Aua = value->rValue; + mod->BSIM3v1AuaGiven = TRUE; + break; + case BSIM3v1A_MOD_UA1: + mod->BSIM3v1Aua1 = value->rValue; + mod->BSIM3v1Aua1Given = TRUE; + break; + case BSIM3v1A_MOD_UB: + mod->BSIM3v1Aub = value->rValue; + mod->BSIM3v1AubGiven = TRUE; + break; + case BSIM3v1A_MOD_UB1: + mod->BSIM3v1Aub1 = value->rValue; + mod->BSIM3v1Aub1Given = TRUE; + break; + case BSIM3v1A_MOD_UC: + mod->BSIM3v1Auc = value->rValue; + mod->BSIM3v1AucGiven = TRUE; + break; + case BSIM3v1A_MOD_UC1: + mod->BSIM3v1Auc1 = value->rValue; + mod->BSIM3v1Auc1Given = TRUE; + break; + case BSIM3v1A_MOD_U0 : + mod->BSIM3v1Au0 = value->rValue; + mod->BSIM3v1Au0Given = TRUE; + if (mod->BSIM3v1Au0 > 1.0) + mod->BSIM3v1Au0 *= 1.0e-4; + break; + case BSIM3v1A_MOD_UTE : + mod->BSIM3v1Aute = value->rValue; + mod->BSIM3v1AuteGiven = TRUE; + break; + case BSIM3v1A_MOD_VOFF: + mod->BSIM3v1Avoff = value->rValue; + mod->BSIM3v1AvoffGiven = TRUE; + break; + case BSIM3v1A_MOD_DELTA : + mod->BSIM3v1Adelta = value->rValue; + mod->BSIM3v1AdeltaGiven = TRUE; + break; + case BSIM3v1A_MOD_RDSW: + mod->BSIM3v1Ardsw = value->rValue; + mod->BSIM3v1ArdswGiven = TRUE; + break; + case BSIM3v1A_MOD_PRWG: + mod->BSIM3v1Aprwg = value->rValue; + mod->BSIM3v1AprwgGiven = TRUE; + break; + case BSIM3v1A_MOD_PRWB: + mod->BSIM3v1Aprwb = value->rValue; + mod->BSIM3v1AprwbGiven = TRUE; + break; + case BSIM3v1A_MOD_PRT: + mod->BSIM3v1Aprt = value->rValue; + mod->BSIM3v1AprtGiven = TRUE; + break; + case BSIM3v1A_MOD_ETA0: + mod->BSIM3v1Aeta0 = value->rValue; + mod->BSIM3v1Aeta0Given = TRUE; + break; + case BSIM3v1A_MOD_ETAB: + mod->BSIM3v1Aetab = value->rValue; + mod->BSIM3v1AetabGiven = TRUE; + break; + case BSIM3v1A_MOD_PCLM: + mod->BSIM3v1Apclm = value->rValue; + mod->BSIM3v1ApclmGiven = TRUE; + break; + case BSIM3v1A_MOD_PDIBL1: + mod->BSIM3v1Apdibl1 = value->rValue; + mod->BSIM3v1Apdibl1Given = TRUE; + break; + case BSIM3v1A_MOD_PDIBL2: + mod->BSIM3v1Apdibl2 = value->rValue; + mod->BSIM3v1Apdibl2Given = TRUE; + break; + case BSIM3v1A_MOD_PDIBLB: + mod->BSIM3v1Apdiblb = value->rValue; + mod->BSIM3v1ApdiblbGiven = TRUE; + break; + case BSIM3v1A_MOD_PSCBE1: + mod->BSIM3v1Apscbe1 = value->rValue; + mod->BSIM3v1Apscbe1Given = TRUE; + break; + case BSIM3v1A_MOD_PSCBE2: + mod->BSIM3v1Apscbe2 = value->rValue; + mod->BSIM3v1Apscbe2Given = TRUE; + break; + case BSIM3v1A_MOD_PVAG: + mod->BSIM3v1Apvag = value->rValue; + mod->BSIM3v1ApvagGiven = TRUE; + break; + case BSIM3v1A_MOD_WR : + mod->BSIM3v1Awr = value->rValue; + mod->BSIM3v1AwrGiven = TRUE; + break; + case BSIM3v1A_MOD_DWG : + mod->BSIM3v1Adwg = value->rValue; + mod->BSIM3v1AdwgGiven = TRUE; + break; + case BSIM3v1A_MOD_DWB : + mod->BSIM3v1Adwb = value->rValue; + mod->BSIM3v1AdwbGiven = TRUE; + break; + case BSIM3v1A_MOD_B0 : + mod->BSIM3v1Ab0 = value->rValue; + mod->BSIM3v1Ab0Given = TRUE; + break; + case BSIM3v1A_MOD_B1 : + mod->BSIM3v1Ab1 = value->rValue; + mod->BSIM3v1Ab1Given = TRUE; + break; + case BSIM3v1A_MOD_ALPHA0 : + mod->BSIM3v1Aalpha0 = value->rValue; + mod->BSIM3v1Aalpha0Given = TRUE; + break; + case BSIM3v1A_MOD_BETA0 : + mod->BSIM3v1Abeta0 = value->rValue; + mod->BSIM3v1Abeta0Given = TRUE; + break; + + case BSIM3v1A_MOD_ELM : + mod->BSIM3v1Aelm = value->rValue; + mod->BSIM3v1AelmGiven = TRUE; + break; + case BSIM3v1A_MOD_CGSL : + mod->BSIM3v1Acgsl = value->rValue; + mod->BSIM3v1AcgslGiven = TRUE; + break; + case BSIM3v1A_MOD_CGDL : + mod->BSIM3v1Acgdl = value->rValue; + mod->BSIM3v1AcgdlGiven = TRUE; + break; + case BSIM3v1A_MOD_CKAPPA : + mod->BSIM3v1Ackappa = value->rValue; + mod->BSIM3v1AckappaGiven = TRUE; + break; + case BSIM3v1A_MOD_CF : + mod->BSIM3v1Acf = value->rValue; + mod->BSIM3v1AcfGiven = TRUE; + break; + case BSIM3v1A_MOD_CLC : + mod->BSIM3v1Aclc = value->rValue; + mod->BSIM3v1AclcGiven = TRUE; + break; + case BSIM3v1A_MOD_CLE : + mod->BSIM3v1Acle = value->rValue; + mod->BSIM3v1AcleGiven = TRUE; + break; + case BSIM3v1A_MOD_DWC : + mod->BSIM3v1Adwc = value->rValue; + mod->BSIM3v1AdwcGiven = TRUE; + break; + case BSIM3v1A_MOD_DLC : + mod->BSIM3v1Adlc = value->rValue; + mod->BSIM3v1AdlcGiven = TRUE; + break; + + /* Length dependence */ + case BSIM3v1A_MOD_LCDSC : + mod->BSIM3v1Alcdsc = value->rValue; + mod->BSIM3v1AlcdscGiven = TRUE; + break; + + + case BSIM3v1A_MOD_LCDSCB : + mod->BSIM3v1Alcdscb = value->rValue; + mod->BSIM3v1AlcdscbGiven = TRUE; + break; + case BSIM3v1A_MOD_LCDSCD : + mod->BSIM3v1Alcdscd = value->rValue; + mod->BSIM3v1AlcdscdGiven = TRUE; + break; + case BSIM3v1A_MOD_LCIT : + mod->BSIM3v1Alcit = value->rValue; + mod->BSIM3v1AlcitGiven = TRUE; + break; + case BSIM3v1A_MOD_LNFACTOR : + mod->BSIM3v1Alnfactor = value->rValue; + mod->BSIM3v1AlnfactorGiven = TRUE; + break; + case BSIM3v1A_MOD_LXJ: + mod->BSIM3v1Alxj = value->rValue; + mod->BSIM3v1AlxjGiven = TRUE; + break; + case BSIM3v1A_MOD_LVSAT: + mod->BSIM3v1Alvsat = value->rValue; + mod->BSIM3v1AlvsatGiven = TRUE; + break; + + + case BSIM3v1A_MOD_LA0: + mod->BSIM3v1Ala0 = value->rValue; + mod->BSIM3v1Ala0Given = TRUE; + break; + case BSIM3v1A_MOD_LAGS: + mod->BSIM3v1Alags = value->rValue; + mod->BSIM3v1AlagsGiven = TRUE; + break; + case BSIM3v1A_MOD_LA1: + mod->BSIM3v1Ala1 = value->rValue; + mod->BSIM3v1Ala1Given = TRUE; + break; + case BSIM3v1A_MOD_LA2: + mod->BSIM3v1Ala2 = value->rValue; + mod->BSIM3v1Ala2Given = TRUE; + break; + case BSIM3v1A_MOD_LAT: + mod->BSIM3v1Alat = value->rValue; + mod->BSIM3v1AlatGiven = TRUE; + break; + case BSIM3v1A_MOD_LKETA: + mod->BSIM3v1Alketa = value->rValue; + mod->BSIM3v1AlketaGiven = TRUE; + break; + case BSIM3v1A_MOD_LNSUB: + mod->BSIM3v1Alnsub = value->rValue; + mod->BSIM3v1AlnsubGiven = TRUE; + break; + case BSIM3v1A_MOD_LNPEAK: + mod->BSIM3v1Alnpeak = value->rValue; + mod->BSIM3v1AlnpeakGiven = TRUE; + if (mod->BSIM3v1Alnpeak > 1.0e20) + mod->BSIM3v1Alnpeak *= 1.0e-6; + break; + case BSIM3v1A_MOD_LNGATE: + mod->BSIM3v1Alngate = value->rValue; + mod->BSIM3v1AlngateGiven = TRUE; + if (mod->BSIM3v1Alngate > 1.0e23) + mod->BSIM3v1Alngate *= 1.0e-6; + break; + case BSIM3v1A_MOD_LGAMMA1: + mod->BSIM3v1Algamma1 = value->rValue; + mod->BSIM3v1Algamma1Given = TRUE; + break; + case BSIM3v1A_MOD_LGAMMA2: + mod->BSIM3v1Algamma2 = value->rValue; + mod->BSIM3v1Algamma2Given = TRUE; + break; + case BSIM3v1A_MOD_LVBX: + mod->BSIM3v1Alvbx = value->rValue; + mod->BSIM3v1AlvbxGiven = TRUE; + break; + case BSIM3v1A_MOD_LVBM: + mod->BSIM3v1Alvbm = value->rValue; + mod->BSIM3v1AlvbmGiven = TRUE; + break; + case BSIM3v1A_MOD_LXT: + mod->BSIM3v1Alxt = value->rValue; + mod->BSIM3v1AlxtGiven = TRUE; + break; + case BSIM3v1A_MOD_LK1: + mod->BSIM3v1Alk1 = value->rValue; + mod->BSIM3v1Alk1Given = TRUE; + break; + case BSIM3v1A_MOD_LKT1: + mod->BSIM3v1Alkt1 = value->rValue; + mod->BSIM3v1Alkt1Given = TRUE; + break; + case BSIM3v1A_MOD_LKT1L: + mod->BSIM3v1Alkt1l = value->rValue; + mod->BSIM3v1Alkt1lGiven = TRUE; + break; + case BSIM3v1A_MOD_LKT2: + mod->BSIM3v1Alkt2 = value->rValue; + mod->BSIM3v1Alkt2Given = TRUE; + break; + case BSIM3v1A_MOD_LK2: + mod->BSIM3v1Alk2 = value->rValue; + mod->BSIM3v1Alk2Given = TRUE; + break; + case BSIM3v1A_MOD_LK3: + mod->BSIM3v1Alk3 = value->rValue; + mod->BSIM3v1Alk3Given = TRUE; + break; + case BSIM3v1A_MOD_LK3B: + mod->BSIM3v1Alk3b = value->rValue; + mod->BSIM3v1Alk3bGiven = TRUE; + break; + case BSIM3v1A_MOD_LNLX: + mod->BSIM3v1Alnlx = value->rValue; + mod->BSIM3v1AlnlxGiven = TRUE; + break; + case BSIM3v1A_MOD_LW0: + mod->BSIM3v1Alw0 = value->rValue; + mod->BSIM3v1Alw0Given = TRUE; + break; + case BSIM3v1A_MOD_LDVT0: + mod->BSIM3v1Aldvt0 = value->rValue; + mod->BSIM3v1Aldvt0Given = TRUE; + break; + case BSIM3v1A_MOD_LDVT1: + mod->BSIM3v1Aldvt1 = value->rValue; + mod->BSIM3v1Aldvt1Given = TRUE; + break; + case BSIM3v1A_MOD_LDVT2: + mod->BSIM3v1Aldvt2 = value->rValue; + mod->BSIM3v1Aldvt2Given = TRUE; + break; + case BSIM3v1A_MOD_LDVT0W: + mod->BSIM3v1Aldvt0w = value->rValue; + mod->BSIM3v1Aldvt0Given = TRUE; + break; + case BSIM3v1A_MOD_LDVT1W: + mod->BSIM3v1Aldvt1 = value->rValue; + mod->BSIM3v1Aldvt1wGiven = TRUE; + break; + case BSIM3v1A_MOD_LDVT2W: + mod->BSIM3v1Aldvt2 = value->rValue; + mod->BSIM3v1Aldvt2wGiven = TRUE; + break; + case BSIM3v1A_MOD_LDROUT: + mod->BSIM3v1Aldrout = value->rValue; + mod->BSIM3v1AldroutGiven = TRUE; + break; + case BSIM3v1A_MOD_LDSUB: + mod->BSIM3v1Aldsub = value->rValue; + mod->BSIM3v1AldsubGiven = TRUE; + break; + case BSIM3v1A_MOD_LVTH0: + mod->BSIM3v1Alvth0 = value->rValue; + mod->BSIM3v1Alvth0Given = TRUE; + break; + case BSIM3v1A_MOD_LUA: + mod->BSIM3v1Alua = value->rValue; + mod->BSIM3v1AluaGiven = TRUE; + break; + case BSIM3v1A_MOD_LUA1: + mod->BSIM3v1Alua1 = value->rValue; + mod->BSIM3v1Alua1Given = TRUE; + break; + case BSIM3v1A_MOD_LUB: + mod->BSIM3v1Alub = value->rValue; + mod->BSIM3v1AlubGiven = TRUE; + break; + case BSIM3v1A_MOD_LUB1: + mod->BSIM3v1Alub1 = value->rValue; + mod->BSIM3v1Alub1Given = TRUE; + break; + case BSIM3v1A_MOD_LUC: + mod->BSIM3v1Aluc = value->rValue; + mod->BSIM3v1AlucGiven = TRUE; + break; + case BSIM3v1A_MOD_LUC1: + mod->BSIM3v1Aluc1 = value->rValue; + mod->BSIM3v1Aluc1Given = TRUE; + break; + case BSIM3v1A_MOD_LU0 : + mod->BSIM3v1Alu0 = value->rValue; + mod->BSIM3v1Alu0Given = TRUE; + if (mod->BSIM3v1Alu0 > 1.0) + mod->BSIM3v1Alu0 *= 1.0e-4; + break; + case BSIM3v1A_MOD_LUTE : + mod->BSIM3v1Alute = value->rValue; + mod->BSIM3v1AluteGiven = TRUE; + break; + case BSIM3v1A_MOD_LVOFF: + mod->BSIM3v1Alvoff = value->rValue; + mod->BSIM3v1AlvoffGiven = TRUE; + break; + case BSIM3v1A_MOD_LDELTA : + mod->BSIM3v1Aldelta = value->rValue; + mod->BSIM3v1AldeltaGiven = TRUE; + break; + case BSIM3v1A_MOD_LRDSW: + mod->BSIM3v1Alrdsw = value->rValue; + mod->BSIM3v1AlrdswGiven = TRUE; + break; + case BSIM3v1A_MOD_LPRWB: + mod->BSIM3v1Alprwb = value->rValue; + mod->BSIM3v1AlprwbGiven = TRUE; + break; + case BSIM3v1A_MOD_LPRWG: + mod->BSIM3v1Alprwg = value->rValue; + mod->BSIM3v1AlprwgGiven = TRUE; + break; + case BSIM3v1A_MOD_LPRT: + mod->BSIM3v1Alprt = value->rValue; + mod->BSIM3v1AlprtGiven = TRUE; + break; + case BSIM3v1A_MOD_LETA0: + mod->BSIM3v1Aleta0 = value->rValue; + mod->BSIM3v1Aleta0Given = TRUE; + break; + case BSIM3v1A_MOD_LETAB: + mod->BSIM3v1Aletab = value->rValue; + mod->BSIM3v1AletabGiven = TRUE; + break; + case BSIM3v1A_MOD_LPCLM: + mod->BSIM3v1Alpclm = value->rValue; + mod->BSIM3v1AlpclmGiven = TRUE; + break; + case BSIM3v1A_MOD_LPDIBL1: + mod->BSIM3v1Alpdibl1 = value->rValue; + mod->BSIM3v1Alpdibl1Given = TRUE; + break; + case BSIM3v1A_MOD_LPDIBL2: + mod->BSIM3v1Alpdibl2 = value->rValue; + mod->BSIM3v1Alpdibl2Given = TRUE; + break; + case BSIM3v1A_MOD_LPDIBLB: + mod->BSIM3v1Alpdiblb = value->rValue; + mod->BSIM3v1AlpdiblbGiven = TRUE; + break; + case BSIM3v1A_MOD_LPSCBE1: + mod->BSIM3v1Alpscbe1 = value->rValue; + mod->BSIM3v1Alpscbe1Given = TRUE; + break; + case BSIM3v1A_MOD_LPSCBE2: + mod->BSIM3v1Alpscbe2 = value->rValue; + mod->BSIM3v1Alpscbe2Given = TRUE; + break; + case BSIM3v1A_MOD_LPVAG: + mod->BSIM3v1Alpvag = value->rValue; + mod->BSIM3v1AlpvagGiven = TRUE; + break; + case BSIM3v1A_MOD_LWR : + mod->BSIM3v1Alwr = value->rValue; + mod->BSIM3v1AlwrGiven = TRUE; + break; + case BSIM3v1A_MOD_LDWG : + mod->BSIM3v1Aldwg = value->rValue; + mod->BSIM3v1AldwgGiven = TRUE; + break; + case BSIM3v1A_MOD_LDWB : + mod->BSIM3v1Aldwb = value->rValue; + mod->BSIM3v1AldwbGiven = TRUE; + break; + case BSIM3v1A_MOD_LB0 : + mod->BSIM3v1Alb0 = value->rValue; + mod->BSIM3v1Alb0Given = TRUE; + break; + case BSIM3v1A_MOD_LB1 : + mod->BSIM3v1Alb1 = value->rValue; + mod->BSIM3v1Alb1Given = TRUE; + break; + case BSIM3v1A_MOD_LALPHA0 : + mod->BSIM3v1Alalpha0 = value->rValue; + mod->BSIM3v1Alalpha0Given = TRUE; + break; + case BSIM3v1A_MOD_LBETA0 : + mod->BSIM3v1Albeta0 = value->rValue; + mod->BSIM3v1Albeta0Given = TRUE; + break; + + case BSIM3v1A_MOD_LELM : + mod->BSIM3v1Alelm = value->rValue; + mod->BSIM3v1AlelmGiven = TRUE; + break; + case BSIM3v1A_MOD_LCGSL : + mod->BSIM3v1Alcgsl = value->rValue; + mod->BSIM3v1AlcgslGiven = TRUE; + break; + case BSIM3v1A_MOD_LCGDL : + mod->BSIM3v1Alcgdl = value->rValue; + mod->BSIM3v1AlcgdlGiven = TRUE; + break; + case BSIM3v1A_MOD_LCKAPPA : + mod->BSIM3v1Alckappa = value->rValue; + mod->BSIM3v1AlckappaGiven = TRUE; + break; + case BSIM3v1A_MOD_LCF : + mod->BSIM3v1Alcf = value->rValue; + mod->BSIM3v1AlcfGiven = TRUE; + break; + case BSIM3v1A_MOD_LCLC : + mod->BSIM3v1Alclc = value->rValue; + mod->BSIM3v1AlclcGiven = TRUE; + break; + case BSIM3v1A_MOD_LCLE : + mod->BSIM3v1Alcle = value->rValue; + mod->BSIM3v1AlcleGiven = TRUE; + break; + + /* Width dependence */ + case BSIM3v1A_MOD_WCDSC : + mod->BSIM3v1Awcdsc = value->rValue; + mod->BSIM3v1AwcdscGiven = TRUE; + break; + + + case BSIM3v1A_MOD_WCDSCB : + mod->BSIM3v1Awcdscb = value->rValue; + mod->BSIM3v1AwcdscbGiven = TRUE; + break; + case BSIM3v1A_MOD_WCDSCD : + mod->BSIM3v1Awcdscd = value->rValue; + mod->BSIM3v1AwcdscdGiven = TRUE; + break; + case BSIM3v1A_MOD_WCIT : + mod->BSIM3v1Awcit = value->rValue; + mod->BSIM3v1AwcitGiven = TRUE; + break; + case BSIM3v1A_MOD_WNFACTOR : + mod->BSIM3v1Awnfactor = value->rValue; + mod->BSIM3v1AwnfactorGiven = TRUE; + break; + case BSIM3v1A_MOD_WXJ: + mod->BSIM3v1Awxj = value->rValue; + mod->BSIM3v1AwxjGiven = TRUE; + break; + case BSIM3v1A_MOD_WVSAT: + mod->BSIM3v1Awvsat = value->rValue; + mod->BSIM3v1AwvsatGiven = TRUE; + break; + + + case BSIM3v1A_MOD_WA0: + mod->BSIM3v1Awa0 = value->rValue; + mod->BSIM3v1Awa0Given = TRUE; + break; + case BSIM3v1A_MOD_WAGS: + mod->BSIM3v1Awags = value->rValue; + mod->BSIM3v1AwagsGiven = TRUE; + break; + case BSIM3v1A_MOD_WA1: + mod->BSIM3v1Awa1 = value->rValue; + mod->BSIM3v1Awa1Given = TRUE; + break; + case BSIM3v1A_MOD_WA2: + mod->BSIM3v1Awa2 = value->rValue; + mod->BSIM3v1Awa2Given = TRUE; + break; + case BSIM3v1A_MOD_WAT: + mod->BSIM3v1Awat = value->rValue; + mod->BSIM3v1AwatGiven = TRUE; + break; + case BSIM3v1A_MOD_WKETA: + mod->BSIM3v1Awketa = value->rValue; + mod->BSIM3v1AwketaGiven = TRUE; + break; + case BSIM3v1A_MOD_WNSUB: + mod->BSIM3v1Awnsub = value->rValue; + mod->BSIM3v1AwnsubGiven = TRUE; + break; + case BSIM3v1A_MOD_WNPEAK: + mod->BSIM3v1Awnpeak = value->rValue; + mod->BSIM3v1AwnpeakGiven = TRUE; + if (mod->BSIM3v1Awnpeak > 1.0e20) + mod->BSIM3v1Awnpeak *= 1.0e-6; + break; + case BSIM3v1A_MOD_WNGATE: + mod->BSIM3v1Awngate = value->rValue; + mod->BSIM3v1AwngateGiven = TRUE; + if (mod->BSIM3v1Awngate > 1.0e23) + mod->BSIM3v1Awngate *= 1.0e-6; + break; + case BSIM3v1A_MOD_WGAMMA1: + mod->BSIM3v1Awgamma1 = value->rValue; + mod->BSIM3v1Awgamma1Given = TRUE; + break; + case BSIM3v1A_MOD_WGAMMA2: + mod->BSIM3v1Awgamma2 = value->rValue; + mod->BSIM3v1Awgamma2Given = TRUE; + break; + case BSIM3v1A_MOD_WVBX: + mod->BSIM3v1Awvbx = value->rValue; + mod->BSIM3v1AwvbxGiven = TRUE; + break; + case BSIM3v1A_MOD_WVBM: + mod->BSIM3v1Awvbm = value->rValue; + mod->BSIM3v1AwvbmGiven = TRUE; + break; + case BSIM3v1A_MOD_WXT: + mod->BSIM3v1Awxt = value->rValue; + mod->BSIM3v1AwxtGiven = TRUE; + break; + case BSIM3v1A_MOD_WK1: + mod->BSIM3v1Awk1 = value->rValue; + mod->BSIM3v1Awk1Given = TRUE; + break; + case BSIM3v1A_MOD_WKT1: + mod->BSIM3v1Awkt1 = value->rValue; + mod->BSIM3v1Awkt1Given = TRUE; + break; + case BSIM3v1A_MOD_WKT1L: + mod->BSIM3v1Awkt1l = value->rValue; + mod->BSIM3v1Awkt1lGiven = TRUE; + break; + case BSIM3v1A_MOD_WKT2: + mod->BSIM3v1Awkt2 = value->rValue; + mod->BSIM3v1Awkt2Given = TRUE; + break; + case BSIM3v1A_MOD_WK2: + mod->BSIM3v1Awk2 = value->rValue; + mod->BSIM3v1Awk2Given = TRUE; + break; + case BSIM3v1A_MOD_WK3: + mod->BSIM3v1Awk3 = value->rValue; + mod->BSIM3v1Awk3Given = TRUE; + break; + case BSIM3v1A_MOD_WK3B: + mod->BSIM3v1Awk3b = value->rValue; + mod->BSIM3v1Awk3bGiven = TRUE; + break; + case BSIM3v1A_MOD_WNLX: + mod->BSIM3v1Awnlx = value->rValue; + mod->BSIM3v1AwnlxGiven = TRUE; + break; + case BSIM3v1A_MOD_WW0: + mod->BSIM3v1Aww0 = value->rValue; + mod->BSIM3v1Aww0Given = TRUE; + break; + case BSIM3v1A_MOD_WDVT0: + mod->BSIM3v1Awdvt0 = value->rValue; + mod->BSIM3v1Awdvt0Given = TRUE; + break; + case BSIM3v1A_MOD_WDVT1: + mod->BSIM3v1Awdvt1 = value->rValue; + mod->BSIM3v1Awdvt1Given = TRUE; + break; + case BSIM3v1A_MOD_WDVT2: + mod->BSIM3v1Awdvt2 = value->rValue; + mod->BSIM3v1Awdvt2Given = TRUE; + break; + case BSIM3v1A_MOD_WDVT0W: + mod->BSIM3v1Awdvt0w = value->rValue; + mod->BSIM3v1Awdvt0wGiven = TRUE; + break; + case BSIM3v1A_MOD_WDVT1W: + mod->BSIM3v1Awdvt1w = value->rValue; + mod->BSIM3v1Awdvt1wGiven = TRUE; + break; + case BSIM3v1A_MOD_WDVT2W: + mod->BSIM3v1Awdvt2w = value->rValue; + mod->BSIM3v1Awdvt2wGiven = TRUE; + break; + case BSIM3v1A_MOD_WDROUT: + mod->BSIM3v1Awdrout = value->rValue; + mod->BSIM3v1AwdroutGiven = TRUE; + break; + case BSIM3v1A_MOD_WDSUB: + mod->BSIM3v1Awdsub = value->rValue; + mod->BSIM3v1AwdsubGiven = TRUE; + break; + case BSIM3v1A_MOD_WVTH0: + mod->BSIM3v1Awvth0 = value->rValue; + mod->BSIM3v1Awvth0Given = TRUE; + break; + case BSIM3v1A_MOD_WUA: + mod->BSIM3v1Awua = value->rValue; + mod->BSIM3v1AwuaGiven = TRUE; + break; + case BSIM3v1A_MOD_WUA1: + mod->BSIM3v1Awua1 = value->rValue; + mod->BSIM3v1Awua1Given = TRUE; + break; + case BSIM3v1A_MOD_WUB: + mod->BSIM3v1Awub = value->rValue; + mod->BSIM3v1AwubGiven = TRUE; + break; + case BSIM3v1A_MOD_WUB1: + mod->BSIM3v1Awub1 = value->rValue; + mod->BSIM3v1Awub1Given = TRUE; + break; + case BSIM3v1A_MOD_WUC: + mod->BSIM3v1Awuc = value->rValue; + mod->BSIM3v1AwucGiven = TRUE; + break; + case BSIM3v1A_MOD_WUC1: + mod->BSIM3v1Awuc1 = value->rValue; + mod->BSIM3v1Awuc1Given = TRUE; + break; + case BSIM3v1A_MOD_WU0 : + mod->BSIM3v1Awu0 = value->rValue; + mod->BSIM3v1Awu0Given = TRUE; + if (mod->BSIM3v1Awu0 > 1.0) + mod->BSIM3v1Awu0 *= 1.0e-4; + break; + case BSIM3v1A_MOD_WUTE : + mod->BSIM3v1Awute = value->rValue; + mod->BSIM3v1AwuteGiven = TRUE; + break; + case BSIM3v1A_MOD_WVOFF: + mod->BSIM3v1Awvoff = value->rValue; + mod->BSIM3v1AwvoffGiven = TRUE; + break; + case BSIM3v1A_MOD_WDELTA : + mod->BSIM3v1Awdelta = value->rValue; + mod->BSIM3v1AwdeltaGiven = TRUE; + break; + case BSIM3v1A_MOD_WRDSW: + mod->BSIM3v1Awrdsw = value->rValue; + mod->BSIM3v1AwrdswGiven = TRUE; + break; + case BSIM3v1A_MOD_WPRWB: + mod->BSIM3v1Awprwb = value->rValue; + mod->BSIM3v1AwprwbGiven = TRUE; + break; + case BSIM3v1A_MOD_WPRWG: + mod->BSIM3v1Awprwg = value->rValue; + mod->BSIM3v1AwprwgGiven = TRUE; + break; + case BSIM3v1A_MOD_WPRT: + mod->BSIM3v1Awprt = value->rValue; + mod->BSIM3v1AwprtGiven = TRUE; + break; + case BSIM3v1A_MOD_WETA0: + mod->BSIM3v1Aweta0 = value->rValue; + mod->BSIM3v1Aweta0Given = TRUE; + break; + case BSIM3v1A_MOD_WETAB: + mod->BSIM3v1Awetab = value->rValue; + mod->BSIM3v1AwetabGiven = TRUE; + break; + case BSIM3v1A_MOD_WPCLM: + mod->BSIM3v1Awpclm = value->rValue; + mod->BSIM3v1AwpclmGiven = TRUE; + break; + case BSIM3v1A_MOD_WPDIBL1: + mod->BSIM3v1Awpdibl1 = value->rValue; + mod->BSIM3v1Awpdibl1Given = TRUE; + break; + case BSIM3v1A_MOD_WPDIBL2: + mod->BSIM3v1Awpdibl2 = value->rValue; + mod->BSIM3v1Awpdibl2Given = TRUE; + break; + case BSIM3v1A_MOD_WPDIBLB: + mod->BSIM3v1Awpdiblb = value->rValue; + mod->BSIM3v1AwpdiblbGiven = TRUE; + break; + case BSIM3v1A_MOD_WPSCBE1: + mod->BSIM3v1Awpscbe1 = value->rValue; + mod->BSIM3v1Awpscbe1Given = TRUE; + break; + case BSIM3v1A_MOD_WPSCBE2: + mod->BSIM3v1Awpscbe2 = value->rValue; + mod->BSIM3v1Awpscbe2Given = TRUE; + break; + case BSIM3v1A_MOD_WPVAG: + mod->BSIM3v1Awpvag = value->rValue; + mod->BSIM3v1AwpvagGiven = TRUE; + break; + case BSIM3v1A_MOD_WWR : + mod->BSIM3v1Awwr = value->rValue; + mod->BSIM3v1AwwrGiven = TRUE; + break; + case BSIM3v1A_MOD_WDWG : + mod->BSIM3v1Awdwg = value->rValue; + mod->BSIM3v1AwdwgGiven = TRUE; + break; + case BSIM3v1A_MOD_WDWB : + mod->BSIM3v1Awdwb = value->rValue; + mod->BSIM3v1AwdwbGiven = TRUE; + break; + case BSIM3v1A_MOD_WB0 : + mod->BSIM3v1Awb0 = value->rValue; + mod->BSIM3v1Awb0Given = TRUE; + break; + case BSIM3v1A_MOD_WB1 : + mod->BSIM3v1Awb1 = value->rValue; + mod->BSIM3v1Awb1Given = TRUE; + break; + case BSIM3v1A_MOD_WALPHA0 : + mod->BSIM3v1Awalpha0 = value->rValue; + mod->BSIM3v1Awalpha0Given = TRUE; + break; + case BSIM3v1A_MOD_WBETA0 : + mod->BSIM3v1Awbeta0 = value->rValue; + mod->BSIM3v1Awbeta0Given = TRUE; + break; + + case BSIM3v1A_MOD_WELM : + mod->BSIM3v1Awelm = value->rValue; + mod->BSIM3v1AwelmGiven = TRUE; + break; + case BSIM3v1A_MOD_WCGSL : + mod->BSIM3v1Awcgsl = value->rValue; + mod->BSIM3v1AwcgslGiven = TRUE; + break; + case BSIM3v1A_MOD_WCGDL : + mod->BSIM3v1Awcgdl = value->rValue; + mod->BSIM3v1AwcgdlGiven = TRUE; + break; + case BSIM3v1A_MOD_WCKAPPA : + mod->BSIM3v1Awckappa = value->rValue; + mod->BSIM3v1AwckappaGiven = TRUE; + break; + case BSIM3v1A_MOD_WCF : + mod->BSIM3v1Awcf = value->rValue; + mod->BSIM3v1AwcfGiven = TRUE; + break; + case BSIM3v1A_MOD_WCLC : + mod->BSIM3v1Awclc = value->rValue; + mod->BSIM3v1AwclcGiven = TRUE; + break; + case BSIM3v1A_MOD_WCLE : + mod->BSIM3v1Awcle = value->rValue; + mod->BSIM3v1AwcleGiven = TRUE; + break; + + /* Cross-term dependence */ + case BSIM3v1A_MOD_PCDSC : + mod->BSIM3v1Apcdsc = value->rValue; + mod->BSIM3v1ApcdscGiven = TRUE; + break; + + + case BSIM3v1A_MOD_PCDSCB : + mod->BSIM3v1Apcdscb = value->rValue; + mod->BSIM3v1ApcdscbGiven = TRUE; + break; + case BSIM3v1A_MOD_PCDSCD : + mod->BSIM3v1Apcdscd = value->rValue; + mod->BSIM3v1ApcdscdGiven = TRUE; + break; + case BSIM3v1A_MOD_PCIT : + mod->BSIM3v1Apcit = value->rValue; + mod->BSIM3v1ApcitGiven = TRUE; + break; + case BSIM3v1A_MOD_PNFACTOR : + mod->BSIM3v1Apnfactor = value->rValue; + mod->BSIM3v1ApnfactorGiven = TRUE; + break; + case BSIM3v1A_MOD_PXJ: + mod->BSIM3v1Apxj = value->rValue; + mod->BSIM3v1ApxjGiven = TRUE; + break; + case BSIM3v1A_MOD_PVSAT: + mod->BSIM3v1Apvsat = value->rValue; + mod->BSIM3v1ApvsatGiven = TRUE; + break; + + + case BSIM3v1A_MOD_PA0: + mod->BSIM3v1Apa0 = value->rValue; + mod->BSIM3v1Apa0Given = TRUE; + break; + case BSIM3v1A_MOD_PAGS: + mod->BSIM3v1Apags = value->rValue; + mod->BSIM3v1ApagsGiven = TRUE; + break; + case BSIM3v1A_MOD_PA1: + mod->BSIM3v1Apa1 = value->rValue; + mod->BSIM3v1Apa1Given = TRUE; + break; + case BSIM3v1A_MOD_PA2: + mod->BSIM3v1Apa2 = value->rValue; + mod->BSIM3v1Apa2Given = TRUE; + break; + case BSIM3v1A_MOD_PAT: + mod->BSIM3v1Apat = value->rValue; + mod->BSIM3v1ApatGiven = TRUE; + break; + case BSIM3v1A_MOD_PKETA: + mod->BSIM3v1Apketa = value->rValue; + mod->BSIM3v1ApketaGiven = TRUE; + break; + case BSIM3v1A_MOD_PNSUB: + mod->BSIM3v1Apnsub = value->rValue; + mod->BSIM3v1ApnsubGiven = TRUE; + break; + case BSIM3v1A_MOD_PNPEAK: + mod->BSIM3v1Apnpeak = value->rValue; + mod->BSIM3v1ApnpeakGiven = TRUE; + if (mod->BSIM3v1Apnpeak > 1.0e20) + mod->BSIM3v1Apnpeak *= 1.0e-6; + break; + case BSIM3v1A_MOD_PNGATE: + mod->BSIM3v1Apngate = value->rValue; + mod->BSIM3v1ApngateGiven = TRUE; + if (mod->BSIM3v1Apngate > 1.0e23) + mod->BSIM3v1Apngate *= 1.0e-6; + break; + case BSIM3v1A_MOD_PGAMMA1: + mod->BSIM3v1Apgamma1 = value->rValue; + mod->BSIM3v1Apgamma1Given = TRUE; + break; + case BSIM3v1A_MOD_PGAMMA2: + mod->BSIM3v1Apgamma2 = value->rValue; + mod->BSIM3v1Apgamma2Given = TRUE; + break; + case BSIM3v1A_MOD_PVBX: + mod->BSIM3v1Apvbx = value->rValue; + mod->BSIM3v1ApvbxGiven = TRUE; + break; + case BSIM3v1A_MOD_PVBM: + mod->BSIM3v1Apvbm = value->rValue; + mod->BSIM3v1ApvbmGiven = TRUE; + break; + case BSIM3v1A_MOD_PXT: + mod->BSIM3v1Apxt = value->rValue; + mod->BSIM3v1ApxtGiven = TRUE; + break; + case BSIM3v1A_MOD_PK1: + mod->BSIM3v1Apk1 = value->rValue; + mod->BSIM3v1Apk1Given = TRUE; + break; + case BSIM3v1A_MOD_PKT1: + mod->BSIM3v1Apkt1 = value->rValue; + mod->BSIM3v1Apkt1Given = TRUE; + break; + case BSIM3v1A_MOD_PKT1L: + mod->BSIM3v1Apkt1l = value->rValue; + mod->BSIM3v1Apkt1lGiven = TRUE; + break; + case BSIM3v1A_MOD_PKT2: + mod->BSIM3v1Apkt2 = value->rValue; + mod->BSIM3v1Apkt2Given = TRUE; + break; + case BSIM3v1A_MOD_PK2: + mod->BSIM3v1Apk2 = value->rValue; + mod->BSIM3v1Apk2Given = TRUE; + break; + case BSIM3v1A_MOD_PK3: + mod->BSIM3v1Apk3 = value->rValue; + mod->BSIM3v1Apk3Given = TRUE; + break; + case BSIM3v1A_MOD_PK3B: + mod->BSIM3v1Apk3b = value->rValue; + mod->BSIM3v1Apk3bGiven = TRUE; + break; + case BSIM3v1A_MOD_PNLX: + mod->BSIM3v1Apnlx = value->rValue; + mod->BSIM3v1ApnlxGiven = TRUE; + break; + case BSIM3v1A_MOD_PW0: + mod->BSIM3v1Apw0 = value->rValue; + mod->BSIM3v1Apw0Given = TRUE; + break; + case BSIM3v1A_MOD_PDVT0: + mod->BSIM3v1Apdvt0 = value->rValue; + mod->BSIM3v1Apdvt0Given = TRUE; + break; + case BSIM3v1A_MOD_PDVT1: + mod->BSIM3v1Apdvt1 = value->rValue; + mod->BSIM3v1Apdvt1Given = TRUE; + break; + case BSIM3v1A_MOD_PDVT2: + mod->BSIM3v1Apdvt2 = value->rValue; + mod->BSIM3v1Apdvt2Given = TRUE; + break; + case BSIM3v1A_MOD_PDVT0W: + mod->BSIM3v1Apdvt0w = value->rValue; + mod->BSIM3v1Apdvt0wGiven = TRUE; + break; + case BSIM3v1A_MOD_PDVT1W: + mod->BSIM3v1Apdvt1w = value->rValue; + mod->BSIM3v1Apdvt1wGiven = TRUE; + break; + case BSIM3v1A_MOD_PDVT2W: + mod->BSIM3v1Apdvt2w = value->rValue; + mod->BSIM3v1Apdvt2wGiven = TRUE; + break; + case BSIM3v1A_MOD_PDROUT: + mod->BSIM3v1Apdrout = value->rValue; + mod->BSIM3v1ApdroutGiven = TRUE; + break; + case BSIM3v1A_MOD_PDSUB: + mod->BSIM3v1Apdsub = value->rValue; + mod->BSIM3v1ApdsubGiven = TRUE; + break; + case BSIM3v1A_MOD_PVTH0: + mod->BSIM3v1Apvth0 = value->rValue; + mod->BSIM3v1Apvth0Given = TRUE; + break; + case BSIM3v1A_MOD_PUA: + mod->BSIM3v1Apua = value->rValue; + mod->BSIM3v1ApuaGiven = TRUE; + break; + case BSIM3v1A_MOD_PUA1: + mod->BSIM3v1Apua1 = value->rValue; + mod->BSIM3v1Apua1Given = TRUE; + break; + case BSIM3v1A_MOD_PUB: + mod->BSIM3v1Apub = value->rValue; + mod->BSIM3v1ApubGiven = TRUE; + break; + case BSIM3v1A_MOD_PUB1: + mod->BSIM3v1Apub1 = value->rValue; + mod->BSIM3v1Apub1Given = TRUE; + break; + case BSIM3v1A_MOD_PUC: + mod->BSIM3v1Apuc = value->rValue; + mod->BSIM3v1ApucGiven = TRUE; + break; + case BSIM3v1A_MOD_PUC1: + mod->BSIM3v1Apuc1 = value->rValue; + mod->BSIM3v1Apuc1Given = TRUE; + break; + case BSIM3v1A_MOD_PU0 : + mod->BSIM3v1Apu0 = value->rValue; + mod->BSIM3v1Apu0Given = TRUE; + if (mod->BSIM3v1Apu0 > 1.0) + mod->BSIM3v1Apu0 *= 1.0e-4; + break; + case BSIM3v1A_MOD_PUTE : + mod->BSIM3v1Apute = value->rValue; + mod->BSIM3v1AputeGiven = TRUE; + break; + case BSIM3v1A_MOD_PVOFF: + mod->BSIM3v1Apvoff = value->rValue; + mod->BSIM3v1ApvoffGiven = TRUE; + break; + case BSIM3v1A_MOD_PDELTA : + mod->BSIM3v1Apdelta = value->rValue; + mod->BSIM3v1ApdeltaGiven = TRUE; + break; + case BSIM3v1A_MOD_PRDSW: + mod->BSIM3v1Aprdsw = value->rValue; + mod->BSIM3v1AprdswGiven = TRUE; + break; + case BSIM3v1A_MOD_PPRWB: + mod->BSIM3v1Apprwb = value->rValue; + mod->BSIM3v1ApprwbGiven = TRUE; + break; + case BSIM3v1A_MOD_PPRWG: + mod->BSIM3v1Apprwg = value->rValue; + mod->BSIM3v1ApprwgGiven = TRUE; + break; + case BSIM3v1A_MOD_PPRT: + mod->BSIM3v1Apprt = value->rValue; + mod->BSIM3v1ApprtGiven = TRUE; + break; + case BSIM3v1A_MOD_PETA0: + mod->BSIM3v1Apeta0 = value->rValue; + mod->BSIM3v1Apeta0Given = TRUE; + break; + case BSIM3v1A_MOD_PETAB: + mod->BSIM3v1Apetab = value->rValue; + mod->BSIM3v1ApetabGiven = TRUE; + break; + case BSIM3v1A_MOD_PPCLM: + mod->BSIM3v1Appclm = value->rValue; + mod->BSIM3v1AppclmGiven = TRUE; + break; + case BSIM3v1A_MOD_PPDIBL1: + mod->BSIM3v1Appdibl1 = value->rValue; + mod->BSIM3v1Appdibl1Given = TRUE; + break; + case BSIM3v1A_MOD_PPDIBL2: + mod->BSIM3v1Appdibl2 = value->rValue; + mod->BSIM3v1Appdibl2Given = TRUE; + break; + case BSIM3v1A_MOD_PPDIBLB: + mod->BSIM3v1Appdiblb = value->rValue; + mod->BSIM3v1AppdiblbGiven = TRUE; + break; + case BSIM3v1A_MOD_PPSCBE1: + mod->BSIM3v1Appscbe1 = value->rValue; + mod->BSIM3v1Appscbe1Given = TRUE; + break; + case BSIM3v1A_MOD_PPSCBE2: + mod->BSIM3v1Appscbe2 = value->rValue; + mod->BSIM3v1Appscbe2Given = TRUE; + break; + case BSIM3v1A_MOD_PPVAG: + mod->BSIM3v1Appvag = value->rValue; + mod->BSIM3v1AppvagGiven = TRUE; + break; + case BSIM3v1A_MOD_PWR : + mod->BSIM3v1Apwr = value->rValue; + mod->BSIM3v1ApwrGiven = TRUE; + break; + case BSIM3v1A_MOD_PDWG : + mod->BSIM3v1Apdwg = value->rValue; + mod->BSIM3v1ApdwgGiven = TRUE; + break; + case BSIM3v1A_MOD_PDWB : + mod->BSIM3v1Apdwb = value->rValue; + mod->BSIM3v1ApdwbGiven = TRUE; + break; + case BSIM3v1A_MOD_PB0 : + mod->BSIM3v1Apb0 = value->rValue; + mod->BSIM3v1Apb0Given = TRUE; + break; + case BSIM3v1A_MOD_PB1 : + mod->BSIM3v1Apb1 = value->rValue; + mod->BSIM3v1Apb1Given = TRUE; + break; + case BSIM3v1A_MOD_PALPHA0 : + mod->BSIM3v1Apalpha0 = value->rValue; + mod->BSIM3v1Apalpha0Given = TRUE; + break; + case BSIM3v1A_MOD_PBETA0 : + mod->BSIM3v1Apbeta0 = value->rValue; + mod->BSIM3v1Apbeta0Given = TRUE; + break; + + case BSIM3v1A_MOD_PELM : + mod->BSIM3v1Apelm = value->rValue; + mod->BSIM3v1ApelmGiven = TRUE; + break; + case BSIM3v1A_MOD_PCGSL : + mod->BSIM3v1Apcgsl = value->rValue; + mod->BSIM3v1ApcgslGiven = TRUE; + break; + case BSIM3v1A_MOD_PCGDL : + mod->BSIM3v1Apcgdl = value->rValue; + mod->BSIM3v1ApcgdlGiven = TRUE; + break; + case BSIM3v1A_MOD_PCKAPPA : + mod->BSIM3v1Apckappa = value->rValue; + mod->BSIM3v1ApckappaGiven = TRUE; + break; + case BSIM3v1A_MOD_PCF : + mod->BSIM3v1Apcf = value->rValue; + mod->BSIM3v1ApcfGiven = TRUE; + break; + case BSIM3v1A_MOD_PCLC : + mod->BSIM3v1Apclc = value->rValue; + mod->BSIM3v1ApclcGiven = TRUE; + break; + case BSIM3v1A_MOD_PCLE : + mod->BSIM3v1Apcle = value->rValue; + mod->BSIM3v1ApcleGiven = TRUE; + break; + + case BSIM3v1A_MOD_TNOM : + mod->BSIM3v1Atnom = value->rValue + 273.15; + mod->BSIM3v1AtnomGiven = TRUE; + break; + case BSIM3v1A_MOD_CGSO : + mod->BSIM3v1Acgso = value->rValue; + mod->BSIM3v1AcgsoGiven = TRUE; + break; + case BSIM3v1A_MOD_CGDO : + mod->BSIM3v1Acgdo = value->rValue; + mod->BSIM3v1AcgdoGiven = TRUE; + break; + case BSIM3v1A_MOD_CGBO : + mod->BSIM3v1Acgbo = value->rValue; + mod->BSIM3v1AcgboGiven = TRUE; + break; + case BSIM3v1A_MOD_XPART : + mod->BSIM3v1Axpart = value->rValue; + mod->BSIM3v1AxpartGiven = TRUE; + break; + case BSIM3v1A_MOD_RSH : + mod->BSIM3v1AsheetResistance = value->rValue; + mod->BSIM3v1AsheetResistanceGiven = TRUE; + break; + case BSIM3v1A_MOD_JS : + mod->BSIM3v1AjctSatCurDensity = value->rValue; + mod->BSIM3v1AjctSatCurDensityGiven = TRUE; + break; + case BSIM3v1A_MOD_PB : + mod->BSIM3v1AbulkJctPotential = value->rValue; + mod->BSIM3v1AbulkJctPotentialGiven = TRUE; + break; + case BSIM3v1A_MOD_MJ : + mod->BSIM3v1AbulkJctBotGradingCoeff = value->rValue; + mod->BSIM3v1AbulkJctBotGradingCoeffGiven = TRUE; + break; + case BSIM3v1A_MOD_PBSW : + mod->BSIM3v1AsidewallJctPotential = value->rValue; + mod->BSIM3v1AsidewallJctPotentialGiven = TRUE; + break; + case BSIM3v1A_MOD_MJSW : + mod->BSIM3v1AbulkJctSideGradingCoeff = value->rValue; + mod->BSIM3v1AbulkJctSideGradingCoeffGiven = TRUE; + break; + case BSIM3v1A_MOD_CJ : + mod->BSIM3v1AunitAreaJctCap = value->rValue; + mod->BSIM3v1AunitAreaJctCapGiven = TRUE; + break; + case BSIM3v1A_MOD_CJSW : + mod->BSIM3v1AunitLengthSidewallJctCap = value->rValue; + mod->BSIM3v1AunitLengthSidewallJctCapGiven = TRUE; + break; + case BSIM3v1A_MOD_LINT : + mod->BSIM3v1ALint = value->rValue; + mod->BSIM3v1ALintGiven = TRUE; + break; + case BSIM3v1A_MOD_LL : + mod->BSIM3v1ALl = value->rValue; + mod->BSIM3v1ALlGiven = TRUE; + break; + case BSIM3v1A_MOD_LLN : + mod->BSIM3v1ALln = value->rValue; + mod->BSIM3v1ALlnGiven = TRUE; + break; + case BSIM3v1A_MOD_LW : + mod->BSIM3v1ALw = value->rValue; + mod->BSIM3v1ALwGiven = TRUE; + break; + case BSIM3v1A_MOD_LWN : + mod->BSIM3v1ALwn = value->rValue; + mod->BSIM3v1ALwnGiven = TRUE; + break; + case BSIM3v1A_MOD_LWL : + mod->BSIM3v1ALwl = value->rValue; + mod->BSIM3v1ALwlGiven = TRUE; + break; + case BSIM3v1A_MOD_LMIN : + mod->BSIM3v1ALmin = value->rValue; + mod->BSIM3v1ALminGiven = TRUE; + break; + case BSIM3v1A_MOD_LMAX : + mod->BSIM3v1ALmax = value->rValue; + mod->BSIM3v1ALmaxGiven = TRUE; + break; + case BSIM3v1A_MOD_WINT : + mod->BSIM3v1AWint = value->rValue; + mod->BSIM3v1AWintGiven = TRUE; + break; + case BSIM3v1A_MOD_WL : + mod->BSIM3v1AWl = value->rValue; + mod->BSIM3v1AWlGiven = TRUE; + break; + case BSIM3v1A_MOD_WLN : + mod->BSIM3v1AWln = value->rValue; + mod->BSIM3v1AWlnGiven = TRUE; + break; + case BSIM3v1A_MOD_WW : + mod->BSIM3v1AWw = value->rValue; + mod->BSIM3v1AWwGiven = TRUE; + break; + case BSIM3v1A_MOD_WWN : + mod->BSIM3v1AWwn = value->rValue; + mod->BSIM3v1AWwnGiven = TRUE; + break; + case BSIM3v1A_MOD_WWL : + mod->BSIM3v1AWwl = value->rValue; + mod->BSIM3v1AWwlGiven = TRUE; + break; + case BSIM3v1A_MOD_WMIN : + mod->BSIM3v1AWmin = value->rValue; + mod->BSIM3v1AWminGiven = TRUE; + break; + case BSIM3v1A_MOD_WMAX : + mod->BSIM3v1AWmax = value->rValue; + mod->BSIM3v1AWmaxGiven = TRUE; + break; + + case BSIM3v1A_MOD_NOIA : + mod->BSIM3v1AoxideTrapDensityA = value->rValue; + mod->BSIM3v1AoxideTrapDensityAGiven = TRUE; + break; + case BSIM3v1A_MOD_NOIB : + mod->BSIM3v1AoxideTrapDensityB = value->rValue; + mod->BSIM3v1AoxideTrapDensityBGiven = TRUE; + break; + case BSIM3v1A_MOD_NOIC : + mod->BSIM3v1AoxideTrapDensityC = value->rValue; + mod->BSIM3v1AoxideTrapDensityCGiven = TRUE; + break; + case BSIM3v1A_MOD_EM : + mod->BSIM3v1Aem = value->rValue; + mod->BSIM3v1AemGiven = TRUE; + break; + case BSIM3v1A_MOD_EF : + mod->BSIM3v1Aef = value->rValue; + mod->BSIM3v1AefGiven = TRUE; + break; + case BSIM3v1A_MOD_AF : + mod->BSIM3v1Aaf = value->rValue; + mod->BSIM3v1AafGiven = TRUE; + break; + case BSIM3v1A_MOD_KF : + mod->BSIM3v1Akf = value->rValue; + mod->BSIM3v1AkfGiven = TRUE; + break; + case BSIM3v1A_MOD_NMOS : + if(value->iValue) { + mod->BSIM3v1Atype = 1; + mod->BSIM3v1AtypeGiven = TRUE; + } + break; + case BSIM3v1A_MOD_PMOS : + if(value->iValue) { + mod->BSIM3v1Atype = - 1; + mod->BSIM3v1AtypeGiven = TRUE; + } + break; + default: + return(E_BADPARM); + } + return(OK); +} + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1anoi.c b/src/spicelib/devices/bsim3v1a/b3v1anoi.c new file mode 100644 index 000000000..d335d9c31 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1anoi.c @@ -0,0 +1,357 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Gary W. Ng and Min-Chie Jeng. +Modified by Paolo Nenzi 2002 +File: b3v1anoi.c +**********/ + +#include "ngspice.h" +#include "bsim3v1adef.h" +#include "cktdefs.h" +#include "iferrmsg.h" +#include "noisedef.h" +#include "suffix.h" +#include "const.h" /* jwan */ + +/* + * BSIM3v1Anoise (mode, operation, firstModel, ckt, data, OnDens) + * This routine names and evaluates all of the noise sources + * associated with MOSFET's. It starts with the model *firstModel and + * traverses all of its insts. It then proceeds to any other models + * on the linked list. The total output noise density generated by + * all of the MOSFET's is summed with the variable "OnDens". + */ + +extern void NevalSrc(); +extern double Nintegrate(); + + +double +StrongInversionNoiseEval(double vgs, double vds, BSIM3v1Amodel *model, + BSIM3v1Ainstance *here, double freq, double temp) +{ +struct bsim3v1aSizeDependParam *pParam; +double cd, esat, DelClm, EffFreq, N0, Nl, Vgst; +double T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, Ssi; + + pParam = here->pParam; + cd = fabs(here->BSIM3v1Acd) * here->BSIM3v1Am; + if (vds > here->BSIM3v1Avdsat) + { esat = 2.0 * pParam->BSIM3v1Avsattemp / here->BSIM3v1Aueff; + T0 = ((((vds - here->BSIM3v1Avdsat) / pParam->BSIM3v1Alitl) + model->BSIM3v1Aem) + / esat); + DelClm = pParam->BSIM3v1Alitl * log (MAX(T0, N_MINLOG)); + } + else + DelClm = 0.0; + EffFreq = pow(freq, model->BSIM3v1Aef); + T1 = CHARGE * CHARGE * 8.62e-5 * cd * (temp + CONSTCtoK) * here->BSIM3v1Aueff; + T2 = 1.0e8 * EffFreq * model->BSIM3v1Acox + * pParam->BSIM3v1Aleff * pParam->BSIM3v1Aleff; + Vgst = vgs - here->BSIM3v1Avon; + N0 = model->BSIM3v1Acox * Vgst / CHARGE; + if (N0 < 0.0) + N0 = 0.0; + Nl = model->BSIM3v1Acox * (Vgst - MIN(vds, here->BSIM3v1Avdsat)) / CHARGE; + if (Nl < 0.0) + Nl = 0.0; + + T3 = model->BSIM3v1AoxideTrapDensityA + * log(MAX(((N0 + 2.0e14) / (Nl + 2.0e14)), N_MINLOG)); + T4 = model->BSIM3v1AoxideTrapDensityB * (N0 - Nl); + T5 = model->BSIM3v1AoxideTrapDensityC * 0.5 * (N0 * N0 - Nl * Nl); + + T6 = 8.62e-5 * (temp + CONSTCtoK) * cd * cd; + T7 = 1.0e8 * EffFreq * pParam->BSIM3v1Aleff + * pParam->BSIM3v1Aleff * pParam->BSIM3v1Aweff * here->BSIM3v1Am; + T8 = model->BSIM3v1AoxideTrapDensityA + model->BSIM3v1AoxideTrapDensityB * Nl + + model->BSIM3v1AoxideTrapDensityC * Nl * Nl; + T9 = (Nl + 2.0e14) * (Nl + 2.0e14); + + Ssi = T1 / T2 * (T3 + T4 + T5) + T6 / T7 * DelClm * T8 / T9; + return Ssi; +} + +int +BSIM3v1Anoise (int mode, int operation, GENmodel *inModel, CKTcircuit *ckt, + Ndata *data, double *OnDens) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel *)inModel; +BSIM3v1Ainstance *here; +struct bsim3v1aSizeDependParam *pParam; +char name[N_MXVLNTH]; +double tempOnoise; +double tempInoise; +double noizDens[BSIM3v1ANSRCS]; +double lnNdens[BSIM3v1ANSRCS]; + +double vgs, vds, Slimit; +double N0, Nl; +double T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13; +double n, ExpArg, Ssi, Swi; + +int error, i; + + /* define the names of the noise sources */ + static char *BSIM3v1AnNames[BSIM3v1ANSRCS] = + { /* Note that we have to keep the order */ + ".rd", /* noise due to rd */ + /* consistent with the index definitions */ + ".rs", /* noise due to rs */ + /* in BSIM3v1Adefs.h */ + ".id", /* noise due to id */ + ".1overf", /* flicker (1/f) noise */ + "" /* total transistor noise */ + }; + + for (; model != NULL; model = model->BSIM3v1AnextModel) + { for (here = model->BSIM3v1Ainstances; here != NULL; + here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + pParam = here->pParam; + switch (operation) + { case N_OPEN: + /* see if we have to to produce a summary report */ + /* if so, name all the noise generators */ + + if (((NOISEAN*)ckt->CKTcurJob)->NStpsSm != 0) + { switch (mode) + { case N_DENS: + for (i = 0; i < BSIM3v1ANSRCS; i++) + { (void) sprintf(name, "onoise.%s%s", + here->BSIM3v1Aname, + BSIM3v1AnNames[i]); + data->namelist = (IFuid *) trealloc( + (char *) data->namelist, + (data->numPlots + 1) + * sizeof(IFuid)); + if (!data->namelist) + return(E_NOMEM); + (*(SPfrontEnd->IFnewUid)) (ckt, + &(data->namelist[data->numPlots++]), + (IFuid) NULL, name, UID_OTHER, + (void **) NULL); + /* we've added one more plot */ + } + break; + case INT_NOIZ: + for (i = 0; i < BSIM3v1ANSRCS; i++) + { (void) sprintf(name, "onoise_total.%s%s", + here->BSIM3v1Aname, + BSIM3v1AnNames[i]); + data->namelist = (IFuid *) trealloc( + (char *) data->namelist, + (data->numPlots + 1) + * sizeof(IFuid)); + if (!data->namelist) + return(E_NOMEM); + (*(SPfrontEnd->IFnewUid)) (ckt, + &(data->namelist[data->numPlots++]), + (IFuid) NULL, name, UID_OTHER, + (void **) NULL); + /* we've added one more plot */ + + (void) sprintf(name, "inoise_total.%s%s", + here->BSIM3v1Aname, + BSIM3v1AnNames[i]); + data->namelist = (IFuid *) trealloc( + (char *) data->namelist, + (data->numPlots + 1) + * sizeof(IFuid)); + if (!data->namelist) + return(E_NOMEM); + (*(SPfrontEnd->IFnewUid)) (ckt, + &(data->namelist[data->numPlots++]), + (IFuid) NULL, name, UID_OTHER, + (void **)NULL); + /* we've added one more plot */ + } + break; + } + } + break; + case N_CALC: + switch (mode) + { case N_DENS: + NevalSrc(&noizDens[BSIM3v1ARDNOIZ], + &lnNdens[BSIM3v1ARDNOIZ], ckt, THERMNOISE, + here->BSIM3v1AdNodePrime, here->BSIM3v1AdNode, + here->BSIM3v1AdrainConductance * here->BSIM3v1Am); + + NevalSrc(&noizDens[BSIM3v1ARSNOIZ], + &lnNdens[BSIM3v1ARSNOIZ], ckt, THERMNOISE, + here->BSIM3v1AsNodePrime, here->BSIM3v1AsNode, + here->BSIM3v1AsourceConductance * here->BSIM3v1Am); + + if (model->BSIM3v1AnoiMod == 2) + { NevalSrc(&noizDens[BSIM3v1AIDNOIZ], + &lnNdens[BSIM3v1AIDNOIZ], ckt, THERMNOISE, + here->BSIM3v1AdNodePrime, + here->BSIM3v1AsNodePrime, (here->BSIM3v1Aueff + * fabs((here->BSIM3v1Aqinv * here->BSIM3v1Am) + / (pParam->BSIM3v1Aleff + * pParam->BSIM3v1Aleff)))); + } + else + { NevalSrc(&noizDens[BSIM3v1AIDNOIZ], + &lnNdens[BSIM3v1AIDNOIZ], ckt, THERMNOISE, + here->BSIM3v1AdNodePrime, + here->BSIM3v1AsNodePrime, + (2.0 / 3.0 * fabs(here->BSIM3v1Agm + + here->BSIM3v1Agds))); + + } + NevalSrc(&noizDens[BSIM3v1AFLNOIZ], (double*) NULL, + ckt, N_GAIN, here->BSIM3v1AdNodePrime, + here->BSIM3v1AsNodePrime, (double) 0.0); + + if (model->BSIM3v1AnoiMod == 2) + { vgs = *(ckt->CKTstates[0] + here->BSIM3v1Avgs); + vds = *(ckt->CKTstates[0] + here->BSIM3v1Avds); + if (vds < 0.0) + { vds = -vds; + vgs = vgs + vds; + } + if (vgs >= here->BSIM3v1Avon + 0.1) + { Ssi = StrongInversionNoiseEval(vgs, vds, + model, here, data->freq, + ckt->CKTtemp); + noizDens[BSIM3v1AFLNOIZ] *= Ssi; + } + else + { pParam = here->pParam; + T10 = model->BSIM3v1AoxideTrapDensityA + * 8.62e-5 * (ckt->CKTtemp + CONSTCtoK); + T11 = pParam->BSIM3v1Aweff * pParam->BSIM3v1Aleff + * pow(data->freq, model->BSIM3v1Aef) + * 4.0e36; + Swi = T10 / T11 * here->BSIM3v1Acd * here->BSIM3v1Am + * here->BSIM3v1Acd * here->BSIM3v1Am; + Slimit = StrongInversionNoiseEval( + here->BSIM3v1Avon + 0.1, + vds, model, here, + data->freq, ckt->CKTtemp); + T1 = Swi + Slimit; + if (T1 > 0.0) + noizDens[BSIM3v1AFLNOIZ] *= (Slimit * Swi) + / T1; + else + noizDens[BSIM3v1AFLNOIZ] *= 0.0; + } + } + else + { noizDens[BSIM3v1AFLNOIZ] *= model->BSIM3v1Akf * + exp(model->BSIM3v1Aaf + * log(MAX(fabs(here->BSIM3v1Acd * here->BSIM3v1Am), + N_MINLOG))) + / (pow(data->freq, model->BSIM3v1Aef) + * pParam->BSIM3v1Aleff + * pParam->BSIM3v1Aleff + * model->BSIM3v1Acox); + } + + lnNdens[BSIM3v1AFLNOIZ] = + log(MAX(noizDens[BSIM3v1AFLNOIZ], N_MINLOG)); + + noizDens[BSIM3v1ATOTNOIZ] = noizDens[BSIM3v1ARDNOIZ] + + noizDens[BSIM3v1ARSNOIZ] + + noizDens[BSIM3v1AIDNOIZ] + + noizDens[BSIM3v1AFLNOIZ]; + lnNdens[BSIM3v1ATOTNOIZ] = + log(MAX(noizDens[BSIM3v1ATOTNOIZ], N_MINLOG)); + + *OnDens += noizDens[BSIM3v1ATOTNOIZ]; + + if (data->delFreq == 0.0) + { /* if we haven't done any previous + integration, we need to initialize our + "history" variables. + */ + + for (i = 0; i < BSIM3v1ANSRCS; i++) + { here->BSIM3v1AnVar[LNLSTDENS][i] = + lnNdens[i]; + } + + /* clear out our integration variables + if it's the first pass + */ + if (data->freq == + ((NOISEAN*) ckt->CKTcurJob)->NstartFreq) + { for (i = 0; i < BSIM3v1ANSRCS; i++) + { here->BSIM3v1AnVar[OUTNOIZ][i] = 0.0; + here->BSIM3v1AnVar[INNOIZ][i] = 0.0; + } + } + } + else + { /* data->delFreq != 0.0, + we have to integrate. + */ + for (i = 0; i < BSIM3v1ANSRCS; i++) + { if (i != BSIM3v1ATOTNOIZ) + { tempOnoise = Nintegrate(noizDens[i], + lnNdens[i], + here->BSIM3v1AnVar[LNLSTDENS][i], + data); + tempInoise = Nintegrate(noizDens[i] + * data->GainSqInv, lnNdens[i] + + data->lnGainInv, + here->BSIM3v1AnVar[LNLSTDENS][i] + + data->lnGainInv, data); + here->BSIM3v1AnVar[LNLSTDENS][i] = + lnNdens[i]; + data->outNoiz += tempOnoise; + data->inNoise += tempInoise; + if (((NOISEAN*) + ckt->CKTcurJob)->NStpsSm != 0) + { here->BSIM3v1AnVar[OUTNOIZ][i] + += tempOnoise; + here->BSIM3v1AnVar[OUTNOIZ][BSIM3v1ATOTNOIZ] + += tempOnoise; + here->BSIM3v1AnVar[INNOIZ][i] + += tempInoise; + here->BSIM3v1AnVar[INNOIZ][BSIM3v1ATOTNOIZ] + += tempInoise; + } + } + } + } + if (data->prtSummary) + { for (i = 0; i < BSIM3v1ANSRCS; i++) + { /* print a summary report */ + data->outpVector[data->outNumber++] + = noizDens[i]; + } + } + break; + case INT_NOIZ: + /* already calculated, just output */ + if (((NOISEAN*)ckt->CKTcurJob)->NStpsSm != 0) + { for (i = 0; i < BSIM3v1ANSRCS; i++) + { data->outpVector[data->outNumber++] + = here->BSIM3v1AnVar[OUTNOIZ][i]; + data->outpVector[data->outNumber++] + = here->BSIM3v1AnVar[INNOIZ][i]; + } + } + break; + } + break; + case N_CLOSE: + /* do nothing, the main calling routine will close */ + return (OK); + break; /* the plots */ + } /* switch (operation) */ + } /* for here */ + } /* for model */ + + return(OK); +} + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1apar.c b/src/spicelib/devices/bsim3v1a/b3v1apar.c new file mode 100644 index 000000000..dbd0df32c --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1apar.c @@ -0,0 +1,97 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1apar.c +**********/ + +#include "ngspice.h" +#include "ifsim.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + +int +BSIM3v1Aparam(int param, IFvalue *value, GENinstance *inst, IFvalue *select) +{ + BSIM3v1Ainstance *here = (BSIM3v1Ainstance*)inst; + switch(param) + { case BSIM3v1A_W: + here->BSIM3v1Aw = value->rValue; + here->BSIM3v1AwGiven = TRUE; + break; + case BSIM3v1A_L: + here->BSIM3v1Al = value->rValue; + here->BSIM3v1AlGiven = TRUE; + break; + case BSIM3v1A_M: + here->BSIM3v1Am = value->rValue; + here->BSIM3v1AmGiven = TRUE; + break; + case BSIM3v1A_AS: + here->BSIM3v1AsourceArea = value->rValue; + here->BSIM3v1AsourceAreaGiven = TRUE; + break; + case BSIM3v1A_AD: + here->BSIM3v1AdrainArea = value->rValue; + here->BSIM3v1AdrainAreaGiven = TRUE; + break; + case BSIM3v1A_PS: + here->BSIM3v1AsourcePerimeter = value->rValue; + here->BSIM3v1AsourcePerimeterGiven = TRUE; + break; + case BSIM3v1A_PD: + here->BSIM3v1AdrainPerimeter = value->rValue; + here->BSIM3v1AdrainPerimeterGiven = TRUE; + break; + case BSIM3v1A_NRS: + here->BSIM3v1AsourceSquares = value->rValue; + here->BSIM3v1AsourceSquaresGiven = TRUE; + break; + case BSIM3v1A_NRD: + here->BSIM3v1AdrainSquares = value->rValue; + here->BSIM3v1AdrainSquaresGiven = TRUE; + break; + case BSIM3v1A_OFF: + here->BSIM3v1Aoff = value->iValue; + break; + case BSIM3v1A_IC_VBS: + here->BSIM3v1AicVBS = value->rValue; + here->BSIM3v1AicVBSGiven = TRUE; + break; + case BSIM3v1A_IC_VDS: + here->BSIM3v1AicVDS = value->rValue; + here->BSIM3v1AicVDSGiven = TRUE; + break; + case BSIM3v1A_IC_VGS: + here->BSIM3v1AicVGS = value->rValue; + here->BSIM3v1AicVGSGiven = TRUE; + break; + case BSIM3v1A_NQSMOD: + here->BSIM3v1AnqsMod = value->iValue; + here->BSIM3v1AnqsModGiven = TRUE; + break; + case BSIM3v1A_IC: + switch(value->v.numValue){ + case 3: + here->BSIM3v1AicVBS = *(value->v.vec.rVec+2); + here->BSIM3v1AicVBSGiven = TRUE; + case 2: + here->BSIM3v1AicVGS = *(value->v.vec.rVec+1); + here->BSIM3v1AicVGSGiven = TRUE; + case 1: + here->BSIM3v1AicVDS = *(value->v.vec.rVec); + here->BSIM3v1AicVDSGiven = TRUE; + break; + default: + return(E_BADPARM); + } + break; + default: + return(E_BADPARM); + } + return(OK); +} + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1apzld.c b/src/spicelib/devices/bsim3v1a/b3v1apzld.c new file mode 100644 index 000000000..3513b2945 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1apzld.c @@ -0,0 +1,152 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1apzld.c +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "complex.h" +#include "sperror.h" +#include "bsim3v1adef.h" +#include "suffix.h" + +int +BSIM3v1ApzLoad(GENmodel *inModel, CKTcircuit *ckt, SPcomplex *s) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; +double xcggb, xcgdb, xcgsb, xcbgb, xcbdb, xcbsb, xcddb, xcssb, xcdgb; +double gdpr, gspr, gds, gbd, gbs, capbd, capbs, xcsgb, xcdsb, xcsdb; +double cggb, cgdb, cgsb, cbgb, cbdb, cbsb, cddb, cdgb, cdsb; +double GSoverlapCap, GDoverlapCap, GBoverlapCap; +double FwdSum, RevSum, Gm, Gmbs; + +double m; + + for (; model != NULL; model = model->BSIM3v1AnextModel) + { for (here = model->BSIM3v1Ainstances; here!= NULL; + here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + + if (here->BSIM3v1Amode >= 0) + { Gm = here->BSIM3v1Agm; + Gmbs = here->BSIM3v1Agmbs; + FwdSum = Gm + Gmbs; + RevSum = 0.0; + cggb = here->BSIM3v1Acggb; + cgsb = here->BSIM3v1Acgsb; + cgdb = here->BSIM3v1Acgdb; + + cbgb = here->BSIM3v1Acbgb; + cbsb = here->BSIM3v1Acbsb; + cbdb = here->BSIM3v1Acbdb; + + cdgb = here->BSIM3v1Acdgb; + cdsb = here->BSIM3v1Acdsb; + cddb = here->BSIM3v1Acddb; + } + else + { Gm = -here->BSIM3v1Agm; + Gmbs = -here->BSIM3v1Agmbs; + FwdSum = 0.0; + RevSum = -Gm - Gmbs; + cggb = here->BSIM3v1Acggb; + cgsb = here->BSIM3v1Acgdb; + cgdb = here->BSIM3v1Acgsb; + + cbgb = here->BSIM3v1Acbgb; + cbsb = here->BSIM3v1Acbdb; + cbdb = here->BSIM3v1Acbsb; + + cdgb = -(here->BSIM3v1Acdgb + cggb + cbgb); + cdsb = -(here->BSIM3v1Acddb + cgsb + cbsb); + cddb = -(here->BSIM3v1Acdsb + cgdb + cbdb); + } + gdpr=here->BSIM3v1AdrainConductance; + gspr=here->BSIM3v1AsourceConductance; + gds= here->BSIM3v1Agds; + gbd= here->BSIM3v1Agbd; + gbs= here->BSIM3v1Agbs; + capbd= here->BSIM3v1Acapbd; + capbs= here->BSIM3v1Acapbs; + GSoverlapCap = here->BSIM3v1Acgso; + GDoverlapCap = here->BSIM3v1Acgdo; + GBoverlapCap = here->pParam->BSIM3v1Acgbo; + + xcdgb = (cdgb - GDoverlapCap); + xcddb = (cddb + capbd + GDoverlapCap); + xcdsb = cdsb; + xcsgb = -(cggb + cbgb + cdgb + GSoverlapCap); + xcsdb = -(cgdb + cbdb + cddb); + xcssb = (capbs + GSoverlapCap - (cgsb+cbsb+cdsb)); + xcggb = (cggb + GDoverlapCap + GSoverlapCap + GBoverlapCap); + xcgdb = (cgdb - GDoverlapCap); + xcgsb = (cgsb - GSoverlapCap); + xcbgb = (cbgb - GBoverlapCap); + xcbdb = (cbdb - capbd); + xcbsb = (cbsb - capbs); + + m = here->BSIM3v1Am; + + *(here->BSIM3v1AGgPtr ) += m * (xcggb * s->real); + *(here->BSIM3v1AGgPtr +1) += m * (xcggb * s->imag); + *(here->BSIM3v1ABbPtr ) += m * ((-xcbgb-xcbdb-xcbsb) * s->real); + *(here->BSIM3v1ABbPtr +1) += m * ((-xcbgb-xcbdb-xcbsb) * s->imag); + *(here->BSIM3v1ADPdpPtr ) += m * (xcddb * s->real); + *(here->BSIM3v1ADPdpPtr +1) += m * (xcddb * s->imag); + *(here->BSIM3v1ASPspPtr ) += m * (xcssb * s->real); + *(here->BSIM3v1ASPspPtr +1) += m * (xcssb * s->imag); + *(here->BSIM3v1AGbPtr ) += m * ((-xcggb-xcgdb-xcgsb) * s->real); + *(here->BSIM3v1AGbPtr +1) += m * ((-xcggb-xcgdb-xcgsb) * s->imag); + *(here->BSIM3v1AGdpPtr ) += m * (xcgdb * s->real); + *(here->BSIM3v1AGdpPtr +1) += m * (xcgdb * s->imag); + *(here->BSIM3v1AGspPtr ) += m * (xcgsb * s->real); + *(here->BSIM3v1AGspPtr +1) += m * (xcgsb * s->imag); + *(here->BSIM3v1ABgPtr ) += m * (xcbgb * s->real); + *(here->BSIM3v1ABgPtr +1) += m * (xcbgb * s->imag); + *(here->BSIM3v1ABdpPtr ) += m * (xcbdb * s->real); + *(here->BSIM3v1ABdpPtr +1) += m * (xcbdb * s->imag); + *(here->BSIM3v1ABspPtr ) += m * (xcbsb * s->real); + *(here->BSIM3v1ABspPtr +1) += m * (xcbsb * s->imag); + *(here->BSIM3v1ADPgPtr ) += m * (xcdgb * s->real); + *(here->BSIM3v1ADPgPtr +1) += m * (xcdgb * s->imag); + *(here->BSIM3v1ADPbPtr ) += m * ((-xcdgb-xcddb-xcdsb) * s->real); + *(here->BSIM3v1ADPbPtr +1) += m * ((-xcdgb-xcddb-xcdsb) * s->imag); + *(here->BSIM3v1ADPspPtr ) += m * (xcdsb * s->real); + *(here->BSIM3v1ADPspPtr +1) += m * (xcdsb * s->imag); + *(here->BSIM3v1ASPgPtr ) += m * (xcsgb * s->real); + *(here->BSIM3v1ASPgPtr +1) += m * (xcsgb * s->imag); + *(here->BSIM3v1ASPbPtr ) += m * ((-xcsgb-xcsdb-xcssb) * s->real); + *(here->BSIM3v1ASPbPtr +1) += m * ((-xcsgb-xcsdb-xcssb) * s->imag); + *(here->BSIM3v1ASPdpPtr ) += m * (xcsdb * s->real); + *(here->BSIM3v1ASPdpPtr +1) += m * (xcsdb * s->imag); + *(here->BSIM3v1ADdPtr) += m * gdpr; + *(here->BSIM3v1ASsPtr) += m * gspr; + *(here->BSIM3v1ABbPtr) += m * (gbd + gbs); + *(here->BSIM3v1ADPdpPtr) += m * (gdpr + gds + gbd + RevSum); + *(here->BSIM3v1ASPspPtr) += m * (gspr + gds + gbs + FwdSum); + *(here->BSIM3v1ADdpPtr) -= m * gdpr; + *(here->BSIM3v1ASspPtr) -= m * gspr; + *(here->BSIM3v1ABdpPtr) -= m * gbd; + *(here->BSIM3v1ABspPtr) -= m * gbs; + *(here->BSIM3v1ADPdPtr) -= m * gdpr; + *(here->BSIM3v1ADPgPtr) += m * Gm; + *(here->BSIM3v1ADPbPtr) -= m * (gbd - Gmbs); + *(here->BSIM3v1ADPspPtr) -= m * (gds + FwdSum); + *(here->BSIM3v1ASPgPtr) -= m * Gm; + *(here->BSIM3v1ASPsPtr) -= m * gspr; + *(here->BSIM3v1ASPbPtr) -= m * (gbs + Gmbs); + *(here->BSIM3v1ASPdpPtr) -= m * (gds + RevSum); + + } + } + return(OK); +} + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1aset.c b/src/spicelib/devices/bsim3v1a/b3v1aset.c new file mode 100644 index 000000000..51eba2e9e --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1aset.c @@ -0,0 +1,928 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1aset.c +**********/ + +#include "ngspice.h" +#include "smpdefs.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "const.h" +#include "sperror.h" +#include "suffix.h" + +#define MAX_EXP 5.834617425e14 +#define MIN_EXP 1.713908431e-15 +#define EXP_THRESHOLD 34.0 +#define SMOOTHFACTOR 0.1 +#define EPSOX 3.453133e-11 +#define EPSSI 1.03594e-10 +#define PI 3.141592654 +#define Charge_q 1.60219e-19 +#define Meter2Micron 1.0e6 + +int +BSIM3v1Asetup(SMPmatrix *matrix, GENmodel *inModel, CKTcircuit *ckt, + int *states) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; +int error; +CKTnode *tmp; + +double tmp1, tmp2; + +CKTnode *tmpNode; +IFuid tmpName; + + /* loop through all the BSIM3v1A device models */ + for( ; model != NULL; model = model->BSIM3v1AnextModel ) + { +/* Default value Processing for BSIM3v1A MOSFET Models */ + if (!model->BSIM3v1AtypeGiven) + model->BSIM3v1Atype = NMOS; + if (!model->BSIM3v1AmobModGiven) + model->BSIM3v1AmobMod = 1; + if (!model->BSIM3v1AbinUnitGiven) + model->BSIM3v1AbinUnit = 1; + if (!model->BSIM3v1AcapModGiven) + model->BSIM3v1AcapMod = 1; + if (!model->BSIM3v1AnqsModGiven) + model->BSIM3v1AnqsMod = 0; + if (!model->BSIM3v1AnoiModGiven) + model->BSIM3v1AnoiMod = 1; + if (!model->BSIM3v1AtoxGiven) + model->BSIM3v1Atox = 150.0e-10; + model->BSIM3v1Acox = 3.453133e-11 / model->BSIM3v1Atox; + + if (!model->BSIM3v1AcdscGiven) + model->BSIM3v1Acdsc = 2.4e-4; /* unit Q/V/m^2 */ + if (!model->BSIM3v1AcdscbGiven) + model->BSIM3v1Acdscb = 0.0; /* unit Q/V/m^2 */ + if (!model->BSIM3v1AcdscdGiven) + model->BSIM3v1Acdscd = 0.0; /* unit Q/V/m^2 */ + if (!model->BSIM3v1AcitGiven) + model->BSIM3v1Acit = 0.0; /* unit Q/V/m^2 */ + if (!model->BSIM3v1AnfactorGiven) + model->BSIM3v1Anfactor = 1; + if (!model->BSIM3v1AxjGiven) + model->BSIM3v1Axj = .15e-6; + if (!model->BSIM3v1AvsatGiven) + model->BSIM3v1Avsat = 8.0e4; /* unit m/s */ + if (!model->BSIM3v1AatGiven) + model->BSIM3v1Aat = 3.3e4; /* unit m/s */ + if (!model->BSIM3v1Aa0Given) + model->BSIM3v1Aa0 = 1.0; + if (!model->BSIM3v1AagsGiven) + model->BSIM3v1Aags = 0.0; + if (!model->BSIM3v1Aa1Given) + model->BSIM3v1Aa1 = 0.0; + if (!model->BSIM3v1Aa2Given) + model->BSIM3v1Aa2 = 1.0; + if (!model->BSIM3v1AketaGiven) + model->BSIM3v1Aketa = -0.047; /* unit / V */ + if (!model->BSIM3v1AnsubGiven) + model->BSIM3v1Ansub = 6.0e16; /* unit 1/cm3 */ + if (!model->BSIM3v1AnpeakGiven) + model->BSIM3v1Anpeak = 1.7e17; /* unit 1/cm3 */ + if (!model->BSIM3v1AvbmGiven) + model->BSIM3v1Avbm = -5.0; + if (!model->BSIM3v1AxtGiven) + model->BSIM3v1Axt = 1.55e-7; + if (!model->BSIM3v1Akt1Given) + model->BSIM3v1Akt1 = -0.11; /* unit V */ + if (!model->BSIM3v1Akt1lGiven) + model->BSIM3v1Akt1l = 0.0; /* unit V*m */ + if (!model->BSIM3v1Akt2Given) + model->BSIM3v1Akt2 = 0.022; /* No unit */ + if (!model->BSIM3v1Ak3Given) + model->BSIM3v1Ak3 = 80.0; + if (!model->BSIM3v1Ak3bGiven) + model->BSIM3v1Ak3b = 0.0; + if (!model->BSIM3v1Aw0Given) + model->BSIM3v1Aw0 = 2.5e-6; + if (!model->BSIM3v1AnlxGiven) + model->BSIM3v1Anlx = 1.74e-7; + if (!model->BSIM3v1Advt0Given) + model->BSIM3v1Advt0 = 2.2; + if (!model->BSIM3v1Advt1Given) + model->BSIM3v1Advt1 = 0.53; + if (!model->BSIM3v1Advt2Given) + model->BSIM3v1Advt2 = -0.032; /* unit 1 / V */ + + if (!model->BSIM3v1Advt0wGiven) + model->BSIM3v1Advt0w = 0.0; + if (!model->BSIM3v1Advt1wGiven) + model->BSIM3v1Advt1w = 5.3e6; + if (!model->BSIM3v1Advt2wGiven) + model->BSIM3v1Advt2w = -0.032; + + if (!model->BSIM3v1AdroutGiven) + model->BSIM3v1Adrout = 0.56; + if (!model->BSIM3v1AdsubGiven) + model->BSIM3v1Adsub = model->BSIM3v1Adrout; + if (!model->BSIM3v1Avth0Given) + model->BSIM3v1Avth0 = (model->BSIM3v1Atype == NMOS) ? 0.7 : -0.7; + if (!model->BSIM3v1AuaGiven) + model->BSIM3v1Aua = 2.25e-9; /* unit m/V */ + if (!model->BSIM3v1Aua1Given) + model->BSIM3v1Aua1 = 4.31e-9; /* unit m/V */ + if (!model->BSIM3v1AubGiven) + model->BSIM3v1Aub = 5.87e-19; /* unit (m/V)**2 */ + if (!model->BSIM3v1Aub1Given) + model->BSIM3v1Aub1 = -7.61e-18; /* unit (m/V)**2 */ + if (!model->BSIM3v1AucGiven) + model->BSIM3v1Auc = (model->BSIM3v1AmobMod == 3) ? -0.0465 : -0.0465e-9; + if (!model->BSIM3v1Auc1Given) + model->BSIM3v1Auc1 = (model->BSIM3v1AmobMod == 3) ? -0.056 : -0.056e-9; + if (!model->BSIM3v1Au0Given) + model->BSIM3v1Au0 = (model->BSIM3v1Atype == NMOS) ? 0.067 : 0.025; + else if (model->BSIM3v1Au0 > 1.0) + model->BSIM3v1Au0 = model->BSIM3v1Au0 / 1.0e4; + /* if u0 > 1.0, cm.g.sec unit system is used. If should be + converted into SI unit system. */ + if (!model->BSIM3v1AuteGiven) + model->BSIM3v1Aute = -1.5; + if (!model->BSIM3v1AvoffGiven) + model->BSIM3v1Avoff = -0.08; + if (!model->BSIM3v1AdeltaGiven) + model->BSIM3v1Adelta = 0.01; + if (!model->BSIM3v1ArdswGiven) + model->BSIM3v1Ardsw = 0; + if (!model->BSIM3v1AprwgGiven) + model->BSIM3v1Aprwg = 0.0; /* unit 1/V */ + if (!model->BSIM3v1AprwbGiven) + model->BSIM3v1Aprwb = 0.0; + if (!model->BSIM3v1AprtGiven) + if (!model->BSIM3v1AprtGiven) + model->BSIM3v1Aprt = 0.0; + if (!model->BSIM3v1Aeta0Given) + model->BSIM3v1Aeta0 = 0.08; /* no unit */ + if (!model->BSIM3v1AetabGiven) + model->BSIM3v1Aetab = -0.07; /* unit 1/V */ + if (!model->BSIM3v1ApclmGiven) + model->BSIM3v1Apclm = 1.3; /* no unit */ + if (!model->BSIM3v1Apdibl1Given) + model->BSIM3v1Apdibl1 = .39; /* no unit */ + if (!model->BSIM3v1Apdibl2Given) + model->BSIM3v1Apdibl2 = 0.0086; /* no unit */ + if (!model->BSIM3v1ApdiblbGiven) + model->BSIM3v1Apdiblb = 0.0; /* 1/V */ + if (!model->BSIM3v1Apscbe1Given) + model->BSIM3v1Apscbe1 = 4.24e8; + if (!model->BSIM3v1Apscbe2Given) + model->BSIM3v1Apscbe2 = 1.0e-5; + if (!model->BSIM3v1ApvagGiven) + model->BSIM3v1Apvag = 0.0; + if (!model->BSIM3v1AwrGiven) + model->BSIM3v1Awr = 1.0; + if (!model->BSIM3v1AdwgGiven) + model->BSIM3v1Adwg = 0.0; + if (!model->BSIM3v1AdwbGiven) + model->BSIM3v1Adwb = 0.0; + if (!model->BSIM3v1Ab0Given) + model->BSIM3v1Ab0 = 0.0; + if (!model->BSIM3v1Ab1Given) + model->BSIM3v1Ab1 = 0.0; + if (!model->BSIM3v1Aalpha0Given) + model->BSIM3v1Aalpha0 = 0.0; + if (!model->BSIM3v1Abeta0Given) + model->BSIM3v1Abeta0 = 30.0; + + if (!model->BSIM3v1AelmGiven) + model->BSIM3v1Aelm = 5.0; + if (!model->BSIM3v1AcgslGiven) + model->BSIM3v1Acgsl = 0.0; + if (!model->BSIM3v1AcgdlGiven) + model->BSIM3v1Acgdl = 0.0; + if (!model->BSIM3v1AckappaGiven) + model->BSIM3v1Ackappa = 0.6; + if (!model->BSIM3v1AclcGiven) + model->BSIM3v1Aclc = 0.1e-6; + if (!model->BSIM3v1AcleGiven) + model->BSIM3v1Acle = 0.6; + + /* Length dependence */ + if (!model->BSIM3v1AlcdscGiven) + model->BSIM3v1Alcdsc = 0.0; + if (!model->BSIM3v1AlcdscbGiven) + model->BSIM3v1Alcdscb = 0.0; + if (!model->BSIM3v1AlcdscdGiven) + model->BSIM3v1Alcdscd = 0.0; + if (!model->BSIM3v1AlcitGiven) + model->BSIM3v1Alcit = 0.0; + if (!model->BSIM3v1AlnfactorGiven) + model->BSIM3v1Alnfactor = 0.0; + if (!model->BSIM3v1AlxjGiven) + model->BSIM3v1Alxj = 0.0; + if (!model->BSIM3v1AlvsatGiven) + model->BSIM3v1Alvsat = 0.0; + if (!model->BSIM3v1AlatGiven) + model->BSIM3v1Alat = 0.0; + if (!model->BSIM3v1Ala0Given) + model->BSIM3v1Ala0 = 0.0; + if (!model->BSIM3v1AlagsGiven) + model->BSIM3v1Alags = 0.0; + if (!model->BSIM3v1Ala1Given) + model->BSIM3v1Ala1 = 0.0; + if (!model->BSIM3v1Ala2Given) + model->BSIM3v1Ala2 = 0.0; + if (!model->BSIM3v1AlketaGiven) + model->BSIM3v1Alketa = 0.0; + if (!model->BSIM3v1AlnsubGiven) + model->BSIM3v1Alnsub = 0.0; + if (!model->BSIM3v1AlnpeakGiven) + model->BSIM3v1Alnpeak = 0.0; + if (!model->BSIM3v1AlvbmGiven) + model->BSIM3v1Alvbm = 0.0; + if (!model->BSIM3v1AlxtGiven) + model->BSIM3v1Alxt = 0.0; + if (!model->BSIM3v1Alkt1Given) + model->BSIM3v1Alkt1 = 0.0; + if (!model->BSIM3v1Alkt1lGiven) + model->BSIM3v1Alkt1l = 0.0; + if (!model->BSIM3v1Alkt2Given) + model->BSIM3v1Alkt2 = 0.0; + if (!model->BSIM3v1Alk3Given) + model->BSIM3v1Alk3 = 0.0; + if (!model->BSIM3v1Alk3bGiven) + model->BSIM3v1Alk3b = 0.0; + if (!model->BSIM3v1Alw0Given) + model->BSIM3v1Alw0 = 0.0; + if (!model->BSIM3v1AlnlxGiven) + model->BSIM3v1Alnlx = 0.0; + if (!model->BSIM3v1Aldvt0Given) + model->BSIM3v1Aldvt0 = 0.0; + if (!model->BSIM3v1Aldvt1Given) + model->BSIM3v1Aldvt1 = 0.0; + if (!model->BSIM3v1Aldvt2Given) + model->BSIM3v1Aldvt2 = 0.0; + if (!model->BSIM3v1Aldvt0wGiven) + model->BSIM3v1Aldvt0w = 0.0; + if (!model->BSIM3v1Aldvt1wGiven) + model->BSIM3v1Aldvt1w = 0.0; + if (!model->BSIM3v1Aldvt2wGiven) + model->BSIM3v1Aldvt2w = 0.0; + if (!model->BSIM3v1AldroutGiven) + model->BSIM3v1Aldrout = 0.0; + if (!model->BSIM3v1AldsubGiven) + model->BSIM3v1Aldsub = 0.0; + if (!model->BSIM3v1Alvth0Given) + model->BSIM3v1Alvth0 = 0.0; + if (!model->BSIM3v1AluaGiven) + model->BSIM3v1Alua = 0.0; + if (!model->BSIM3v1Alua1Given) + model->BSIM3v1Alua1 = 0.0; + if (!model->BSIM3v1AlubGiven) + model->BSIM3v1Alub = 0.0; + if (!model->BSIM3v1Alub1Given) + model->BSIM3v1Alub1 = 0.0; + if (!model->BSIM3v1AlucGiven) + model->BSIM3v1Aluc = 0.0; + if (!model->BSIM3v1Aluc1Given) + model->BSIM3v1Aluc1 = 0.0; + if (!model->BSIM3v1Alu0Given) + model->BSIM3v1Alu0 = 0.0; + else if (model->BSIM3v1Au0 > 1.0) + model->BSIM3v1Alu0 = model->BSIM3v1Alu0 / 1.0e4; + if (!model->BSIM3v1AluteGiven) + model->BSIM3v1Alute = 0.0; + if (!model->BSIM3v1AlvoffGiven) + model->BSIM3v1Alvoff = 0.0; + if (!model->BSIM3v1AldeltaGiven) + model->BSIM3v1Aldelta = 0.0; + if (!model->BSIM3v1AlrdswGiven) + model->BSIM3v1Alrdsw = 0.0; + if (!model->BSIM3v1AlprwbGiven) + model->BSIM3v1Alprwb = 0.0; + if (!model->BSIM3v1AlprwgGiven) + model->BSIM3v1Alprwg = 0.0; + if (!model->BSIM3v1AlprtGiven) + if (!model->BSIM3v1AlprtGiven) + model->BSIM3v1Alprt = 0.0; + if (!model->BSIM3v1Aleta0Given) + model->BSIM3v1Aleta0 = 0.0; + if (!model->BSIM3v1AletabGiven) + model->BSIM3v1Aletab = -0.0; + if (!model->BSIM3v1AlpclmGiven) + model->BSIM3v1Alpclm = 0.0; + if (!model->BSIM3v1Alpdibl1Given) + model->BSIM3v1Alpdibl1 = 0.0; + if (!model->BSIM3v1Alpdibl2Given) + model->BSIM3v1Alpdibl2 = 0.0; + if (!model->BSIM3v1AlpdiblbGiven) + model->BSIM3v1Alpdiblb = 0.0; + if (!model->BSIM3v1Alpscbe1Given) + model->BSIM3v1Alpscbe1 = 0.0; + if (!model->BSIM3v1Alpscbe2Given) + model->BSIM3v1Alpscbe2 = 0.0; + if (!model->BSIM3v1AlpvagGiven) + model->BSIM3v1Alpvag = 0.0; + if (!model->BSIM3v1AlwrGiven) + model->BSIM3v1Alwr = 0.0; + if (!model->BSIM3v1AldwgGiven) + model->BSIM3v1Aldwg = 0.0; + if (!model->BSIM3v1AldwbGiven) + model->BSIM3v1Aldwb = 0.0; + if (!model->BSIM3v1Alb0Given) + model->BSIM3v1Alb0 = 0.0; + if (!model->BSIM3v1Alb1Given) + model->BSIM3v1Alb1 = 0.0; + if (!model->BSIM3v1Alalpha0Given) + model->BSIM3v1Alalpha0 = 0.0; + if (!model->BSIM3v1Albeta0Given) + model->BSIM3v1Albeta0 = 0.0; + + if (!model->BSIM3v1AlelmGiven) + model->BSIM3v1Alelm = 0.0; + if (!model->BSIM3v1AlcgslGiven) + model->BSIM3v1Alcgsl = 0.0; + if (!model->BSIM3v1AlcgdlGiven) + model->BSIM3v1Alcgdl = 0.0; + if (!model->BSIM3v1AlckappaGiven) + model->BSIM3v1Alckappa = 0.0; + if (!model->BSIM3v1AlcfGiven) + model->BSIM3v1Alcf = 0.0; + if (!model->BSIM3v1AlclcGiven) + model->BSIM3v1Alclc = 0.0; + if (!model->BSIM3v1AlcleGiven) + model->BSIM3v1Alcle = 0.0; + + /* Width dependence */ + if (!model->BSIM3v1AwcdscGiven) + model->BSIM3v1Awcdsc = 0.0; + if (!model->BSIM3v1AwcdscbGiven) + model->BSIM3v1Awcdscb = 0.0; + if (!model->BSIM3v1AwcdscdGiven) + model->BSIM3v1Awcdscd = 0.0; + if (!model->BSIM3v1AwcitGiven) + model->BSIM3v1Awcit = 0.0; + if (!model->BSIM3v1AwnfactorGiven) + model->BSIM3v1Awnfactor = 0.0; + if (!model->BSIM3v1AwxjGiven) + model->BSIM3v1Awxj = 0.0; + if (!model->BSIM3v1AwvsatGiven) + model->BSIM3v1Awvsat = 0.0; + if (!model->BSIM3v1AwatGiven) + model->BSIM3v1Awat = 0.0; + if (!model->BSIM3v1Awa0Given) + model->BSIM3v1Awa0 = 0.0; + if (!model->BSIM3v1AwagsGiven) + model->BSIM3v1Awags = 0.0; + if (!model->BSIM3v1Awa1Given) + model->BSIM3v1Awa1 = 0.0; + if (!model->BSIM3v1Awa2Given) + model->BSIM3v1Awa2 = 0.0; + if (!model->BSIM3v1AwketaGiven) + model->BSIM3v1Awketa = 0.0; + if (!model->BSIM3v1AwnsubGiven) + model->BSIM3v1Awnsub = 0.0; + if (!model->BSIM3v1AwnpeakGiven) + model->BSIM3v1Awnpeak = 0.0; + if (!model->BSIM3v1AwvbmGiven) + model->BSIM3v1Awvbm = 0.0; + if (!model->BSIM3v1AwxtGiven) + model->BSIM3v1Awxt = 0.0; + if (!model->BSIM3v1Awkt1Given) + model->BSIM3v1Awkt1 = 0.0; + if (!model->BSIM3v1Awkt1lGiven) + model->BSIM3v1Awkt1l = 0.0; + if (!model->BSIM3v1Awkt2Given) + model->BSIM3v1Awkt2 = 0.0; + if (!model->BSIM3v1Awk3Given) + model->BSIM3v1Awk3 = 0.0; + if (!model->BSIM3v1Awk3bGiven) + model->BSIM3v1Awk3b = 0.0; + if (!model->BSIM3v1Aww0Given) + model->BSIM3v1Aww0 = 0.0; + if (!model->BSIM3v1AwnlxGiven) + model->BSIM3v1Awnlx = 0.0; + if (!model->BSIM3v1Awdvt0Given) + model->BSIM3v1Awdvt0 = 0.0; + if (!model->BSIM3v1Awdvt1Given) + model->BSIM3v1Awdvt1 = 0.0; + if (!model->BSIM3v1Awdvt2Given) + model->BSIM3v1Awdvt2 = 0.0; + if (!model->BSIM3v1Awdvt0wGiven) + model->BSIM3v1Awdvt0w = 0.0; + if (!model->BSIM3v1Awdvt1wGiven) + model->BSIM3v1Awdvt1w = 0.0; + if (!model->BSIM3v1Awdvt2wGiven) + model->BSIM3v1Awdvt2w = 0.0; + if (!model->BSIM3v1AwdroutGiven) + model->BSIM3v1Awdrout = 0.0; + if (!model->BSIM3v1AwdsubGiven) + model->BSIM3v1Awdsub = 0.0; + if (!model->BSIM3v1Awvth0Given) + model->BSIM3v1Awvth0 = 0.0; + if (!model->BSIM3v1AwuaGiven) + model->BSIM3v1Awua = 0.0; + if (!model->BSIM3v1Awua1Given) + model->BSIM3v1Awua1 = 0.0; + if (!model->BSIM3v1AwubGiven) + model->BSIM3v1Awub = 0.0; + if (!model->BSIM3v1Awub1Given) + model->BSIM3v1Awub1 = 0.0; + if (!model->BSIM3v1AwucGiven) + model->BSIM3v1Awuc = 0.0; + if (!model->BSIM3v1Awuc1Given) + model->BSIM3v1Awuc1 = 0.0; + if (!model->BSIM3v1Awu0Given) + model->BSIM3v1Awu0 = 0.0; + else if (model->BSIM3v1Au0 > 1.0) + model->BSIM3v1Awu0 = model->BSIM3v1Awu0 / 1.0e4; + if (!model->BSIM3v1AwuteGiven) + model->BSIM3v1Awute = 0.0; + if (!model->BSIM3v1AwvoffGiven) + model->BSIM3v1Awvoff = 0.0; + if (!model->BSIM3v1AwdeltaGiven) + model->BSIM3v1Awdelta = 0.0; + if (!model->BSIM3v1AwrdswGiven) + model->BSIM3v1Awrdsw = 0.0; + if (!model->BSIM3v1AwprwbGiven) + model->BSIM3v1Awprwb = 0.0; + if (!model->BSIM3v1AwprwgGiven) + model->BSIM3v1Awprwg = 0.0; + if (!model->BSIM3v1AwprtGiven) + model->BSIM3v1Awprt = 0.0; + if (!model->BSIM3v1Aweta0Given) + model->BSIM3v1Aweta0 = 0.0; + if (!model->BSIM3v1AwetabGiven) + model->BSIM3v1Awetab = 0.0; + if (!model->BSIM3v1AwpclmGiven) + model->BSIM3v1Awpclm = 0.0; + if (!model->BSIM3v1Awpdibl1Given) + model->BSIM3v1Awpdibl1 = 0.0; + if (!model->BSIM3v1Awpdibl2Given) + model->BSIM3v1Awpdibl2 = 0.0; + if (!model->BSIM3v1AwpdiblbGiven) + model->BSIM3v1Awpdiblb = 0.0; + if (!model->BSIM3v1Awpscbe1Given) + model->BSIM3v1Awpscbe1 = 0.0; + if (!model->BSIM3v1Awpscbe2Given) + model->BSIM3v1Awpscbe2 = 0.0; + if (!model->BSIM3v1AwpvagGiven) + model->BSIM3v1Awpvag = 0.0; + if (!model->BSIM3v1AwwrGiven) + model->BSIM3v1Awwr = 0.0; + if (!model->BSIM3v1AwdwgGiven) + model->BSIM3v1Awdwg = 0.0; + if (!model->BSIM3v1AwdwbGiven) + model->BSIM3v1Awdwb = 0.0; + if (!model->BSIM3v1Awb0Given) + model->BSIM3v1Awb0 = 0.0; + if (!model->BSIM3v1Awb1Given) + model->BSIM3v1Awb1 = 0.0; + if (!model->BSIM3v1Awalpha0Given) + model->BSIM3v1Awalpha0 = 0.0; + if (!model->BSIM3v1Awbeta0Given) + model->BSIM3v1Awbeta0 = 0.0; + + if (!model->BSIM3v1AwelmGiven) + model->BSIM3v1Awelm = 0.0; + if (!model->BSIM3v1AwcgslGiven) + model->BSIM3v1Awcgsl = 0.0; + if (!model->BSIM3v1AwcgdlGiven) + model->BSIM3v1Awcgdl = 0.0; + if (!model->BSIM3v1AwckappaGiven) + model->BSIM3v1Awckappa = 0.0; + if (!model->BSIM3v1AwcfGiven) + model->BSIM3v1Awcf = 0.0; + if (!model->BSIM3v1AwclcGiven) + model->BSIM3v1Awclc = 0.0; + if (!model->BSIM3v1AwcleGiven) + model->BSIM3v1Awcle = 0.0; + + /* Cross-term dependence */ + if (!model->BSIM3v1ApcdscGiven) + model->BSIM3v1Apcdsc = 0.0; + if (!model->BSIM3v1ApcdscbGiven) + model->BSIM3v1Apcdscb = 0.0; + if (!model->BSIM3v1ApcdscdGiven) + model->BSIM3v1Apcdscd = 0.0; + if (!model->BSIM3v1ApcitGiven) + model->BSIM3v1Apcit = 0.0; + if (!model->BSIM3v1ApnfactorGiven) + model->BSIM3v1Apnfactor = 0.0; + if (!model->BSIM3v1ApxjGiven) + model->BSIM3v1Apxj = 0.0; + if (!model->BSIM3v1ApvsatGiven) + model->BSIM3v1Apvsat = 0.0; + if (!model->BSIM3v1ApatGiven) + model->BSIM3v1Apat = 0.0; + if (!model->BSIM3v1Apa0Given) + model->BSIM3v1Apa0 = 0.0; + + if (!model->BSIM3v1ApagsGiven) + model->BSIM3v1Apags = 0.0; + if (!model->BSIM3v1Apa1Given) + model->BSIM3v1Apa1 = 0.0; + if (!model->BSIM3v1Apa2Given) + model->BSIM3v1Apa2 = 0.0; + if (!model->BSIM3v1ApketaGiven) + model->BSIM3v1Apketa = 0.0; + if (!model->BSIM3v1ApnsubGiven) + model->BSIM3v1Apnsub = 0.0; + if (!model->BSIM3v1ApnpeakGiven) + model->BSIM3v1Apnpeak = 0.0; + if (!model->BSIM3v1ApvbmGiven) + model->BSIM3v1Apvbm = 0.0; + if (!model->BSIM3v1ApxtGiven) + model->BSIM3v1Apxt = 0.0; + if (!model->BSIM3v1Apkt1Given) + model->BSIM3v1Apkt1 = 0.0; + if (!model->BSIM3v1Apkt1lGiven) + model->BSIM3v1Apkt1l = 0.0; + if (!model->BSIM3v1Apkt2Given) + model->BSIM3v1Apkt2 = 0.0; + if (!model->BSIM3v1Apk3Given) + model->BSIM3v1Apk3 = 0.0; + if (!model->BSIM3v1Apk3bGiven) + model->BSIM3v1Apk3b = 0.0; + if (!model->BSIM3v1Apw0Given) + model->BSIM3v1Apw0 = 0.0; + if (!model->BSIM3v1ApnlxGiven) + model->BSIM3v1Apnlx = 0.0; + if (!model->BSIM3v1Apdvt0Given) + model->BSIM3v1Apdvt0 = 0.0; + if (!model->BSIM3v1Apdvt1Given) + model->BSIM3v1Apdvt1 = 0.0; + if (!model->BSIM3v1Apdvt2Given) + model->BSIM3v1Apdvt2 = 0.0; + if (!model->BSIM3v1Apdvt0wGiven) + model->BSIM3v1Apdvt0w = 0.0; + if (!model->BSIM3v1Apdvt1wGiven) + model->BSIM3v1Apdvt1w = 0.0; + if (!model->BSIM3v1Apdvt2wGiven) + model->BSIM3v1Apdvt2w = 0.0; + if (!model->BSIM3v1ApdroutGiven) + model->BSIM3v1Apdrout = 0.0; + if (!model->BSIM3v1ApdsubGiven) + model->BSIM3v1Apdsub = 0.0; + if (!model->BSIM3v1Apvth0Given) + model->BSIM3v1Apvth0 = 0.0; + if (!model->BSIM3v1ApuaGiven) + model->BSIM3v1Apua = 0.0; + if (!model->BSIM3v1Apua1Given) + model->BSIM3v1Apua1 = 0.0; + if (!model->BSIM3v1ApubGiven) + model->BSIM3v1Apub = 0.0; + if (!model->BSIM3v1Apub1Given) + model->BSIM3v1Apub1 = 0.0; + if (!model->BSIM3v1ApucGiven) + model->BSIM3v1Apuc = 0.0; + if (!model->BSIM3v1Apuc1Given) + model->BSIM3v1Apuc1 = 0.0; + if (!model->BSIM3v1Apu0Given) + model->BSIM3v1Apu0 = 0.0; + else if (model->BSIM3v1Au0 > 1.0) + model->BSIM3v1Apu0 = model->BSIM3v1Apu0 / 1.0e4; + if (!model->BSIM3v1AputeGiven) + model->BSIM3v1Apute = 0.0; + if (!model->BSIM3v1ApvoffGiven) + model->BSIM3v1Apvoff = 0.0; + if (!model->BSIM3v1ApdeltaGiven) + model->BSIM3v1Apdelta = 0.0; + if (!model->BSIM3v1AprdswGiven) + model->BSIM3v1Aprdsw = 0.0; + if (!model->BSIM3v1ApprwbGiven) + model->BSIM3v1Apprwb = 0.0; + if (!model->BSIM3v1ApprwgGiven) + model->BSIM3v1Apprwg = 0.0; + if (!model->BSIM3v1ApprtGiven) + model->BSIM3v1Apprt = 0.0; + if (!model->BSIM3v1Apeta0Given) + model->BSIM3v1Apeta0 = 0.0; + if (!model->BSIM3v1ApetabGiven) + model->BSIM3v1Apetab = 0.0; + if (!model->BSIM3v1AppclmGiven) + model->BSIM3v1Appclm = 0.0; + if (!model->BSIM3v1Appdibl1Given) + model->BSIM3v1Appdibl1 = 0.0; + if (!model->BSIM3v1Appdibl2Given) + model->BSIM3v1Appdibl2 = 0.0; + if (!model->BSIM3v1AppdiblbGiven) + model->BSIM3v1Appdiblb = 0.0; + if (!model->BSIM3v1Appscbe1Given) + model->BSIM3v1Appscbe1 = 0.0; + if (!model->BSIM3v1Appscbe2Given) + model->BSIM3v1Appscbe2 = 0.0; + if (!model->BSIM3v1AppvagGiven) + model->BSIM3v1Appvag = 0.0; + if (!model->BSIM3v1ApwrGiven) + model->BSIM3v1Apwr = 0.0; + if (!model->BSIM3v1ApdwgGiven) + model->BSIM3v1Apdwg = 0.0; + if (!model->BSIM3v1ApdwbGiven) + model->BSIM3v1Apdwb = 0.0; + if (!model->BSIM3v1Apb0Given) + model->BSIM3v1Apb0 = 0.0; + if (!model->BSIM3v1Apb1Given) + model->BSIM3v1Apb1 = 0.0; + if (!model->BSIM3v1Apalpha0Given) + model->BSIM3v1Apalpha0 = 0.0; + if (!model->BSIM3v1Apbeta0Given) + model->BSIM3v1Apbeta0 = 0.0; + + if (!model->BSIM3v1ApelmGiven) + model->BSIM3v1Apelm = 0.0; + if (!model->BSIM3v1ApcgslGiven) + model->BSIM3v1Apcgsl = 0.0; + if (!model->BSIM3v1ApcgdlGiven) + model->BSIM3v1Apcgdl = 0.0; + if (!model->BSIM3v1ApckappaGiven) + model->BSIM3v1Apckappa = 0.0; + if (!model->BSIM3v1ApcfGiven) + model->BSIM3v1Apcf = 0.0; + if (!model->BSIM3v1ApclcGiven) + model->BSIM3v1Apclc = 0.0; + if (!model->BSIM3v1ApcleGiven) + model->BSIM3v1Apcle = 0.0; + + /* unit degree celcius */ + if (!model->BSIM3v1AtnomGiven) + model->BSIM3v1Atnom = ckt->CKTnomTemp; + if (!model->BSIM3v1ALintGiven) + model->BSIM3v1ALint = 0.0; + if (!model->BSIM3v1ALlGiven) + model->BSIM3v1ALl = 0.0; + if (!model->BSIM3v1ALlnGiven) + model->BSIM3v1ALln = 1.0; + if (!model->BSIM3v1ALwGiven) + model->BSIM3v1ALw = 0.0; + if (!model->BSIM3v1ALwnGiven) + model->BSIM3v1ALwn = 1.0; + if (!model->BSIM3v1ALwlGiven) + model->BSIM3v1ALwl = 0.0; + if (!model->BSIM3v1ALminGiven) + model->BSIM3v1ALmin = 0.0; + if (!model->BSIM3v1ALmaxGiven) + model->BSIM3v1ALmax = 1.0; + if (!model->BSIM3v1AWintGiven) + model->BSIM3v1AWint = 0.0; + if (!model->BSIM3v1AWlGiven) + model->BSIM3v1AWl = 0.0; + if (!model->BSIM3v1AWlnGiven) + model->BSIM3v1AWln = 1.0; + if (!model->BSIM3v1AWwGiven) + model->BSIM3v1AWw = 0.0; + if (!model->BSIM3v1AWwnGiven) + model->BSIM3v1AWwn = 1.0; + if (!model->BSIM3v1AWwlGiven) + model->BSIM3v1AWwl = 0.0; + if (!model->BSIM3v1AWminGiven) + model->BSIM3v1AWmin = 0.0; + if (!model->BSIM3v1AWmaxGiven) + model->BSIM3v1AWmax = 1.0; + if (!model->BSIM3v1AdwcGiven) + model->BSIM3v1Adwc = model->BSIM3v1AWint; + if (!model->BSIM3v1AdlcGiven) + model->BSIM3v1Adlc = model->BSIM3v1ALint; + if (!model->BSIM3v1AcfGiven) + model->BSIM3v1Acf = 2.0 * EPSOX / PI + * log(1.0 + 0.4e-6 / model->BSIM3v1Atox); + if (!model->BSIM3v1AcgdoGiven) + { if (model->BSIM3v1AdlcGiven && (model->BSIM3v1Adlc > 0.0)) + { model->BSIM3v1Acgdo = model->BSIM3v1Adlc * model->BSIM3v1Acox + - model->BSIM3v1Acgdl ; + if (model->BSIM3v1Acgdo < 0.0) + model->BSIM3v1Acgdo = 0.0; + } + else + model->BSIM3v1Acgdo = 0.6 * model->BSIM3v1Axj * model->BSIM3v1Acox; + } + if (!model->BSIM3v1AcgsoGiven) + { if (model->BSIM3v1AdlcGiven && (model->BSIM3v1Adlc > 0.0)) + { model->BSIM3v1Acgso = model->BSIM3v1Adlc * model->BSIM3v1Acox + - model->BSIM3v1Acgsl ; + if (model->BSIM3v1Acgso < 0.0) + model->BSIM3v1Acgso = 0.0; + } + else + model->BSIM3v1Acgso = 0.6 * model->BSIM3v1Axj * model->BSIM3v1Acox; + } + + if (!model->BSIM3v1AcgboGiven) + model->BSIM3v1Acgbo = 0.0; + if (!model->BSIM3v1AxpartGiven) + model->BSIM3v1Axpart = 0.0; + if (!model->BSIM3v1AsheetResistanceGiven) + model->BSIM3v1AsheetResistance = 0.0; + if (!model->BSIM3v1AunitAreaJctCapGiven) + model->BSIM3v1AunitAreaJctCap = 5.0E-4; + if (!model->BSIM3v1AunitLengthSidewallJctCapGiven) + model->BSIM3v1AunitLengthSidewallJctCap = 5.0E-10; + if (!model->BSIM3v1AjctSatCurDensityGiven) + model->BSIM3v1AjctSatCurDensity = 1.0E-4; + if (!model->BSIM3v1AbulkJctPotentialGiven) + model->BSIM3v1AbulkJctPotential = 1.0; + if (!model->BSIM3v1AsidewallJctPotentialGiven) + model->BSIM3v1AsidewallJctPotential = 1.0; + if (!model->BSIM3v1AbulkJctBotGradingCoeffGiven) + model->BSIM3v1AbulkJctBotGradingCoeff = 0.5; + if (!model->BSIM3v1AbulkJctSideGradingCoeffGiven) + model->BSIM3v1AbulkJctSideGradingCoeff = 0.33; + if (!model->BSIM3v1AoxideTrapDensityAGiven) + { if (model->BSIM3v1Atype == NMOS) + model->BSIM3v1AoxideTrapDensityA = 1e20; + else + model->BSIM3v1AoxideTrapDensityA=9.9e18; + } + if (!model->BSIM3v1AoxideTrapDensityBGiven) + { if (model->BSIM3v1Atype == NMOS) + model->BSIM3v1AoxideTrapDensityB = 5e4; + else + model->BSIM3v1AoxideTrapDensityB = 2.4e3; + } + if (!model->BSIM3v1AoxideTrapDensityCGiven) + { if (model->BSIM3v1Atype == NMOS) + model->BSIM3v1AoxideTrapDensityC = -1.4e-12; + else + model->BSIM3v1AoxideTrapDensityC = 1.4e-12; + + } + if (!model->BSIM3v1AemGiven) + model->BSIM3v1Aem = 4.1e7; /* V/m */ + if (!model->BSIM3v1AefGiven) + model->BSIM3v1Aef = 1.0; + if (!model->BSIM3v1AafGiven) + model->BSIM3v1Aaf = 1.0; + if (!model->BSIM3v1AkfGiven) + model->BSIM3v1Akf = 0.0; + /* loop through all the instances of the model */ + for (here = model->BSIM3v1Ainstances; here != NULL ; + here=here->BSIM3v1AnextInstance) + { + if (here->BSIM3v1Aowner == ARCHme) + { + /* allocate a chunk of the state vector */ + here->BSIM3v1Astates = *states; + *states += BSIM3v1AnumStates; + } + + + /* perform the parameter defaulting */ + if (!here->BSIM3v1AdrainAreaGiven) + here->BSIM3v1AdrainArea = 0.0; + if (!here->BSIM3v1AdrainPerimeterGiven) + here->BSIM3v1AdrainPerimeter = 0.0; + if (!here->BSIM3v1AdrainSquaresGiven) + here->BSIM3v1AdrainSquares = 1.0; + if (!here->BSIM3v1AicVBSGiven) + here->BSIM3v1AicVBS = 0; + if (!here->BSIM3v1AicVDSGiven) + here->BSIM3v1AicVDS = 0; + if (!here->BSIM3v1AicVGSGiven) + here->BSIM3v1AicVGS = 0; + if (!here->BSIM3v1AlGiven) + here->BSIM3v1Al = 5e-6; + if (!here->BSIM3v1AsourceAreaGiven) + here->BSIM3v1AsourceArea = 0; + if (!here->BSIM3v1AsourcePerimeterGiven) + here->BSIM3v1AsourcePerimeter = 0; + if (!here->BSIM3v1AsourceSquaresGiven) + here->BSIM3v1AsourceSquares = 1; + if (!here->BSIM3v1AwGiven) + here->BSIM3v1Aw = 5e-6; + + if (!here->BSIM3v1AmGiven) + here->BSIM3v1Am = 1; + + if (!here->BSIM3v1AnqsModGiven) + here->BSIM3v1AnqsMod = model->BSIM3v1AnqsMod; + + /* process drain series resistance */ + if ((model->BSIM3v1AsheetResistance > 0.0) && + (here->BSIM3v1AdrainSquares > 0.0 ) && + (here->BSIM3v1AdNodePrime == 0)) + { error = CKTmkVolt(ckt,&tmp,here->BSIM3v1Aname,"drain"); + if(error) return(error); + here->BSIM3v1AdNodePrime = tmp->number; + + if (ckt->CKTcopyNodesets) { + if (CKTinst2Node(ckt,here,1,&tmpNode,&tmpName)==OK) { + if (tmpNode->nsGiven) { + tmp->nodeset=tmpNode->nodeset; + tmp->nsGiven=tmpNode->nsGiven; + } + } + } + + } + else + { here->BSIM3v1AdNodePrime = here->BSIM3v1AdNode; + } + + /* process source series resistance */ + if ((model->BSIM3v1AsheetResistance > 0.0) && + (here->BSIM3v1AsourceSquares > 0.0 ) && + (here->BSIM3v1AsNodePrime == 0)) + { error = CKTmkVolt(ckt,&tmp,here->BSIM3v1Aname,"source"); + if(error) return(error); + here->BSIM3v1AsNodePrime = tmp->number; + + if (ckt->CKTcopyNodesets) { + if (CKTinst2Node(ckt,here,3,&tmpNode,&tmpName)==OK) { + if (tmpNode->nsGiven) { + tmp->nodeset=tmpNode->nodeset; + tmp->nsGiven=tmpNode->nsGiven; + } + } + } + + } + else + { here->BSIM3v1AsNodePrime = here->BSIM3v1AsNode; + } + + /* internal charge node */ + + if ((here->BSIM3v1AnqsMod) && (here->BSIM3v1AqNode == 0)) + { error = CKTmkVolt(ckt,&tmp,here->BSIM3v1Aname,"charge"); + if(error) return(error); + here->BSIM3v1AqNode = tmp->number; + } + else + { here->BSIM3v1AqNode = 0; + } + + /* set Sparse Matrix Pointers */ + +/* macro to make elements with built in test for out of memory */ +#define TSTALLOC(ptr,first,second) \ +if((here->ptr = SMPmakeElt(matrix,here->first,here->second))==(double *)NULL){\ + return(E_NOMEM);\ +} + + TSTALLOC(BSIM3v1ADdPtr, BSIM3v1AdNode, BSIM3v1AdNode) + TSTALLOC(BSIM3v1AGgPtr, BSIM3v1AgNode, BSIM3v1AgNode) + TSTALLOC(BSIM3v1ASsPtr, BSIM3v1AsNode, BSIM3v1AsNode) + TSTALLOC(BSIM3v1ABbPtr, BSIM3v1AbNode, BSIM3v1AbNode) + TSTALLOC(BSIM3v1ADPdpPtr, BSIM3v1AdNodePrime, BSIM3v1AdNodePrime) + TSTALLOC(BSIM3v1ASPspPtr, BSIM3v1AsNodePrime, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1ADdpPtr, BSIM3v1AdNode, BSIM3v1AdNodePrime) + TSTALLOC(BSIM3v1AGbPtr, BSIM3v1AgNode, BSIM3v1AbNode) + TSTALLOC(BSIM3v1AGdpPtr, BSIM3v1AgNode, BSIM3v1AdNodePrime) + TSTALLOC(BSIM3v1AGspPtr, BSIM3v1AgNode, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1ASspPtr, BSIM3v1AsNode, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1ABdpPtr, BSIM3v1AbNode, BSIM3v1AdNodePrime) + TSTALLOC(BSIM3v1ABspPtr, BSIM3v1AbNode, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1ADPspPtr, BSIM3v1AdNodePrime, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1ADPdPtr, BSIM3v1AdNodePrime, BSIM3v1AdNode) + TSTALLOC(BSIM3v1ABgPtr, BSIM3v1AbNode, BSIM3v1AgNode) + TSTALLOC(BSIM3v1ADPgPtr, BSIM3v1AdNodePrime, BSIM3v1AgNode) + TSTALLOC(BSIM3v1ASPgPtr, BSIM3v1AsNodePrime, BSIM3v1AgNode) + TSTALLOC(BSIM3v1ASPsPtr, BSIM3v1AsNodePrime, BSIM3v1AsNode) + TSTALLOC(BSIM3v1ADPbPtr, BSIM3v1AdNodePrime, BSIM3v1AbNode) + TSTALLOC(BSIM3v1ASPbPtr, BSIM3v1AsNodePrime, BSIM3v1AbNode) + TSTALLOC(BSIM3v1ASPdpPtr, BSIM3v1AsNodePrime, BSIM3v1AdNodePrime) + + TSTALLOC(BSIM3v1AQqPtr, BSIM3v1AqNode, BSIM3v1AqNode) + + TSTALLOC(BSIM3v1AQdpPtr, BSIM3v1AqNode, BSIM3v1AdNodePrime) + TSTALLOC(BSIM3v1AQspPtr, BSIM3v1AqNode, BSIM3v1AsNodePrime) + TSTALLOC(BSIM3v1AQgPtr, BSIM3v1AqNode, BSIM3v1AgNode) + TSTALLOC(BSIM3v1AQbPtr, BSIM3v1AqNode, BSIM3v1AbNode) + TSTALLOC(BSIM3v1ADPqPtr, BSIM3v1AdNodePrime, BSIM3v1AqNode) + TSTALLOC(BSIM3v1ASPqPtr, BSIM3v1AsNodePrime, BSIM3v1AqNode) + TSTALLOC(BSIM3v1AGqPtr, BSIM3v1AgNode, BSIM3v1AqNode) + TSTALLOC(BSIM3v1ABqPtr, BSIM3v1AbNode, BSIM3v1AqNode) + + } + } + return(OK); +} + + +int +BSIM3v1Aunsetup(GENmodel *inModel, CKTcircuit *ckt) +{ + BSIM3v1Amodel *model; + BSIM3v1Ainstance *here; + + for (model = (BSIM3v1Amodel *)inModel; model != NULL; + model = model->BSIM3v1AnextModel) + { + for (here = model->BSIM3v1Ainstances; here != NULL; + here=here->BSIM3v1AnextInstance) + { + if (here->BSIM3v1AdNodePrime + && here->BSIM3v1AdNodePrime != here->BSIM3v1AdNode) + { + CKTdltNNum(ckt, here->BSIM3v1AdNodePrime); + here->BSIM3v1AdNodePrime = 0; + } + if (here->BSIM3v1AsNodePrime + && here->BSIM3v1AsNodePrime != here->BSIM3v1AsNode) + { + CKTdltNNum(ckt, here->BSIM3v1AsNodePrime); + here->BSIM3v1AsNodePrime = 0; + } + } + } + return OK; +} + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1atemp.c b/src/spicelib/devices/bsim3v1a/b3v1atemp.c new file mode 100644 index 000000000..b630dd4f7 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1atemp.c @@ -0,0 +1,632 @@ +/*********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1atemp.c +**********/ +/* Lmin, Lmax, Wmin, Wmax */ + +#include "ngspice.h" +#include "smpdefs.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "const.h" +#include "sperror.h" +#include "suffix.h" + +#define Kb 1.3806226e-23 +#define KboQ 8.617087e-5 /* Kb / q where q = 1.60219e-19 */ +#define EPSOX 3.453133e-11 +#define EPSSI 1.03594e-10 +#define PI 3.141592654 +#define MAX_EXP 5.834617425e14 +#define MIN_EXP 1.713908431e-15 +#define EXP_THRESHOLD 34.0 +#define Charge_q 1.60219e-19 + + +/* ARGSUSED */ +int +BSIM3v1Atemp(GENmodel *inModel, CKTcircuit *ckt) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*) inModel; +BSIM3v1Ainstance *here; +struct bsim3v1aSizeDependParam *pSizeDependParamKnot, *pLastKnot, *pParam; +double tmp, tmp1, tmp2, Eg, ni, T0, T1, T2, T3, T4, T5, Ldrn, Wdrn; +double Temp, TRatio, Inv_L, Inv_W, Inv_LW, Dw, Dl, Vtm0, Tnom; +int Size_Not_Found; + + /* loop through all the BSIM3v1A device models */ + for (; model != NULL; model = model->BSIM3v1AnextModel) + { Temp = ckt->CKTtemp; + if (model->BSIM3v1AbulkJctPotential < 0.1) + model->BSIM3v1AbulkJctPotential = 0.1; + if (model->BSIM3v1AsidewallJctPotential < 0.1) + model->BSIM3v1AsidewallJctPotential = 0.1; + model->pSizeDependParamKnot = NULL; + pLastKnot = NULL; + + Tnom = model->BSIM3v1Atnom; + TRatio = Temp / Tnom; + + /* loop through all the instances of the model */ + for (here = model->BSIM3v1Ainstances; here != NULL; + here=here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + + pSizeDependParamKnot = model->pSizeDependParamKnot; + Size_Not_Found = 1; + while ((pSizeDependParamKnot != NULL) && Size_Not_Found) + { if ((here->BSIM3v1Al == pSizeDependParamKnot->Length) + && (here->BSIM3v1Aw == pSizeDependParamKnot->Width)) + { Size_Not_Found = 0; + here->pParam = pSizeDependParamKnot; + } + else + { pLastKnot = pSizeDependParamKnot; + pSizeDependParamKnot = pSizeDependParamKnot->pNext; + } + } + + if (Size_Not_Found) + { pParam = (struct bsim3v1aSizeDependParam *)tmalloc( + sizeof(struct bsim3v1aSizeDependParam)); + if (pLastKnot == NULL) + model->pSizeDependParamKnot = pParam; + else + pLastKnot->pNext = pParam; + pParam->pNext = NULL; + here->pParam = pParam; + + Ldrn = here->BSIM3v1Al; + Wdrn = here->BSIM3v1Aw; + + T0 = pow(Ldrn, model->BSIM3v1ALln); + T1 = pow(Wdrn, model->BSIM3v1ALwn); + tmp1 = model->BSIM3v1ALl / T0 + model->BSIM3v1ALw / T1 + + model->BSIM3v1ALwl / (T0 * T1); + pParam->BSIM3v1Adl = model->BSIM3v1ALint + tmp1; + pParam->BSIM3v1Adlc = model->BSIM3v1Adlc + tmp1; + + T2 = pow(Ldrn, model->BSIM3v1AWln); + T3 = pow(Wdrn, model->BSIM3v1AWwn); + tmp2 = model->BSIM3v1AWl / T2 + model->BSIM3v1AWw / T3 + + model->BSIM3v1AWwl / (T2 * T3); + pParam->BSIM3v1Adw = model->BSIM3v1AWint + tmp2; + pParam->BSIM3v1Adwc = model->BSIM3v1Adwc + tmp2; + + pParam->BSIM3v1Aleff = here->BSIM3v1Al - 2.0 * pParam->BSIM3v1Adl; + if (pParam->BSIM3v1Aleff <= 0.0) + { IFuid namarray[2]; + namarray[0] = model->BSIM3v1AmodName; + namarray[1] = here->BSIM3v1Aname; + (*(SPfrontEnd->IFerror))(ERR_FATAL, + "BSIM3v1A: mosfet %s, model %s: Effective channel length <= 0", + namarray); + return(E_BADPARM); + } + + pParam->BSIM3v1Aweff = here->BSIM3v1Aw - 2.0 * pParam->BSIM3v1Adw; + if (pParam->BSIM3v1Aweff <= 0.0) + { IFuid namarray[2]; + namarray[0] = model->BSIM3v1AmodName; + namarray[1] = here->BSIM3v1Aname; + (*(SPfrontEnd->IFerror))(ERR_FATAL, + "BSIM3v1A: mosfet %s, model %s: Effective channel width <= 0", + namarray); + return(E_BADPARM); + } + + pParam->BSIM3v1AleffCV = here->BSIM3v1Al - 2.0 * pParam->BSIM3v1Adlc; + if (pParam->BSIM3v1AleffCV <= 0.0) + { IFuid namarray[2]; + namarray[0] = model->BSIM3v1AmodName; + namarray[1] = here->BSIM3v1Aname; + (*(SPfrontEnd->IFerror))(ERR_FATAL, + "BSIM3v1A: mosfet %s, model %s: Effective channel length for C-V <= 0", + namarray); + return(E_BADPARM); + } + + pParam->BSIM3v1AweffCV = here->BSIM3v1Aw - 2.0 * pParam->BSIM3v1Adwc; + if (pParam->BSIM3v1AweffCV <= 0.0) + { IFuid namarray[2]; + namarray[0] = model->BSIM3v1AmodName; + namarray[1] = here->BSIM3v1Aname; + (*(SPfrontEnd->IFerror))(ERR_FATAL, + "BSIM3v1A: mosfet %s, model %s: Effective channel width for C-V <= 0", + namarray); + return(E_BADPARM); + } + + model->BSIM3v1Avcrit = CONSTvt0 * log(CONSTvt0 + / (CONSTroot2 * 1.0e-14)); + model->BSIM3v1Afactor1 = sqrt(EPSSI / EPSOX * model->BSIM3v1Atox); + + + if (model->BSIM3v1AbinUnit == 1) + { Inv_L = 1.0e-6 / pParam->BSIM3v1Aleff; + Inv_W = 1.0e-6 / pParam->BSIM3v1Aweff; + Inv_LW = 1.0e-12 / (pParam->BSIM3v1Aleff + * pParam->BSIM3v1Aweff); + } + else + { Inv_L = 1.0 / pParam->BSIM3v1Aleff; + Inv_W = 1.0 / pParam->BSIM3v1Aweff; + Inv_LW = 1.0 / (pParam->BSIM3v1Aleff + * pParam->BSIM3v1Aweff); + } + pParam->BSIM3v1Acdsc = model->BSIM3v1Acdsc + + model->BSIM3v1Alcdsc * Inv_L + + model->BSIM3v1Awcdsc * Inv_W + + model->BSIM3v1Apcdsc * Inv_LW; + pParam->BSIM3v1Acdscb = model->BSIM3v1Acdscb + + model->BSIM3v1Alcdscb * Inv_L + + model->BSIM3v1Awcdscb * Inv_W + + model->BSIM3v1Apcdscb * Inv_LW; + + pParam->BSIM3v1Acdscd = model->BSIM3v1Acdscd + + model->BSIM3v1Alcdscd * Inv_L + + model->BSIM3v1Awcdscd * Inv_W + + model->BSIM3v1Apcdscd * Inv_LW; + + pParam->BSIM3v1Acit = model->BSIM3v1Acit + + model->BSIM3v1Alcit * Inv_L + + model->BSIM3v1Awcit * Inv_W + + model->BSIM3v1Apcit * Inv_LW; + pParam->BSIM3v1Anfactor = model->BSIM3v1Anfactor + + model->BSIM3v1Alnfactor * Inv_L + + model->BSIM3v1Awnfactor * Inv_W + + model->BSIM3v1Apnfactor * Inv_LW; + pParam->BSIM3v1Axj = model->BSIM3v1Axj + + model->BSIM3v1Alxj * Inv_L + + model->BSIM3v1Awxj * Inv_W + + model->BSIM3v1Apxj * Inv_LW; + pParam->BSIM3v1Avsat = model->BSIM3v1Avsat + + model->BSIM3v1Alvsat * Inv_L + + model->BSIM3v1Awvsat * Inv_W + + model->BSIM3v1Apvsat * Inv_LW; + pParam->BSIM3v1Aat = model->BSIM3v1Aat + + model->BSIM3v1Alat * Inv_L + + model->BSIM3v1Awat * Inv_W + + model->BSIM3v1Apat * Inv_LW; + pParam->BSIM3v1Aa0 = model->BSIM3v1Aa0 + + model->BSIM3v1Ala0 * Inv_L + + model->BSIM3v1Awa0 * Inv_W + + model->BSIM3v1Apa0 * Inv_LW; + + pParam->BSIM3v1Aags = model->BSIM3v1Aags + + model->BSIM3v1Alags * Inv_L + + model->BSIM3v1Awags * Inv_W + + model->BSIM3v1Apags * Inv_LW; + + pParam->BSIM3v1Aa1 = model->BSIM3v1Aa1 + + model->BSIM3v1Ala1 * Inv_L + + model->BSIM3v1Awa1 * Inv_W + + model->BSIM3v1Apa1 * Inv_LW; + pParam->BSIM3v1Aa2 = model->BSIM3v1Aa2 + + model->BSIM3v1Ala2 * Inv_L + + model->BSIM3v1Awa2 * Inv_W + + model->BSIM3v1Apa2 * Inv_LW; + pParam->BSIM3v1Aketa = model->BSIM3v1Aketa + + model->BSIM3v1Alketa * Inv_L + + model->BSIM3v1Awketa * Inv_W + + model->BSIM3v1Apketa * Inv_LW; + pParam->BSIM3v1Ansub = model->BSIM3v1Ansub + + model->BSIM3v1Alnsub * Inv_L + + model->BSIM3v1Awnsub * Inv_W + + model->BSIM3v1Apnsub * Inv_LW; + pParam->BSIM3v1Anpeak = model->BSIM3v1Anpeak + + model->BSIM3v1Alnpeak * Inv_L + + model->BSIM3v1Awnpeak * Inv_W + + model->BSIM3v1Apnpeak * Inv_LW; + pParam->BSIM3v1Angate = model->BSIM3v1Angate + + model->BSIM3v1Alngate * Inv_L + + model->BSIM3v1Awngate * Inv_W + + model->BSIM3v1Apngate * Inv_LW; + pParam->BSIM3v1Agamma1 = model->BSIM3v1Agamma1 + + model->BSIM3v1Algamma1 * Inv_L + + model->BSIM3v1Awgamma1 * Inv_W + + model->BSIM3v1Apgamma1 * Inv_LW; + pParam->BSIM3v1Agamma2 = model->BSIM3v1Agamma2 + + model->BSIM3v1Algamma2 * Inv_L + + model->BSIM3v1Awgamma2 * Inv_W + + model->BSIM3v1Apgamma2 * Inv_LW; + pParam->BSIM3v1Avbx = model->BSIM3v1Avbx + + model->BSIM3v1Alvbx * Inv_L + + model->BSIM3v1Awvbx * Inv_W + + model->BSIM3v1Apvbx * Inv_LW; + pParam->BSIM3v1Avbm = model->BSIM3v1Avbm + + model->BSIM3v1Alvbm * Inv_L + + model->BSIM3v1Awvbm * Inv_W + + model->BSIM3v1Apvbm * Inv_LW; + pParam->BSIM3v1Axt = model->BSIM3v1Axt + + model->BSIM3v1Alxt * Inv_L + + model->BSIM3v1Awxt * Inv_W + + model->BSIM3v1Apxt * Inv_LW; + pParam->BSIM3v1Ak1 = model->BSIM3v1Ak1 + + model->BSIM3v1Alk1 * Inv_L + + model->BSIM3v1Awk1 * Inv_W + + model->BSIM3v1Apk1 * Inv_LW; + pParam->BSIM3v1Akt1 = model->BSIM3v1Akt1 + + model->BSIM3v1Alkt1 * Inv_L + + model->BSIM3v1Awkt1 * Inv_W + + model->BSIM3v1Apkt1 * Inv_LW; + pParam->BSIM3v1Akt1l = model->BSIM3v1Akt1l + + model->BSIM3v1Alkt1l * Inv_L + + model->BSIM3v1Awkt1l * Inv_W + + model->BSIM3v1Apkt1l * Inv_LW; + pParam->BSIM3v1Ak2 = model->BSIM3v1Ak2 + + model->BSIM3v1Alk2 * Inv_L + + model->BSIM3v1Awk2 * Inv_W + + model->BSIM3v1Apk2 * Inv_LW; + pParam->BSIM3v1Akt2 = model->BSIM3v1Akt2 + + model->BSIM3v1Alkt2 * Inv_L + + model->BSIM3v1Awkt2 * Inv_W + + model->BSIM3v1Apkt2 * Inv_LW; + pParam->BSIM3v1Ak3 = model->BSIM3v1Ak3 + + model->BSIM3v1Alk3 * Inv_L + + model->BSIM3v1Awk3 * Inv_W + + model->BSIM3v1Apk3 * Inv_LW; + pParam->BSIM3v1Ak3b = model->BSIM3v1Ak3b + + model->BSIM3v1Alk3b * Inv_L + + model->BSIM3v1Awk3b * Inv_W + + model->BSIM3v1Apk3b * Inv_LW; + pParam->BSIM3v1Aw0 = model->BSIM3v1Aw0 + + model->BSIM3v1Alw0 * Inv_L + + model->BSIM3v1Aww0 * Inv_W + + model->BSIM3v1Apw0 * Inv_LW; + pParam->BSIM3v1Anlx = model->BSIM3v1Anlx + + model->BSIM3v1Alnlx * Inv_L + + model->BSIM3v1Awnlx * Inv_W + + model->BSIM3v1Apnlx * Inv_LW; + pParam->BSIM3v1Advt0 = model->BSIM3v1Advt0 + + model->BSIM3v1Aldvt0 * Inv_L + + model->BSIM3v1Awdvt0 * Inv_W + + model->BSIM3v1Apdvt0 * Inv_LW; + pParam->BSIM3v1Advt1 = model->BSIM3v1Advt1 + + model->BSIM3v1Aldvt1 * Inv_L + + model->BSIM3v1Awdvt1 * Inv_W + + model->BSIM3v1Apdvt1 * Inv_LW; + pParam->BSIM3v1Advt2 = model->BSIM3v1Advt2 + + model->BSIM3v1Aldvt2 * Inv_L + + model->BSIM3v1Awdvt2 * Inv_W + + model->BSIM3v1Apdvt2 * Inv_LW; + pParam->BSIM3v1Advt0w = model->BSIM3v1Advt0w + + model->BSIM3v1Aldvt0w * Inv_L + + model->BSIM3v1Awdvt0w * Inv_W + + model->BSIM3v1Apdvt0w * Inv_LW; + pParam->BSIM3v1Advt1w = model->BSIM3v1Advt1w + + model->BSIM3v1Aldvt1w * Inv_L + + model->BSIM3v1Awdvt1w * Inv_W + + model->BSIM3v1Apdvt1w * Inv_LW; + pParam->BSIM3v1Advt2w = model->BSIM3v1Advt2w + + model->BSIM3v1Aldvt2w * Inv_L + + model->BSIM3v1Awdvt2w * Inv_W + + model->BSIM3v1Apdvt2w * Inv_LW; + pParam->BSIM3v1Adrout = model->BSIM3v1Adrout + + model->BSIM3v1Aldrout * Inv_L + + model->BSIM3v1Awdrout * Inv_W + + model->BSIM3v1Apdrout * Inv_LW; + pParam->BSIM3v1Adsub = model->BSIM3v1Adsub + + model->BSIM3v1Aldsub * Inv_L + + model->BSIM3v1Awdsub * Inv_W + + model->BSIM3v1Apdsub * Inv_LW; + pParam->BSIM3v1Avth0 = model->BSIM3v1Avth0 + + model->BSIM3v1Alvth0 * Inv_L + + model->BSIM3v1Awvth0 * Inv_W + + model->BSIM3v1Apvth0 * Inv_LW; + pParam->BSIM3v1Aua = model->BSIM3v1Aua + + model->BSIM3v1Alua * Inv_L + + model->BSIM3v1Awua * Inv_W + + model->BSIM3v1Apua * Inv_LW; + pParam->BSIM3v1Aua1 = model->BSIM3v1Aua1 + + model->BSIM3v1Alua1 * Inv_L + + model->BSIM3v1Awua1 * Inv_W + + model->BSIM3v1Apua1 * Inv_LW; + pParam->BSIM3v1Aub = model->BSIM3v1Aub + + model->BSIM3v1Alub * Inv_L + + model->BSIM3v1Awub * Inv_W + + model->BSIM3v1Apub * Inv_LW; + pParam->BSIM3v1Aub1 = model->BSIM3v1Aub1 + + model->BSIM3v1Alub1 * Inv_L + + model->BSIM3v1Awub1 * Inv_W + + model->BSIM3v1Apub1 * Inv_LW; + pParam->BSIM3v1Auc = model->BSIM3v1Auc + + model->BSIM3v1Aluc * Inv_L + + model->BSIM3v1Awuc * Inv_W + + model->BSIM3v1Apuc * Inv_LW; + pParam->BSIM3v1Auc1 = model->BSIM3v1Auc1 + + model->BSIM3v1Aluc1 * Inv_L + + model->BSIM3v1Awuc1 * Inv_W + + model->BSIM3v1Apuc1 * Inv_LW; + pParam->BSIM3v1Au0 = model->BSIM3v1Au0 + + model->BSIM3v1Alu0 * Inv_L + + model->BSIM3v1Awu0 * Inv_W + + model->BSIM3v1Apu0 * Inv_LW; + pParam->BSIM3v1Aute = model->BSIM3v1Aute + + model->BSIM3v1Alute * Inv_L + + model->BSIM3v1Awute * Inv_W + + model->BSIM3v1Apute * Inv_LW; + pParam->BSIM3v1Avoff = model->BSIM3v1Avoff + + model->BSIM3v1Alvoff * Inv_L + + model->BSIM3v1Awvoff * Inv_W + + model->BSIM3v1Apvoff * Inv_LW; + pParam->BSIM3v1Adelta = model->BSIM3v1Adelta + + model->BSIM3v1Aldelta * Inv_L + + model->BSIM3v1Awdelta * Inv_W + + model->BSIM3v1Apdelta * Inv_LW; + pParam->BSIM3v1Ardsw = model->BSIM3v1Ardsw + + model->BSIM3v1Alrdsw * Inv_L + + model->BSIM3v1Awrdsw * Inv_W + + model->BSIM3v1Aprdsw * Inv_LW; + pParam->BSIM3v1Aprwg = model->BSIM3v1Aprwg + + model->BSIM3v1Alprwg * Inv_L + + model->BSIM3v1Awprwg * Inv_W + + model->BSIM3v1Apprwg * Inv_LW; + pParam->BSIM3v1Aprwb = model->BSIM3v1Aprwb + + model->BSIM3v1Alprwb * Inv_L + + model->BSIM3v1Awprwb * Inv_W + + model->BSIM3v1Apprwb * Inv_LW; + pParam->BSIM3v1Aprt = model->BSIM3v1Aprt + + model->BSIM3v1Alprt * Inv_L + + model->BSIM3v1Awprt * Inv_W + + model->BSIM3v1Apprt * Inv_LW; + pParam->BSIM3v1Aeta0 = model->BSIM3v1Aeta0 + + model->BSIM3v1Aleta0 * Inv_L + + model->BSIM3v1Aweta0 * Inv_W + + model->BSIM3v1Apeta0 * Inv_LW; + pParam->BSIM3v1Aetab = model->BSIM3v1Aetab + + model->BSIM3v1Aletab * Inv_L + + model->BSIM3v1Awetab * Inv_W + + model->BSIM3v1Apetab * Inv_LW; + pParam->BSIM3v1Apclm = model->BSIM3v1Apclm + + model->BSIM3v1Alpclm * Inv_L + + model->BSIM3v1Awpclm * Inv_W + + model->BSIM3v1Appclm * Inv_LW; + pParam->BSIM3v1Apdibl1 = model->BSIM3v1Apdibl1 + + model->BSIM3v1Alpdibl1 * Inv_L + + model->BSIM3v1Awpdibl1 * Inv_W + + model->BSIM3v1Appdibl1 * Inv_LW; + pParam->BSIM3v1Apdibl2 = model->BSIM3v1Apdibl2 + + model->BSIM3v1Alpdibl2 * Inv_L + + model->BSIM3v1Awpdibl2 * Inv_W + + model->BSIM3v1Appdibl2 * Inv_LW; + pParam->BSIM3v1Apdiblb = model->BSIM3v1Apdiblb + + model->BSIM3v1Alpdiblb * Inv_L + + model->BSIM3v1Awpdiblb * Inv_W + + model->BSIM3v1Appdiblb * Inv_LW; + pParam->BSIM3v1Apscbe1 = model->BSIM3v1Apscbe1 + + model->BSIM3v1Alpscbe1 * Inv_L + + model->BSIM3v1Awpscbe1 * Inv_W + + model->BSIM3v1Appscbe1 * Inv_LW; + pParam->BSIM3v1Apscbe2 = model->BSIM3v1Apscbe2 + + model->BSIM3v1Alpscbe2 * Inv_L + + model->BSIM3v1Awpscbe2 * Inv_W + + model->BSIM3v1Appscbe2 * Inv_LW; + pParam->BSIM3v1Apvag = model->BSIM3v1Apvag + + model->BSIM3v1Alpvag * Inv_L + + model->BSIM3v1Awpvag * Inv_W + + model->BSIM3v1Appvag * Inv_LW; + pParam->BSIM3v1Awr = model->BSIM3v1Awr + + model->BSIM3v1Alwr * Inv_L + + model->BSIM3v1Awwr * Inv_W + + model->BSIM3v1Apwr * Inv_LW; + pParam->BSIM3v1Adwg = model->BSIM3v1Adwg + + model->BSIM3v1Aldwg * Inv_L + + model->BSIM3v1Awdwg * Inv_W + + model->BSIM3v1Apdwg * Inv_LW; + pParam->BSIM3v1Adwb = model->BSIM3v1Adwb + + model->BSIM3v1Aldwb * Inv_L + + model->BSIM3v1Awdwb * Inv_W + + model->BSIM3v1Apdwb * Inv_LW; + pParam->BSIM3v1Ab0 = model->BSIM3v1Ab0 + + model->BSIM3v1Alb0 * Inv_L + + model->BSIM3v1Awb0 * Inv_W + + model->BSIM3v1Apb0 * Inv_LW; + pParam->BSIM3v1Ab1 = model->BSIM3v1Ab1 + + model->BSIM3v1Alb1 * Inv_L + + model->BSIM3v1Awb1 * Inv_W + + model->BSIM3v1Apb1 * Inv_LW; + pParam->BSIM3v1Aalpha0 = model->BSIM3v1Aalpha0 + + model->BSIM3v1Alalpha0 * Inv_L + + model->BSIM3v1Awalpha0 * Inv_W + + model->BSIM3v1Apalpha0 * Inv_LW; + pParam->BSIM3v1Abeta0 = model->BSIM3v1Abeta0 + + model->BSIM3v1Albeta0 * Inv_L + + model->BSIM3v1Awbeta0 * Inv_W + + model->BSIM3v1Apbeta0 * Inv_LW; + /* CV model */ + pParam->BSIM3v1Aelm = model->BSIM3v1Aelm + + model->BSIM3v1Alelm * Inv_L + + model->BSIM3v1Awelm * Inv_W + + model->BSIM3v1Apelm * Inv_LW; + pParam->BSIM3v1Acgsl = model->BSIM3v1Acgsl + + model->BSIM3v1Alcgsl * Inv_L + + model->BSIM3v1Awcgsl * Inv_W + + model->BSIM3v1Apcgsl * Inv_LW; + pParam->BSIM3v1Acgdl = model->BSIM3v1Acgdl + + model->BSIM3v1Alcgdl * Inv_L + + model->BSIM3v1Awcgdl * Inv_W + + model->BSIM3v1Apcgdl * Inv_LW; + pParam->BSIM3v1Ackappa = model->BSIM3v1Ackappa + + model->BSIM3v1Alckappa * Inv_L + + model->BSIM3v1Awckappa * Inv_W + + model->BSIM3v1Apckappa * Inv_LW; + pParam->BSIM3v1Acf = model->BSIM3v1Acf + + model->BSIM3v1Alcf * Inv_L + + model->BSIM3v1Awcf * Inv_W + + model->BSIM3v1Apcf * Inv_LW; + pParam->BSIM3v1Aclc = model->BSIM3v1Aclc + + model->BSIM3v1Alclc * Inv_L + + model->BSIM3v1Awclc * Inv_W + + model->BSIM3v1Apclc * Inv_LW; + pParam->BSIM3v1Acle = model->BSIM3v1Acle + + model->BSIM3v1Alcle * Inv_L + + model->BSIM3v1Awcle * Inv_W + + model->BSIM3v1Apcle * Inv_LW; + pParam->BSIM3v1AabulkCVfactor = 1.0 + pow((pParam->BSIM3v1Aclc + / pParam->BSIM3v1Aleff), + pParam->BSIM3v1Acle); + + pParam->BSIM3v1Acgdo = (model->BSIM3v1Acgdo + pParam->BSIM3v1Acf) + * pParam->BSIM3v1AweffCV; + pParam->BSIM3v1Acgso = (model->BSIM3v1Acgso + pParam->BSIM3v1Acf) + * pParam->BSIM3v1AweffCV; + pParam->BSIM3v1Acgbo = model->BSIM3v1Acgbo * pParam->BSIM3v1AleffCV; + + T0 = (TRatio - 1.0); + pParam->BSIM3v1Aua = pParam->BSIM3v1Aua + pParam->BSIM3v1Aua1 * T0; + pParam->BSIM3v1Aub = pParam->BSIM3v1Aub + pParam->BSIM3v1Aub1 * T0; + pParam->BSIM3v1Auc = pParam->BSIM3v1Auc + pParam->BSIM3v1Auc1 * T0; + + pParam->BSIM3v1Au0temp = pParam->BSIM3v1Au0 + * pow(TRatio, pParam->BSIM3v1Aute); + pParam->BSIM3v1Avsattemp = pParam->BSIM3v1Avsat - pParam->BSIM3v1Aat + * T0; + pParam->BSIM3v1Ards0 = (pParam->BSIM3v1Ardsw + pParam->BSIM3v1Aprt * T0) + / pow(pParam->BSIM3v1Aweff * 1E6, pParam->BSIM3v1Awr); + + if (!model->BSIM3v1AnpeakGiven && model->BSIM3v1Agamma1Given) + { T0 = pParam->BSIM3v1Agamma1 * model->BSIM3v1Acox; + pParam->BSIM3v1Anpeak = 3.021E22 * T0 * T0; + } + + Vtm0 = KboQ * Tnom; + Eg = 1.16 - 7.02e-4 * Tnom * Tnom / (Tnom + 1108.0); + ni = 1.45e10 * (Tnom / 300.15) * sqrt(Tnom / 300.15) + * exp(21.5565981 - Eg / (2.0 * Vtm0)); + + pParam->BSIM3v1Aphi = 2.0 * Vtm0 + * log(pParam->BSIM3v1Anpeak / ni); + + pParam->BSIM3v1AsqrtPhi = sqrt(pParam->BSIM3v1Aphi); + pParam->BSIM3v1Aphis3 = pParam->BSIM3v1AsqrtPhi * pParam->BSIM3v1Aphi; + + pParam->BSIM3v1AXdep0 = sqrt(2.0 * EPSSI / (Charge_q + * pParam->BSIM3v1Anpeak * 1.0e6)) + * pParam->BSIM3v1AsqrtPhi; + pParam->BSIM3v1AsqrtXdep0 = sqrt(pParam->BSIM3v1AXdep0); + pParam->BSIM3v1Alitl = sqrt(3.0 * pParam->BSIM3v1Axj + * model->BSIM3v1Atox); + pParam->BSIM3v1Avbi = Vtm0 * log(1.0e20 + * pParam->BSIM3v1Anpeak / (ni * ni)); + pParam->BSIM3v1Acdep0 = sqrt(Charge_q * EPSSI + * pParam->BSIM3v1Anpeak * 1.0e6 / 2.0 + / pParam->BSIM3v1Aphi); + + if (model->BSIM3v1Ak1Given || model->BSIM3v1Ak2Given) + { if (!model->BSIM3v1Ak1Given) + { fprintf(stdout, "Warning: k1 should be specified with k2.\n"); + pParam->BSIM3v1Ak1 = 0.53; + } + if (!model->BSIM3v1Ak2Given) + { fprintf(stdout, "Warning: k2 should be specified with k1.\n"); + pParam->BSIM3v1Ak2 = -0.0186; + } + if (model->BSIM3v1AnsubGiven) + fprintf(stdout, "Warning: nsub is ignored because k1 or k2 is given.\n"); + if (model->BSIM3v1AxtGiven) + fprintf(stdout, "Warning: xt is ignored because k1 or k2 is given.\n"); + if (model->BSIM3v1AvbxGiven) + fprintf(stdout, "Warning: vbx is ignored because k1 or k2 is given.\n"); + if (model->BSIM3v1AvbmGiven) + fprintf(stdout, "Warning: vbm is ignored because k1 or k2 is given.\n"); + if (model->BSIM3v1Agamma1Given) + fprintf(stdout, "Warning: gamma1 is ignored because k1 or k2 is given.\n"); + if (model->BSIM3v1Agamma2Given) + fprintf(stdout, "Warning: gamma2 is ignored because k1 or k2 is given.\n"); + } + else + { if (!model->BSIM3v1AvbxGiven) + pParam->BSIM3v1Avbx = pParam->BSIM3v1Aphi - 7.7348e-4 + * pParam->BSIM3v1Anpeak + * pParam->BSIM3v1Axt * pParam->BSIM3v1Axt; + if (pParam->BSIM3v1Avbx > 0.0) + pParam->BSIM3v1Avbx = -pParam->BSIM3v1Avbx; + if (pParam->BSIM3v1Avbm > 0.0) + pParam->BSIM3v1Avbm = -pParam->BSIM3v1Avbm; + + if (!model->BSIM3v1Agamma1Given) + pParam->BSIM3v1Agamma1 = 5.753e-12 + * sqrt(pParam->BSIM3v1Anpeak) + / model->BSIM3v1Acox; + if (!model->BSIM3v1Agamma2Given) + pParam->BSIM3v1Agamma2 = 5.753e-12 + * sqrt(pParam->BSIM3v1Ansub) + / model->BSIM3v1Acox; + + T0 = pParam->BSIM3v1Agamma1 - pParam->BSIM3v1Agamma2; + T1 = sqrt(pParam->BSIM3v1Aphi - pParam->BSIM3v1Avbx) + - pParam->BSIM3v1AsqrtPhi; + T2 = sqrt(pParam->BSIM3v1Aphi * (pParam->BSIM3v1Aphi + - pParam->BSIM3v1Avbm)) - pParam->BSIM3v1Aphi; + pParam->BSIM3v1Ak2 = T0 * T1 / (2.0 * T2 + pParam->BSIM3v1Avbm); + pParam->BSIM3v1Ak1 = pParam->BSIM3v1Agamma2 - 2.0 + * pParam->BSIM3v1Ak2 * sqrt(pParam->BSIM3v1Aphi + - pParam->BSIM3v1Avbm); + } + + if (pParam->BSIM3v1Ak2 > 0.0) + { T0 = 0.5 * pParam->BSIM3v1Ak1 / pParam->BSIM3v1Ak2; + pParam->BSIM3v1Avbsc = 0.9 * (pParam->BSIM3v1Aphi - T0 * T0); + if (pParam->BSIM3v1Avbsc > -3.0) + pParam->BSIM3v1Avbsc = -3.0; + else if (pParam->BSIM3v1Avbsc < -30.0) + pParam->BSIM3v1Avbsc = -30.0; + } + else + { pParam->BSIM3v1Avbsc = -10.0; + } + + model->BSIM3v1Avtm = KboQ * Temp; + + if (model->BSIM3v1Avth0Given) + pParam->BSIM3v1Avfb = model->BSIM3v1Atype * pParam->BSIM3v1Avth0 + - pParam->BSIM3v1Aphi - pParam->BSIM3v1Ak1 + * pParam->BSIM3v1AsqrtPhi; + else + pParam->BSIM3v1Avth0 = model->BSIM3v1Atype * (-1.0 + + pParam->BSIM3v1Aphi + pParam->BSIM3v1Ak1 + * pParam->BSIM3v1AsqrtPhi); + + T1 = sqrt(EPSSI / EPSOX * model->BSIM3v1Atox + * pParam->BSIM3v1AXdep0); + T0 = exp(-0.5 * pParam->BSIM3v1Adsub * pParam->BSIM3v1Aleff / T1); + pParam->BSIM3v1Atheta0vb0 = (T0 + 2.0 * T0 * T0); + + T0 = exp(-0.5 * pParam->BSIM3v1Adrout * pParam->BSIM3v1Aleff / T1); + T2 = (T0 + 2.0 * T0 * T0); + pParam->BSIM3v1AthetaRout = pParam->BSIM3v1Apdibl1 * T2 + + pParam->BSIM3v1Apdibl2; + + /* process source/drain series resistance */ + here->BSIM3v1AdrainConductance = model->BSIM3v1AsheetResistance + * here->BSIM3v1AdrainSquares; + if (here->BSIM3v1AdrainConductance > 0.0) + here->BSIM3v1AdrainConductance = 1.0 + / here->BSIM3v1AdrainConductance; + else + here->BSIM3v1AdrainConductance = 0.0; + + here->BSIM3v1AsourceConductance = model->BSIM3v1AsheetResistance + * here->BSIM3v1AsourceSquares; + if (here->BSIM3v1AsourceConductance > 0.0) + here->BSIM3v1AsourceConductance = 1.0 + / here->BSIM3v1AsourceConductance; + else + here->BSIM3v1AsourceConductance = 0.0; + } + here->BSIM3v1Acgso = pParam->BSIM3v1Acgso; + here->BSIM3v1Acgdo = pParam->BSIM3v1Acgdo; + } + } + return(OK); +} + + + + diff --git a/src/spicelib/devices/bsim3v1a/b3v1atrunc.c b/src/spicelib/devices/bsim3v1a/b3v1atrunc.c new file mode 100644 index 000000000..7502eb519 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/b3v1atrunc.c @@ -0,0 +1,51 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan. +Modified by Paolo Nenzi 2002 +File: b3v1atrunc.c +**********/ + +#include "ngspice.h" +#include "cktdefs.h" +#include "bsim3v1adef.h" +#include "sperror.h" +#include "suffix.h" + + +int +BSIM3v1Atrunc(GENmodel *inModel, CKTcircuit *ckt, double *timeStep) +{ +BSIM3v1Amodel *model = (BSIM3v1Amodel*)inModel; +BSIM3v1Ainstance *here; + +#ifdef STEPDEBUG + double debugtemp; +#endif /* STEPDEBUG */ + + for (; model != NULL; model = model->BSIM3v1AnextModel) + { for (here = model->BSIM3v1Ainstances; here != NULL; + here = here->BSIM3v1AnextInstance) + { + + if (here->BSIM3v1Aowner != ARCHme) + continue; + +#ifdef STEPDEBUG + debugtemp = *timeStep; +#endif /* STEPDEBUG */ + CKTterr(here->BSIM3v1Aqb,ckt,timeStep); + CKTterr(here->BSIM3v1Aqg,ckt,timeStep); + CKTterr(here->BSIM3v1Aqd,ckt,timeStep); +#ifdef STEPDEBUG + if(debugtemp != *timeStep) + { printf("device %s reduces step from %g to %g\n", + here->BSIM3v1Aname,debugtemp,*timeStep); + } +#endif /* STEPDEBUG */ + } + } + return(OK); +} + + + diff --git a/src/spicelib/devices/bsim3v1a/bsim3v1adef.h b/src/spicelib/devices/bsim3v1a/bsim3v1adef.h new file mode 100644 index 000000000..64d7c7aab --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/bsim3v1adef.h @@ -0,0 +1,1580 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1995 Min-Chie Jeng and Mansun Chan +File: bsim3v1adef.h +**********/ + +#ifndef BSIM3v1A +#define BSIM3v1A + +#include "ifsim.h" +#include "gendefs.h" +#include "cktdefs.h" +#include "complex.h" +#include "noisedef.h" + +typedef struct sBSIM3v1Ainstance +{ + struct sBSIM3v1Amodel *BSIM3v1AmodPtr; + struct sBSIM3v1Ainstance *BSIM3v1AnextInstance; + IFuid BSIM3v1Aname; + int BSIM3v1Aowner; /* number of owner process */ + int BSIM3v1Astates; /* index into state table for this device */ + + int BSIM3v1AdNode; + int BSIM3v1AgNode; + int BSIM3v1AsNode; + int BSIM3v1AbNode; + int BSIM3v1AdNodePrime; + int BSIM3v1AsNodePrime; + int BSIM3v1AqNode; /* MCJ */ + + /* MCJ */ + double BSIM3v1Aueff; + double BSIM3v1Athetavth; + double BSIM3v1Avon; + double BSIM3v1Avdsat; + double BSIM3v1Acgdo; + double BSIM3v1Acgso; + + double BSIM3v1Al; + double BSIM3v1Aw; + double BSIM3v1Am; + double BSIM3v1AdrainArea; + double BSIM3v1AsourceArea; + double BSIM3v1AdrainSquares; + double BSIM3v1AsourceSquares; + double BSIM3v1AdrainPerimeter; + double BSIM3v1AsourcePerimeter; + double BSIM3v1AsourceConductance; + double BSIM3v1AdrainConductance; + + double BSIM3v1AicVBS; + double BSIM3v1AicVDS; + double BSIM3v1AicVGS; + int BSIM3v1Aoff; + int BSIM3v1Amode; + int BSIM3v1AnqsMod; + + /* OP point */ + double BSIM3v1Aqinv; + double BSIM3v1Acd; + double BSIM3v1Acbs; + double BSIM3v1Acbd; + double BSIM3v1Acsub; + double BSIM3v1Agm; + double BSIM3v1Agds; + double BSIM3v1Agmbs; + double BSIM3v1Agbd; + double BSIM3v1Agbs; + + double BSIM3v1Agbbs; + double BSIM3v1Agbgs; + double BSIM3v1Agbds; + + double BSIM3v1Acggb; + double BSIM3v1Acgdb; + double BSIM3v1Acgsb; + double BSIM3v1Acbgb; + double BSIM3v1Acbdb; + double BSIM3v1Acbsb; + double BSIM3v1Acdgb; + double BSIM3v1Acddb; + double BSIM3v1Acdsb; + double BSIM3v1Acapbd; + double BSIM3v1Acapbs; + + double BSIM3v1Acqgb; + double BSIM3v1Acqdb; + double BSIM3v1Acqsb; + double BSIM3v1Acqbb; + + double BSIM3v1Agtau; + double BSIM3v1Agtg; + double BSIM3v1Agtd; + double BSIM3v1Agts; + double BSIM3v1Agtb; + double BSIM3v1Atconst; + + struct bsim3v1aSizeDependParam *pParam; + + unsigned BSIM3v1AlGiven :1; + unsigned BSIM3v1AwGiven :1; + unsigned BSIM3v1AmGiven :1; + unsigned BSIM3v1AdrainAreaGiven :1; + unsigned BSIM3v1AsourceAreaGiven :1; + unsigned BSIM3v1AdrainSquaresGiven :1; + unsigned BSIM3v1AsourceSquaresGiven :1; + unsigned BSIM3v1AdrainPerimeterGiven :1; + unsigned BSIM3v1AsourcePerimeterGiven :1; + unsigned BSIM3v1AdNodePrimeSet :1; + unsigned BSIM3v1AsNodePrimeSet :1; + unsigned BSIM3v1AicVBSGiven :1; + unsigned BSIM3v1AicVDSGiven :1; + unsigned BSIM3v1AicVGSGiven :1; + unsigned BSIM3v1AnqsModGiven :1; + + double *BSIM3v1ADdPtr; + double *BSIM3v1AGgPtr; + double *BSIM3v1ASsPtr; + double *BSIM3v1ABbPtr; + double *BSIM3v1ADPdpPtr; + double *BSIM3v1ASPspPtr; + double *BSIM3v1ADdpPtr; + double *BSIM3v1AGbPtr; + double *BSIM3v1AGdpPtr; + double *BSIM3v1AGspPtr; + double *BSIM3v1ASspPtr; + double *BSIM3v1ABdpPtr; + double *BSIM3v1ABspPtr; + double *BSIM3v1ADPspPtr; + double *BSIM3v1ADPdPtr; + double *BSIM3v1ABgPtr; + double *BSIM3v1ADPgPtr; + double *BSIM3v1ASPgPtr; + double *BSIM3v1ASPsPtr; + double *BSIM3v1ADPbPtr; + double *BSIM3v1ASPbPtr; + double *BSIM3v1ASPdpPtr; + + double *BSIM3v1AQqPtr; + double *BSIM3v1AQdpPtr; + double *BSIM3v1AQgPtr; + double *BSIM3v1AQspPtr; + double *BSIM3v1AQbPtr; + double *BSIM3v1ADPqPtr; + double *BSIM3v1AGqPtr; + double *BSIM3v1ASPqPtr; + double *BSIM3v1ABqPtr; + + +#define BSIM3v1Avbd BSIM3v1Astates+ 0 +#define BSIM3v1Avbs BSIM3v1Astates+ 1 +#define BSIM3v1Avgs BSIM3v1Astates+ 2 +#define BSIM3v1Avds BSIM3v1Astates+ 3 + +#define BSIM3v1Aqb BSIM3v1Astates+ 4 +#define BSIM3v1Acqb BSIM3v1Astates+ 5 +#define BSIM3v1Aqg BSIM3v1Astates+ 6 +#define BSIM3v1Acqg BSIM3v1Astates+ 7 +#define BSIM3v1Aqd BSIM3v1Astates+ 8 +#define BSIM3v1Acqd BSIM3v1Astates+ 9 + +#define BSIM3v1Aqbs BSIM3v1Astates+ 10 +#define BSIM3v1Aqbd BSIM3v1Astates+ 11 + +#define BSIM3v1Aqcheq BSIM3v1Astates+ 12 +#define BSIM3v1Acqcheq BSIM3v1Astates+ 13 +#define BSIM3v1Aqcdump BSIM3v1Astates+ 14 +#define BSIM3v1Acqcdump BSIM3v1Astates+ 15 + +#define BSIM3v1Atau BSIM3v1Astates+ 16 +#define BSIM3v1Aqdef BSIM3v1Astates+ 17 + +#define BSIM3v1AnumStates 18 + + +/* indices to the array of BSIM3v1A NOISE SOURCES */ + +#define BSIM3v1ARDNOIZ 0 +#define BSIM3v1ARSNOIZ 1 +#define BSIM3v1AIDNOIZ 2 +#define BSIM3v1AFLNOIZ 3 +#define BSIM3v1ATOTNOIZ 4 + +#define BSIM3v1ANSRCS 5 /* the number of MOSFET(3) noise sources */ + +#ifndef NONOISE + double BSIM3v1AnVar[NSTATVARS][BSIM3v1ANSRCS]; +#else /* NONOISE */ + double **BSIM3v1AnVar; +#endif /* NONOISE */ + +} BSIM3v1Ainstance ; + +struct bsim3v1aSizeDependParam +{ + double Width; + double Length; + + double BSIM3v1Acdsc; + double BSIM3v1Acdscb; + double BSIM3v1Acdscd; + double BSIM3v1Acit; + double BSIM3v1Anfactor; + double BSIM3v1Axj; + double BSIM3v1Avsat; + double BSIM3v1Aat; + double BSIM3v1Aa0; + double BSIM3v1Aags; + double BSIM3v1Aa1; + double BSIM3v1Aa2; + double BSIM3v1Aketa; + double BSIM3v1Ansub; + double BSIM3v1Anpeak; + double BSIM3v1Angate; + double BSIM3v1Agamma1; + double BSIM3v1Agamma2; + double BSIM3v1Avbx; + double BSIM3v1Avbi; + double BSIM3v1Avbm; + double BSIM3v1Avbsc; + double BSIM3v1Axt; + double BSIM3v1Aphi; + double BSIM3v1Alitl; + double BSIM3v1Ak1; + double BSIM3v1Akt1; + double BSIM3v1Akt1l; + double BSIM3v1Akt2; + double BSIM3v1Ak2; + double BSIM3v1Ak3; + double BSIM3v1Ak3b; + double BSIM3v1Aw0; + double BSIM3v1Anlx; + double BSIM3v1Advt0; + double BSIM3v1Advt1; + double BSIM3v1Advt2; + double BSIM3v1Advt0w; + double BSIM3v1Advt1w; + double BSIM3v1Advt2w; + double BSIM3v1Adrout; + double BSIM3v1Adsub; + double BSIM3v1Avth0; + double BSIM3v1Aua; + double BSIM3v1Aua1; + double BSIM3v1Aub; + double BSIM3v1Aub1; + double BSIM3v1Auc; + double BSIM3v1Auc1; + double BSIM3v1Au0; + double BSIM3v1Aute; + double BSIM3v1Avoff; + double BSIM3v1Avfb; + double BSIM3v1Adelta; + double BSIM3v1Ardsw; + double BSIM3v1Ards0; + double BSIM3v1Aprwg; + double BSIM3v1Aprwb; + double BSIM3v1Aprt; + double BSIM3v1Aeta0; + double BSIM3v1Aetab; + double BSIM3v1Apclm; + double BSIM3v1Apdibl1; + double BSIM3v1Apdibl2; + double BSIM3v1Apdiblb; + double BSIM3v1Apscbe1; + double BSIM3v1Apscbe2; + double BSIM3v1Apvag; + double BSIM3v1Awr; + double BSIM3v1Adwg; + double BSIM3v1Adwb; + double BSIM3v1Ab0; + double BSIM3v1Ab1; + double BSIM3v1Aalpha0; + double BSIM3v1Abeta0; + + + /* CV model */ + double BSIM3v1Aelm; + double BSIM3v1Acgsl; + double BSIM3v1Acgdl; + double BSIM3v1Ackappa; + double BSIM3v1Acf; + double BSIM3v1Aclc; + double BSIM3v1Acle; + + +/* Pre-calculated constants */ + + double BSIM3v1Adw; + double BSIM3v1Adl; + double BSIM3v1Aleff; + double BSIM3v1Aweff; + + double BSIM3v1Adwc; + double BSIM3v1Adlc; + double BSIM3v1AleffCV; + double BSIM3v1AweffCV; + double BSIM3v1AabulkCVfactor; + double BSIM3v1Acgso; + double BSIM3v1Acgdo; + double BSIM3v1Acgbo; + + double BSIM3v1Au0temp; + double BSIM3v1Avsattemp; + double BSIM3v1AsqrtPhi; + double BSIM3v1Aphis3; + double BSIM3v1AXdep0; + double BSIM3v1AsqrtXdep0; + double BSIM3v1Atheta0vb0; + double BSIM3v1AthetaRout; + + double BSIM3v1Acof1; + double BSIM3v1Acof2; + double BSIM3v1Acof3; + double BSIM3v1Acof4; + double BSIM3v1Acdep0; + struct bsim3v1aSizeDependParam *pNext; +}; + + +typedef struct sBSIM3v1Amodel +{ + int BSIM3v1AmodType; + struct sBSIM3v1Amodel *BSIM3v1AnextModel; + BSIM3v1Ainstance *BSIM3v1Ainstances; + IFuid BSIM3v1AmodName; + int BSIM3v1Atype; + + int BSIM3v1AmobMod; + int BSIM3v1AcapMod; + int BSIM3v1AnqsMod; + int BSIM3v1AnoiMod; + int BSIM3v1AbinUnit; + double BSIM3v1Atox; + double BSIM3v1Acdsc; + double BSIM3v1Acdscb; + double BSIM3v1Acdscd; + double BSIM3v1Acit; + double BSIM3v1Anfactor; + double BSIM3v1Axj; + double BSIM3v1Avsat; + double BSIM3v1Aat; + double BSIM3v1Aa0; + double BSIM3v1Aags; + double BSIM3v1Aa1; + double BSIM3v1Aa2; + double BSIM3v1Aketa; + double BSIM3v1Ansub; + double BSIM3v1Anpeak; + double BSIM3v1Angate; + double BSIM3v1Agamma1; + double BSIM3v1Agamma2; + double BSIM3v1Avbx; + double BSIM3v1Avbm; + double BSIM3v1Axt; + double BSIM3v1Ak1; + double BSIM3v1Akt1; + double BSIM3v1Akt1l; + double BSIM3v1Akt2; + double BSIM3v1Ak2; + double BSIM3v1Ak3; + double BSIM3v1Ak3b; + double BSIM3v1Aw0; + double BSIM3v1Anlx; + double BSIM3v1Advt0; + double BSIM3v1Advt1; + double BSIM3v1Advt2; + double BSIM3v1Advt0w; + double BSIM3v1Advt1w; + double BSIM3v1Advt2w; + double BSIM3v1Adrout; + double BSIM3v1Adsub; + double BSIM3v1Avth0; + double BSIM3v1Aua; + double BSIM3v1Aua1; + double BSIM3v1Aub; + double BSIM3v1Aub1; + double BSIM3v1Auc; + double BSIM3v1Auc1; + double BSIM3v1Au0; + double BSIM3v1Aute; + double BSIM3v1Avoff; + double BSIM3v1Adelta; + double BSIM3v1Ardsw; + double BSIM3v1Aprwg; + double BSIM3v1Aprwb; + double BSIM3v1Aprt; + double BSIM3v1Aeta0; + double BSIM3v1Aetab; + double BSIM3v1Apclm; + double BSIM3v1Apdibl1; + double BSIM3v1Apdibl2; + double BSIM3v1Apdiblb; + double BSIM3v1Apscbe1; + double BSIM3v1Apscbe2; + double BSIM3v1Apvag; + double BSIM3v1Awr; + double BSIM3v1Adwg; + double BSIM3v1Adwb; + double BSIM3v1Ab0; + double BSIM3v1Ab1; + double BSIM3v1Aalpha0; + double BSIM3v1Abeta0; + + /* CV model */ + double BSIM3v1Aelm; + double BSIM3v1Acgsl; + double BSIM3v1Acgdl; + double BSIM3v1Ackappa; + double BSIM3v1Acf; + double BSIM3v1Aclc; + double BSIM3v1Acle; + double BSIM3v1Adwc; + double BSIM3v1Adlc; + + /* Length Dependence */ + double BSIM3v1Alcdsc; + double BSIM3v1Alcdscb; + double BSIM3v1Alcdscd; + double BSIM3v1Alcit; + double BSIM3v1Alnfactor; + double BSIM3v1Alxj; + double BSIM3v1Alvsat; + double BSIM3v1Alat; + double BSIM3v1Ala0; + double BSIM3v1Alags; + double BSIM3v1Ala1; + double BSIM3v1Ala2; + double BSIM3v1Alketa; + double BSIM3v1Alnsub; + double BSIM3v1Alnpeak; + double BSIM3v1Alngate; + double BSIM3v1Algamma1; + double BSIM3v1Algamma2; + double BSIM3v1Alvbx; + double BSIM3v1Alvbm; + double BSIM3v1Alxt; + double BSIM3v1Alk1; + double BSIM3v1Alkt1; + double BSIM3v1Alkt1l; + double BSIM3v1Alkt2; + double BSIM3v1Alk2; + double BSIM3v1Alk3; + double BSIM3v1Alk3b; + double BSIM3v1Alw0; + double BSIM3v1Alnlx; + double BSIM3v1Aldvt0; + double BSIM3v1Aldvt1; + double BSIM3v1Aldvt2; + double BSIM3v1Aldvt0w; + double BSIM3v1Aldvt1w; + double BSIM3v1Aldvt2w; + double BSIM3v1Aldrout; + double BSIM3v1Aldsub; + double BSIM3v1Alvth0; + double BSIM3v1Alua; + double BSIM3v1Alua1; + double BSIM3v1Alub; + double BSIM3v1Alub1; + double BSIM3v1Aluc; + double BSIM3v1Aluc1; + double BSIM3v1Alu0; + double BSIM3v1Alute; + double BSIM3v1Alvoff; + double BSIM3v1Aldelta; + double BSIM3v1Alrdsw; + double BSIM3v1Alprwg; + double BSIM3v1Alprwb; + double BSIM3v1Alprt; + double BSIM3v1Aleta0; + double BSIM3v1Aletab; + double BSIM3v1Alpclm; + double BSIM3v1Alpdibl1; + double BSIM3v1Alpdibl2; + double BSIM3v1Alpdiblb; + double BSIM3v1Alpscbe1; + double BSIM3v1Alpscbe2; + double BSIM3v1Alpvag; + double BSIM3v1Alwr; + double BSIM3v1Aldwg; + double BSIM3v1Aldwb; + double BSIM3v1Alb0; + double BSIM3v1Alb1; + double BSIM3v1Alalpha0; + double BSIM3v1Albeta0; + + /* CV model */ + double BSIM3v1Alelm; + double BSIM3v1Alcgsl; + double BSIM3v1Alcgdl; + double BSIM3v1Alckappa; + double BSIM3v1Alcf; + double BSIM3v1Alclc; + double BSIM3v1Alcle; + + /* Width Dependence */ + double BSIM3v1Awcdsc; + double BSIM3v1Awcdscb; + double BSIM3v1Awcdscd; + double BSIM3v1Awcit; + double BSIM3v1Awnfactor; + double BSIM3v1Awxj; + double BSIM3v1Awvsat; + double BSIM3v1Awat; + double BSIM3v1Awa0; + double BSIM3v1Awags; + double BSIM3v1Awa1; + double BSIM3v1Awa2; + double BSIM3v1Awketa; + double BSIM3v1Awnsub; + double BSIM3v1Awnpeak; + double BSIM3v1Awngate; + double BSIM3v1Awgamma1; + double BSIM3v1Awgamma2; + double BSIM3v1Awvbx; + double BSIM3v1Awvbm; + double BSIM3v1Awxt; + double BSIM3v1Awk1; + double BSIM3v1Awkt1; + double BSIM3v1Awkt1l; + double BSIM3v1Awkt2; + double BSIM3v1Awk2; + double BSIM3v1Awk3; + double BSIM3v1Awk3b; + double BSIM3v1Aww0; + double BSIM3v1Awnlx; + double BSIM3v1Awdvt0; + double BSIM3v1Awdvt1; + double BSIM3v1Awdvt2; + double BSIM3v1Awdvt0w; + double BSIM3v1Awdvt1w; + double BSIM3v1Awdvt2w; + double BSIM3v1Awdrout; + double BSIM3v1Awdsub; + double BSIM3v1Awvth0; + double BSIM3v1Awua; + double BSIM3v1Awua1; + double BSIM3v1Awub; + double BSIM3v1Awub1; + double BSIM3v1Awuc; + double BSIM3v1Awuc1; + double BSIM3v1Awu0; + double BSIM3v1Awute; + double BSIM3v1Awvoff; + double BSIM3v1Awdelta; + double BSIM3v1Awrdsw; + double BSIM3v1Awprwg; + double BSIM3v1Awprwb; + double BSIM3v1Awprt; + double BSIM3v1Aweta0; + double BSIM3v1Awetab; + double BSIM3v1Awpclm; + double BSIM3v1Awpdibl1; + double BSIM3v1Awpdibl2; + double BSIM3v1Awpdiblb; + double BSIM3v1Awpscbe1; + double BSIM3v1Awpscbe2; + double BSIM3v1Awpvag; + double BSIM3v1Awwr; + double BSIM3v1Awdwg; + double BSIM3v1Awdwb; + double BSIM3v1Awb0; + double BSIM3v1Awb1; + double BSIM3v1Awalpha0; + double BSIM3v1Awbeta0; + + /* CV model */ + double BSIM3v1Awelm; + double BSIM3v1Awcgsl; + double BSIM3v1Awcgdl; + double BSIM3v1Awckappa; + double BSIM3v1Awcf; + double BSIM3v1Awclc; + double BSIM3v1Awcle; + + /* Cross-term Dependence */ + double BSIM3v1Apcdsc; + double BSIM3v1Apcdscb; + double BSIM3v1Apcdscd; + double BSIM3v1Apcit; + double BSIM3v1Apnfactor; + double BSIM3v1Apxj; + double BSIM3v1Apvsat; + double BSIM3v1Apat; + double BSIM3v1Apa0; + double BSIM3v1Apags; + double BSIM3v1Apa1; + double BSIM3v1Apa2; + double BSIM3v1Apketa; + double BSIM3v1Apnsub; + double BSIM3v1Apnpeak; + double BSIM3v1Apngate; + double BSIM3v1Apgamma1; + double BSIM3v1Apgamma2; + double BSIM3v1Apvbx; + double BSIM3v1Apvbm; + double BSIM3v1Apxt; + double BSIM3v1Apk1; + double BSIM3v1Apkt1; + double BSIM3v1Apkt1l; + double BSIM3v1Apkt2; + double BSIM3v1Apk2; + double BSIM3v1Apk3; + double BSIM3v1Apk3b; + double BSIM3v1Apw0; + double BSIM3v1Apnlx; + double BSIM3v1Apdvt0; + double BSIM3v1Apdvt1; + double BSIM3v1Apdvt2; + double BSIM3v1Apdvt0w; + double BSIM3v1Apdvt1w; + double BSIM3v1Apdvt2w; + double BSIM3v1Apdrout; + double BSIM3v1Apdsub; + double BSIM3v1Apvth0; + double BSIM3v1Apua; + double BSIM3v1Apua1; + double BSIM3v1Apub; + double BSIM3v1Apub1; + double BSIM3v1Apuc; + double BSIM3v1Apuc1; + double BSIM3v1Apu0; + double BSIM3v1Apute; + double BSIM3v1Apvoff; + double BSIM3v1Apdelta; + double BSIM3v1Aprdsw; + double BSIM3v1Apprwg; + double BSIM3v1Apprwb; + double BSIM3v1Apprt; + double BSIM3v1Apeta0; + double BSIM3v1Apetab; + double BSIM3v1Appclm; + double BSIM3v1Appdibl1; + double BSIM3v1Appdibl2; + double BSIM3v1Appdiblb; + double BSIM3v1Appscbe1; + double BSIM3v1Appscbe2; + double BSIM3v1Appvag; + double BSIM3v1Apwr; + double BSIM3v1Apdwg; + double BSIM3v1Apdwb; + double BSIM3v1Apb0; + double BSIM3v1Apb1; + double BSIM3v1Apalpha0; + double BSIM3v1Apbeta0; + + /* CV model */ + double BSIM3v1Apelm; + double BSIM3v1Apcgsl; + double BSIM3v1Apcgdl; + double BSIM3v1Apckappa; + double BSIM3v1Apcf; + double BSIM3v1Apclc; + double BSIM3v1Apcle; + + double BSIM3v1Atnom; + double BSIM3v1Acgso; + double BSIM3v1Acgdo; + double BSIM3v1Acgbo; + double BSIM3v1Axpart; + double BSIM3v1AcFringOut; + double BSIM3v1AcFringMax; + + double BSIM3v1AsheetResistance; + double BSIM3v1AjctSatCurDensity; + double BSIM3v1AbulkJctPotential; + double BSIM3v1AbulkJctBotGradingCoeff; + double BSIM3v1AbulkJctSideGradingCoeff; + double BSIM3v1AsidewallJctPotential; + double BSIM3v1AunitAreaJctCap; + double BSIM3v1AunitLengthSidewallJctCap; + + double BSIM3v1ALint; + double BSIM3v1ALl; + double BSIM3v1ALln; + double BSIM3v1ALw; + double BSIM3v1ALwn; + double BSIM3v1ALwl; + double BSIM3v1ALmin; + double BSIM3v1ALmax; + + double BSIM3v1AWint; + double BSIM3v1AWl; + double BSIM3v1AWln; + double BSIM3v1AWw; + double BSIM3v1AWwn; + double BSIM3v1AWwl; + double BSIM3v1AWmin; + double BSIM3v1AWmax; + + +/* Pre-calculated constants */ + /* MCJ: move to size-dependent param. */ + double BSIM3v1Avtm; + double BSIM3v1Acox; + double BSIM3v1Acof1; + double BSIM3v1Acof2; + double BSIM3v1Acof3; + double BSIM3v1Acof4; + double BSIM3v1Avcrit; + double BSIM3v1Afactor1; + + double BSIM3v1AoxideTrapDensityA; + double BSIM3v1AoxideTrapDensityB; + double BSIM3v1AoxideTrapDensityC; + double BSIM3v1Aem; + double BSIM3v1Aef; + double BSIM3v1Aaf; + double BSIM3v1Akf; + + struct bsim3v1aSizeDependParam *pSizeDependParamKnot; + + /* Flags */ + unsigned BSIM3v1AmobModGiven :1; + unsigned BSIM3v1AbinUnitGiven :1; + unsigned BSIM3v1AcapModGiven :1; + unsigned BSIM3v1AnqsModGiven :1; + unsigned BSIM3v1AnoiModGiven :1; + unsigned BSIM3v1AtypeGiven :1; + unsigned BSIM3v1AtoxGiven :1; + + unsigned BSIM3v1AcdscGiven :1; + unsigned BSIM3v1AcdscbGiven :1; + unsigned BSIM3v1AcdscdGiven :1; + unsigned BSIM3v1AcitGiven :1; + unsigned BSIM3v1AnfactorGiven :1; + unsigned BSIM3v1AxjGiven :1; + unsigned BSIM3v1AvsatGiven :1; + unsigned BSIM3v1AatGiven :1; + unsigned BSIM3v1Aa0Given :1; + unsigned BSIM3v1AagsGiven :1; + unsigned BSIM3v1Aa1Given :1; + unsigned BSIM3v1Aa2Given :1; + unsigned BSIM3v1AketaGiven :1; + unsigned BSIM3v1AnsubGiven :1; + unsigned BSIM3v1AnpeakGiven :1; + unsigned BSIM3v1AngateGiven :1; + unsigned BSIM3v1Agamma1Given :1; + unsigned BSIM3v1Agamma2Given :1; + unsigned BSIM3v1AvbxGiven :1; + unsigned BSIM3v1AvbmGiven :1; + unsigned BSIM3v1AxtGiven :1; + unsigned BSIM3v1Ak1Given :1; + unsigned BSIM3v1Akt1Given :1; + unsigned BSIM3v1Akt1lGiven :1; + unsigned BSIM3v1Akt2Given :1; + unsigned BSIM3v1Ak2Given :1; + unsigned BSIM3v1Ak3Given :1; + unsigned BSIM3v1Ak3bGiven :1; + unsigned BSIM3v1Aw0Given :1; + unsigned BSIM3v1AnlxGiven :1; + unsigned BSIM3v1Advt0Given :1; + unsigned BSIM3v1Advt1Given :1; + unsigned BSIM3v1Advt2Given :1; + unsigned BSIM3v1Advt0wGiven :1; + unsigned BSIM3v1Advt1wGiven :1; + unsigned BSIM3v1Advt2wGiven :1; + unsigned BSIM3v1AdroutGiven :1; + unsigned BSIM3v1AdsubGiven :1; + unsigned BSIM3v1Avth0Given :1; + unsigned BSIM3v1AuaGiven :1; + unsigned BSIM3v1Aua1Given :1; + unsigned BSIM3v1AubGiven :1; + unsigned BSIM3v1Aub1Given :1; + unsigned BSIM3v1AucGiven :1; + unsigned BSIM3v1Auc1Given :1; + unsigned BSIM3v1Au0Given :1; + unsigned BSIM3v1AuteGiven :1; + unsigned BSIM3v1AvoffGiven :1; + unsigned BSIM3v1ArdswGiven :1; + unsigned BSIM3v1AprwgGiven :1; + unsigned BSIM3v1AprwbGiven :1; + unsigned BSIM3v1AprtGiven :1; + unsigned BSIM3v1Aeta0Given :1; + unsigned BSIM3v1AetabGiven :1; + unsigned BSIM3v1ApclmGiven :1; + unsigned BSIM3v1Apdibl1Given :1; + unsigned BSIM3v1Apdibl2Given :1; + unsigned BSIM3v1ApdiblbGiven :1; + unsigned BSIM3v1Apscbe1Given :1; + unsigned BSIM3v1Apscbe2Given :1; + unsigned BSIM3v1ApvagGiven :1; + unsigned BSIM3v1AdeltaGiven :1; + unsigned BSIM3v1AwrGiven :1; + unsigned BSIM3v1AdwgGiven :1; + unsigned BSIM3v1AdwbGiven :1; + unsigned BSIM3v1Ab0Given :1; + unsigned BSIM3v1Ab1Given :1; + unsigned BSIM3v1Aalpha0Given :1; + unsigned BSIM3v1Abeta0Given :1; + + /* CV model */ + unsigned BSIM3v1AelmGiven :1; + unsigned BSIM3v1AcgslGiven :1; + unsigned BSIM3v1AcgdlGiven :1; + unsigned BSIM3v1AckappaGiven :1; + unsigned BSIM3v1AcfGiven :1; + unsigned BSIM3v1AclcGiven :1; + unsigned BSIM3v1AcleGiven :1; + unsigned BSIM3v1AdwcGiven :1; + unsigned BSIM3v1AdlcGiven :1; + + + /* Length dependence */ + unsigned BSIM3v1AlcdscGiven :1; + unsigned BSIM3v1AlcdscbGiven :1; + unsigned BSIM3v1AlcdscdGiven :1; + unsigned BSIM3v1AlcitGiven :1; + unsigned BSIM3v1AlnfactorGiven :1; + unsigned BSIM3v1AlxjGiven :1; + unsigned BSIM3v1AlvsatGiven :1; + unsigned BSIM3v1AlatGiven :1; + unsigned BSIM3v1Ala0Given :1; + unsigned BSIM3v1AlagsGiven :1; + unsigned BSIM3v1Ala1Given :1; + unsigned BSIM3v1Ala2Given :1; + unsigned BSIM3v1AlketaGiven :1; + unsigned BSIM3v1AlnsubGiven :1; + unsigned BSIM3v1AlnpeakGiven :1; + unsigned BSIM3v1AlngateGiven :1; + unsigned BSIM3v1Algamma1Given :1; + unsigned BSIM3v1Algamma2Given :1; + unsigned BSIM3v1AlvbxGiven :1; + unsigned BSIM3v1AlvbmGiven :1; + unsigned BSIM3v1AlxtGiven :1; + unsigned BSIM3v1Alk1Given :1; + unsigned BSIM3v1Alkt1Given :1; + unsigned BSIM3v1Alkt1lGiven :1; + unsigned BSIM3v1Alkt2Given :1; + unsigned BSIM3v1Alk2Given :1; + unsigned BSIM3v1Alk3Given :1; + unsigned BSIM3v1Alk3bGiven :1; + unsigned BSIM3v1Alw0Given :1; + unsigned BSIM3v1AlnlxGiven :1; + unsigned BSIM3v1Aldvt0Given :1; + unsigned BSIM3v1Aldvt1Given :1; + unsigned BSIM3v1Aldvt2Given :1; + unsigned BSIM3v1Aldvt0wGiven :1; + unsigned BSIM3v1Aldvt1wGiven :1; + unsigned BSIM3v1Aldvt2wGiven :1; + unsigned BSIM3v1AldroutGiven :1; + unsigned BSIM3v1AldsubGiven :1; + unsigned BSIM3v1Alvth0Given :1; + unsigned BSIM3v1AluaGiven :1; + unsigned BSIM3v1Alua1Given :1; + unsigned BSIM3v1AlubGiven :1; + unsigned BSIM3v1Alub1Given :1; + unsigned BSIM3v1AlucGiven :1; + unsigned BSIM3v1Aluc1Given :1; + unsigned BSIM3v1Alu0Given :1; + unsigned BSIM3v1AluteGiven :1; + unsigned BSIM3v1AlvoffGiven :1; + unsigned BSIM3v1AlrdswGiven :1; + unsigned BSIM3v1AlprwgGiven :1; + unsigned BSIM3v1AlprwbGiven :1; + unsigned BSIM3v1AlprtGiven :1; + unsigned BSIM3v1Aleta0Given :1; + unsigned BSIM3v1AletabGiven :1; + unsigned BSIM3v1AlpclmGiven :1; + unsigned BSIM3v1Alpdibl1Given :1; + unsigned BSIM3v1Alpdibl2Given :1; + unsigned BSIM3v1AlpdiblbGiven :1; + unsigned BSIM3v1Alpscbe1Given :1; + unsigned BSIM3v1Alpscbe2Given :1; + unsigned BSIM3v1AlpvagGiven :1; + unsigned BSIM3v1AldeltaGiven :1; + unsigned BSIM3v1AlwrGiven :1; + unsigned BSIM3v1AldwgGiven :1; + unsigned BSIM3v1AldwbGiven :1; + unsigned BSIM3v1Alb0Given :1; + unsigned BSIM3v1Alb1Given :1; + unsigned BSIM3v1Alalpha0Given :1; + unsigned BSIM3v1Albeta0Given :1; + + /* CV model */ + unsigned BSIM3v1AlelmGiven :1; + unsigned BSIM3v1AlcgslGiven :1; + unsigned BSIM3v1AlcgdlGiven :1; + unsigned BSIM3v1AlckappaGiven :1; + unsigned BSIM3v1AlcfGiven :1; + unsigned BSIM3v1AlclcGiven :1; + unsigned BSIM3v1AlcleGiven :1; + + /* Width dependence */ + unsigned BSIM3v1AwcdscGiven :1; + unsigned BSIM3v1AwcdscbGiven :1; + unsigned BSIM3v1AwcdscdGiven :1; + unsigned BSIM3v1AwcitGiven :1; + unsigned BSIM3v1AwnfactorGiven :1; + unsigned BSIM3v1AwxjGiven :1; + unsigned BSIM3v1AwvsatGiven :1; + unsigned BSIM3v1AwatGiven :1; + unsigned BSIM3v1Awa0Given :1; + unsigned BSIM3v1AwagsGiven :1; + unsigned BSIM3v1Awa1Given :1; + unsigned BSIM3v1Awa2Given :1; + unsigned BSIM3v1AwketaGiven :1; + unsigned BSIM3v1AwnsubGiven :1; + unsigned BSIM3v1AwnpeakGiven :1; + unsigned BSIM3v1AwngateGiven :1; + unsigned BSIM3v1Awgamma1Given :1; + unsigned BSIM3v1Awgamma2Given :1; + unsigned BSIM3v1AwvbxGiven :1; + unsigned BSIM3v1AwvbmGiven :1; + unsigned BSIM3v1AwxtGiven :1; + unsigned BSIM3v1Awk1Given :1; + unsigned BSIM3v1Awkt1Given :1; + unsigned BSIM3v1Awkt1lGiven :1; + unsigned BSIM3v1Awkt2Given :1; + unsigned BSIM3v1Awk2Given :1; + unsigned BSIM3v1Awk3Given :1; + unsigned BSIM3v1Awk3bGiven :1; + unsigned BSIM3v1Aww0Given :1; + unsigned BSIM3v1AwnlxGiven :1; + unsigned BSIM3v1Awdvt0Given :1; + unsigned BSIM3v1Awdvt1Given :1; + unsigned BSIM3v1Awdvt2Given :1; + unsigned BSIM3v1Awdvt0wGiven :1; + unsigned BSIM3v1Awdvt1wGiven :1; + unsigned BSIM3v1Awdvt2wGiven :1; + unsigned BSIM3v1AwdroutGiven :1; + unsigned BSIM3v1AwdsubGiven :1; + unsigned BSIM3v1Awvth0Given :1; + unsigned BSIM3v1AwuaGiven :1; + unsigned BSIM3v1Awua1Given :1; + unsigned BSIM3v1AwubGiven :1; + unsigned BSIM3v1Awub1Given :1; + unsigned BSIM3v1AwucGiven :1; + unsigned BSIM3v1Awuc1Given :1; + unsigned BSIM3v1Awu0Given :1; + unsigned BSIM3v1AwuteGiven :1; + unsigned BSIM3v1AwvoffGiven :1; + unsigned BSIM3v1AwrdswGiven :1; + unsigned BSIM3v1AwprwgGiven :1; + unsigned BSIM3v1AwprwbGiven :1; + unsigned BSIM3v1AwprtGiven :1; + unsigned BSIM3v1Aweta0Given :1; + unsigned BSIM3v1AwetabGiven :1; + unsigned BSIM3v1AwpclmGiven :1; + unsigned BSIM3v1Awpdibl1Given :1; + unsigned BSIM3v1Awpdibl2Given :1; + unsigned BSIM3v1AwpdiblbGiven :1; + unsigned BSIM3v1Awpscbe1Given :1; + unsigned BSIM3v1Awpscbe2Given :1; + unsigned BSIM3v1AwpvagGiven :1; + unsigned BSIM3v1AwdeltaGiven :1; + unsigned BSIM3v1AwwrGiven :1; + unsigned BSIM3v1AwdwgGiven :1; + unsigned BSIM3v1AwdwbGiven :1; + unsigned BSIM3v1Awb0Given :1; + unsigned BSIM3v1Awb1Given :1; + unsigned BSIM3v1Awalpha0Given :1; + unsigned BSIM3v1Awbeta0Given :1; + + /* CV model */ + unsigned BSIM3v1AwelmGiven :1; + unsigned BSIM3v1AwcgslGiven :1; + unsigned BSIM3v1AwcgdlGiven :1; + unsigned BSIM3v1AwckappaGiven :1; + unsigned BSIM3v1AwcfGiven :1; + unsigned BSIM3v1AwclcGiven :1; + unsigned BSIM3v1AwcleGiven :1; + + /* Cross-term dependence */ + unsigned BSIM3v1ApcdscGiven :1; + unsigned BSIM3v1ApcdscbGiven :1; + unsigned BSIM3v1ApcdscdGiven :1; + unsigned BSIM3v1ApcitGiven :1; + unsigned BSIM3v1ApnfactorGiven :1; + unsigned BSIM3v1ApxjGiven :1; + unsigned BSIM3v1ApvsatGiven :1; + unsigned BSIM3v1ApatGiven :1; + unsigned BSIM3v1Apa0Given :1; + unsigned BSIM3v1ApagsGiven :1; + unsigned BSIM3v1Apa1Given :1; + unsigned BSIM3v1Apa2Given :1; + unsigned BSIM3v1ApketaGiven :1; + unsigned BSIM3v1ApnsubGiven :1; + unsigned BSIM3v1ApnpeakGiven :1; + unsigned BSIM3v1ApngateGiven :1; + unsigned BSIM3v1Apgamma1Given :1; + unsigned BSIM3v1Apgamma2Given :1; + unsigned BSIM3v1ApvbxGiven :1; + unsigned BSIM3v1ApvbmGiven :1; + unsigned BSIM3v1ApxtGiven :1; + unsigned BSIM3v1Apk1Given :1; + unsigned BSIM3v1Apkt1Given :1; + unsigned BSIM3v1Apkt1lGiven :1; + unsigned BSIM3v1Apkt2Given :1; + unsigned BSIM3v1Apk2Given :1; + unsigned BSIM3v1Apk3Given :1; + unsigned BSIM3v1Apk3bGiven :1; + unsigned BSIM3v1Apw0Given :1; + unsigned BSIM3v1ApnlxGiven :1; + unsigned BSIM3v1Apdvt0Given :1; + unsigned BSIM3v1Apdvt1Given :1; + unsigned BSIM3v1Apdvt2Given :1; + unsigned BSIM3v1Apdvt0wGiven :1; + unsigned BSIM3v1Apdvt1wGiven :1; + unsigned BSIM3v1Apdvt2wGiven :1; + unsigned BSIM3v1ApdroutGiven :1; + unsigned BSIM3v1ApdsubGiven :1; + unsigned BSIM3v1Apvth0Given :1; + unsigned BSIM3v1ApuaGiven :1; + unsigned BSIM3v1Apua1Given :1; + unsigned BSIM3v1ApubGiven :1; + unsigned BSIM3v1Apub1Given :1; + unsigned BSIM3v1ApucGiven :1; + unsigned BSIM3v1Apuc1Given :1; + unsigned BSIM3v1Apu0Given :1; + unsigned BSIM3v1AputeGiven :1; + unsigned BSIM3v1ApvoffGiven :1; + unsigned BSIM3v1AprdswGiven :1; + unsigned BSIM3v1ApprwgGiven :1; + unsigned BSIM3v1ApprwbGiven :1; + unsigned BSIM3v1ApprtGiven :1; + unsigned BSIM3v1Apeta0Given :1; + unsigned BSIM3v1ApetabGiven :1; + unsigned BSIM3v1AppclmGiven :1; + unsigned BSIM3v1Appdibl1Given :1; + unsigned BSIM3v1Appdibl2Given :1; + unsigned BSIM3v1AppdiblbGiven :1; + unsigned BSIM3v1Appscbe1Given :1; + unsigned BSIM3v1Appscbe2Given :1; + unsigned BSIM3v1AppvagGiven :1; + unsigned BSIM3v1ApdeltaGiven :1; + unsigned BSIM3v1ApwrGiven :1; + unsigned BSIM3v1ApdwgGiven :1; + unsigned BSIM3v1ApdwbGiven :1; + unsigned BSIM3v1Apb0Given :1; + unsigned BSIM3v1Apb1Given :1; + unsigned BSIM3v1Apalpha0Given :1; + unsigned BSIM3v1Apbeta0Given :1; + + /* CV model */ + unsigned BSIM3v1ApelmGiven :1; + unsigned BSIM3v1ApcgslGiven :1; + unsigned BSIM3v1ApcgdlGiven :1; + unsigned BSIM3v1ApckappaGiven :1; + unsigned BSIM3v1ApcfGiven :1; + unsigned BSIM3v1ApclcGiven :1; + unsigned BSIM3v1ApcleGiven :1; + + unsigned BSIM3v1AuseFringeGiven :1; + + unsigned BSIM3v1AtnomGiven :1; + unsigned BSIM3v1AcgsoGiven :1; + unsigned BSIM3v1AcgdoGiven :1; + unsigned BSIM3v1AcgboGiven :1; + unsigned BSIM3v1AxpartGiven :1; + unsigned BSIM3v1AsheetResistanceGiven :1; + unsigned BSIM3v1AjctSatCurDensityGiven :1; + unsigned BSIM3v1AbulkJctPotentialGiven :1; + unsigned BSIM3v1AbulkJctBotGradingCoeffGiven :1; + unsigned BSIM3v1AsidewallJctPotentialGiven :1; + unsigned BSIM3v1AbulkJctSideGradingCoeffGiven :1; + unsigned BSIM3v1AunitAreaJctCapGiven :1; + unsigned BSIM3v1AunitLengthSidewallJctCapGiven :1; + + unsigned BSIM3v1AoxideTrapDensityAGiven :1; + unsigned BSIM3v1AoxideTrapDensityBGiven :1; + unsigned BSIM3v1AoxideTrapDensityCGiven :1; + unsigned BSIM3v1AemGiven :1; + unsigned BSIM3v1AefGiven :1; + unsigned BSIM3v1AafGiven :1; + unsigned BSIM3v1AkfGiven :1; + + unsigned BSIM3v1ALintGiven :1; + unsigned BSIM3v1ALlGiven :1; + unsigned BSIM3v1ALlnGiven :1; + unsigned BSIM3v1ALwGiven :1; + unsigned BSIM3v1ALwnGiven :1; + unsigned BSIM3v1ALwlGiven :1; + unsigned BSIM3v1ALminGiven :1; + unsigned BSIM3v1ALmaxGiven :1; + + unsigned BSIM3v1AWintGiven :1; + unsigned BSIM3v1AWlGiven :1; + unsigned BSIM3v1AWlnGiven :1; + unsigned BSIM3v1AWwGiven :1; + unsigned BSIM3v1AWwnGiven :1; + unsigned BSIM3v1AWwlGiven :1; + unsigned BSIM3v1AWminGiven :1; + unsigned BSIM3v1AWmaxGiven :1; + +} BSIM3v1Amodel; + + +#ifndef NMOS +#define NMOS 1 +#define PMOS -1 +#endif /*NMOS*/ + + +/* device parameters */ +#define BSIM3v1A_W 1 +#define BSIM3v1A_L 2 +#define BSIM3v1A_M 15 +#define BSIM3v1A_AS 3 +#define BSIM3v1A_AD 4 +#define BSIM3v1A_PS 5 +#define BSIM3v1A_PD 6 +#define BSIM3v1A_NRS 7 +#define BSIM3v1A_NRD 8 +#define BSIM3v1A_OFF 9 +#define BSIM3v1A_IC_VBS 10 +#define BSIM3v1A_IC_VDS 11 +#define BSIM3v1A_IC_VGS 12 +#define BSIM3v1A_IC 13 +#define BSIM3v1A_NQSMOD 14 + +/* model parameters */ +#define BSIM3v1A_MOD_CAPMOD 101 +#define BSIM3v1A_MOD_NQSMOD 102 +#define BSIM3v1A_MOD_MOBMOD 103 +#define BSIM3v1A_MOD_NOIMOD 104 + +#define BSIM3v1A_MOD_TOX 105 + +#define BSIM3v1A_MOD_CDSC 106 +#define BSIM3v1A_MOD_CDSCB 107 +#define BSIM3v1A_MOD_CIT 108 +#define BSIM3v1A_MOD_NFACTOR 109 +#define BSIM3v1A_MOD_XJ 110 +#define BSIM3v1A_MOD_VSAT 111 +#define BSIM3v1A_MOD_AT 112 +#define BSIM3v1A_MOD_A0 113 +#define BSIM3v1A_MOD_A1 114 +#define BSIM3v1A_MOD_A2 115 +#define BSIM3v1A_MOD_KETA 116 +#define BSIM3v1A_MOD_NSUB 117 +#define BSIM3v1A_MOD_NPEAK 118 +#define BSIM3v1A_MOD_NGATE 120 +#define BSIM3v1A_MOD_GAMMA1 121 +#define BSIM3v1A_MOD_GAMMA2 122 +#define BSIM3v1A_MOD_VBX 123 +#define BSIM3v1A_MOD_BINUNIT 124 + +#define BSIM3v1A_MOD_VBM 125 + +#define BSIM3v1A_MOD_XT 126 +#define BSIM3v1A_MOD_K1 129 +#define BSIM3v1A_MOD_KT1 130 +#define BSIM3v1A_MOD_KT1L 131 +#define BSIM3v1A_MOD_K2 132 +#define BSIM3v1A_MOD_KT2 133 +#define BSIM3v1A_MOD_K3 134 +#define BSIM3v1A_MOD_K3B 135 +#define BSIM3v1A_MOD_W0 136 +#define BSIM3v1A_MOD_NLX 137 + +#define BSIM3v1A_MOD_DVT0 138 +#define BSIM3v1A_MOD_DVT1 139 +#define BSIM3v1A_MOD_DVT2 140 + +#define BSIM3v1A_MOD_DVT0W 141 +#define BSIM3v1A_MOD_DVT1W 142 +#define BSIM3v1A_MOD_DVT2W 143 + +#define BSIM3v1A_MOD_DROUT 144 +#define BSIM3v1A_MOD_DSUB 145 +#define BSIM3v1A_MOD_VTH0 146 +#define BSIM3v1A_MOD_UA 147 +#define BSIM3v1A_MOD_UA1 148 +#define BSIM3v1A_MOD_UB 149 +#define BSIM3v1A_MOD_UB1 150 +#define BSIM3v1A_MOD_UC 151 +#define BSIM3v1A_MOD_UC1 152 +#define BSIM3v1A_MOD_U0 153 +#define BSIM3v1A_MOD_UTE 154 +#define BSIM3v1A_MOD_VOFF 155 +#define BSIM3v1A_MOD_DELTA 156 +#define BSIM3v1A_MOD_RDSW 157 +#define BSIM3v1A_MOD_PRT 158 +#define BSIM3v1A_MOD_LDD 159 +#define BSIM3v1A_MOD_ETA 160 +#define BSIM3v1A_MOD_ETA0 161 +#define BSIM3v1A_MOD_ETAB 162 +#define BSIM3v1A_MOD_PCLM 163 +#define BSIM3v1A_MOD_PDIBL1 164 +#define BSIM3v1A_MOD_PDIBL2 165 +#define BSIM3v1A_MOD_PSCBE1 166 +#define BSIM3v1A_MOD_PSCBE2 167 +#define BSIM3v1A_MOD_PVAG 168 +#define BSIM3v1A_MOD_WR 169 +#define BSIM3v1A_MOD_DWG 170 +#define BSIM3v1A_MOD_DWB 171 +#define BSIM3v1A_MOD_B0 172 +#define BSIM3v1A_MOD_B1 173 +#define BSIM3v1A_MOD_ALPHA0 174 +#define BSIM3v1A_MOD_BETA0 175 +#define BSIM3v1A_MOD_PDIBLB 178 + +#define BSIM3v1A_MOD_PRWG 179 +#define BSIM3v1A_MOD_PRWB 180 + +#define BSIM3v1A_MOD_CDSCD 181 +#define BSIM3v1A_MOD_AGS 182 + +#define BSIM3v1A_MOD_FRINGE 184 +#define BSIM3v1A_MOD_ELM 185 +#define BSIM3v1A_MOD_CGSL 186 +#define BSIM3v1A_MOD_CGDL 187 +#define BSIM3v1A_MOD_CKAPPA 188 +#define BSIM3v1A_MOD_CF 189 +#define BSIM3v1A_MOD_CLC 190 +#define BSIM3v1A_MOD_CLE 191 + +/* Length dependence */ +#define BSIM3v1A_MOD_LCDSC 201 +#define BSIM3v1A_MOD_LCDSCB 202 +#define BSIM3v1A_MOD_LCIT 203 +#define BSIM3v1A_MOD_LNFACTOR 204 +#define BSIM3v1A_MOD_LXJ 205 +#define BSIM3v1A_MOD_LVSAT 206 +#define BSIM3v1A_MOD_LAT 207 +#define BSIM3v1A_MOD_LA0 208 +#define BSIM3v1A_MOD_LA1 209 +#define BSIM3v1A_MOD_LA2 210 +#define BSIM3v1A_MOD_LKETA 211 +#define BSIM3v1A_MOD_LNSUB 212 +#define BSIM3v1A_MOD_LNPEAK 213 +#define BSIM3v1A_MOD_LNGATE 215 +#define BSIM3v1A_MOD_LGAMMA1 216 +#define BSIM3v1A_MOD_LGAMMA2 217 +#define BSIM3v1A_MOD_LVBX 218 + +#define BSIM3v1A_MOD_LVBM 220 + +#define BSIM3v1A_MOD_LXT 222 +#define BSIM3v1A_MOD_LK1 225 +#define BSIM3v1A_MOD_LKT1 226 +#define BSIM3v1A_MOD_LKT1L 227 +#define BSIM3v1A_MOD_LK2 228 +#define BSIM3v1A_MOD_LKT2 229 +#define BSIM3v1A_MOD_LK3 230 +#define BSIM3v1A_MOD_LK3B 231 +#define BSIM3v1A_MOD_LW0 232 +#define BSIM3v1A_MOD_LNLX 233 + +#define BSIM3v1A_MOD_LDVT0 234 +#define BSIM3v1A_MOD_LDVT1 235 +#define BSIM3v1A_MOD_LDVT2 236 + +#define BSIM3v1A_MOD_LDVT0W 237 +#define BSIM3v1A_MOD_LDVT1W 238 +#define BSIM3v1A_MOD_LDVT2W 239 + +#define BSIM3v1A_MOD_LDROUT 240 +#define BSIM3v1A_MOD_LDSUB 241 +#define BSIM3v1A_MOD_LVTH0 242 +#define BSIM3v1A_MOD_LUA 243 +#define BSIM3v1A_MOD_LUA1 244 +#define BSIM3v1A_MOD_LUB 245 +#define BSIM3v1A_MOD_LUB1 246 +#define BSIM3v1A_MOD_LUC 247 +#define BSIM3v1A_MOD_LUC1 248 +#define BSIM3v1A_MOD_LU0 249 +#define BSIM3v1A_MOD_LUTE 250 +#define BSIM3v1A_MOD_LVOFF 251 +#define BSIM3v1A_MOD_LDELTA 252 +#define BSIM3v1A_MOD_LRDSW 253 +#define BSIM3v1A_MOD_LPRT 254 +#define BSIM3v1A_MOD_LLDD 255 +#define BSIM3v1A_MOD_LETA 256 +#define BSIM3v1A_MOD_LETA0 257 +#define BSIM3v1A_MOD_LETAB 258 +#define BSIM3v1A_MOD_LPCLM 259 +#define BSIM3v1A_MOD_LPDIBL1 260 +#define BSIM3v1A_MOD_LPDIBL2 261 +#define BSIM3v1A_MOD_LPSCBE1 262 +#define BSIM3v1A_MOD_LPSCBE2 263 +#define BSIM3v1A_MOD_LPVAG 264 +#define BSIM3v1A_MOD_LWR 265 +#define BSIM3v1A_MOD_LDWG 266 +#define BSIM3v1A_MOD_LDWB 267 +#define BSIM3v1A_MOD_LB0 268 +#define BSIM3v1A_MOD_LB1 269 +#define BSIM3v1A_MOD_LALPHA0 270 +#define BSIM3v1A_MOD_LBETA0 271 +#define BSIM3v1A_MOD_LPDIBLB 274 + +#define BSIM3v1A_MOD_LPRWG 275 +#define BSIM3v1A_MOD_LPRWB 276 + +#define BSIM3v1A_MOD_LCDSCD 277 +#define BSIM3v1A_MOD_LAGS 278 + + +#define BSIM3v1A_MOD_LFRINGE 281 +#define BSIM3v1A_MOD_LELM 282 +#define BSIM3v1A_MOD_LCGSL 283 +#define BSIM3v1A_MOD_LCGDL 284 +#define BSIM3v1A_MOD_LCKAPPA 285 +#define BSIM3v1A_MOD_LCF 286 +#define BSIM3v1A_MOD_LCLC 287 +#define BSIM3v1A_MOD_LCLE 288 + +/* Width dependence */ +#define BSIM3v1A_MOD_WCDSC 301 +#define BSIM3v1A_MOD_WCDSCB 302 +#define BSIM3v1A_MOD_WCIT 303 +#define BSIM3v1A_MOD_WNFACTOR 304 +#define BSIM3v1A_MOD_WXJ 305 +#define BSIM3v1A_MOD_WVSAT 306 +#define BSIM3v1A_MOD_WAT 307 +#define BSIM3v1A_MOD_WA0 308 +#define BSIM3v1A_MOD_WA1 309 +#define BSIM3v1A_MOD_WA2 310 +#define BSIM3v1A_MOD_WKETA 311 +#define BSIM3v1A_MOD_WNSUB 312 +#define BSIM3v1A_MOD_WNPEAK 313 +#define BSIM3v1A_MOD_WNGATE 315 +#define BSIM3v1A_MOD_WGAMMA1 316 +#define BSIM3v1A_MOD_WGAMMA2 317 +#define BSIM3v1A_MOD_WVBX 318 + +#define BSIM3v1A_MOD_WVBM 320 + +#define BSIM3v1A_MOD_WXT 322 +#define BSIM3v1A_MOD_WK1 325 +#define BSIM3v1A_MOD_WKT1 326 +#define BSIM3v1A_MOD_WKT1L 327 +#define BSIM3v1A_MOD_WK2 328 +#define BSIM3v1A_MOD_WKT2 329 +#define BSIM3v1A_MOD_WK3 330 +#define BSIM3v1A_MOD_WK3B 331 +#define BSIM3v1A_MOD_WW0 332 +#define BSIM3v1A_MOD_WNLX 333 + +#define BSIM3v1A_MOD_WDVT0 334 +#define BSIM3v1A_MOD_WDVT1 335 +#define BSIM3v1A_MOD_WDVT2 336 + +#define BSIM3v1A_MOD_WDVT0W 337 +#define BSIM3v1A_MOD_WDVT1W 338 +#define BSIM3v1A_MOD_WDVT2W 339 + +#define BSIM3v1A_MOD_WDROUT 340 +#define BSIM3v1A_MOD_WDSUB 341 +#define BSIM3v1A_MOD_WVTH0 342 +#define BSIM3v1A_MOD_WUA 343 +#define BSIM3v1A_MOD_WUA1 344 +#define BSIM3v1A_MOD_WUB 345 +#define BSIM3v1A_MOD_WUB1 346 +#define BSIM3v1A_MOD_WUC 347 +#define BSIM3v1A_MOD_WUC1 348 +#define BSIM3v1A_MOD_WU0 349 +#define BSIM3v1A_MOD_WUTE 350 +#define BSIM3v1A_MOD_WVOFF 351 +#define BSIM3v1A_MOD_WDELTA 352 +#define BSIM3v1A_MOD_WRDSW 353 +#define BSIM3v1A_MOD_WPRT 354 +#define BSIM3v1A_MOD_WLDD 355 +#define BSIM3v1A_MOD_WETA 356 +#define BSIM3v1A_MOD_WETA0 357 +#define BSIM3v1A_MOD_WETAB 358 +#define BSIM3v1A_MOD_WPCLM 359 +#define BSIM3v1A_MOD_WPDIBL1 360 +#define BSIM3v1A_MOD_WPDIBL2 361 +#define BSIM3v1A_MOD_WPSCBE1 362 +#define BSIM3v1A_MOD_WPSCBE2 363 +#define BSIM3v1A_MOD_WPVAG 364 +#define BSIM3v1A_MOD_WWR 365 +#define BSIM3v1A_MOD_WDWG 366 +#define BSIM3v1A_MOD_WDWB 367 +#define BSIM3v1A_MOD_WB0 368 +#define BSIM3v1A_MOD_WB1 369 +#define BSIM3v1A_MOD_WALPHA0 370 +#define BSIM3v1A_MOD_WBETA0 371 +#define BSIM3v1A_MOD_WPDIBLB 374 + +#define BSIM3v1A_MOD_WPRWG 375 +#define BSIM3v1A_MOD_WPRWB 376 + +#define BSIM3v1A_MOD_WCDSCD 377 +#define BSIM3v1A_MOD_WAGS 378 + + +#define BSIM3v1A_MOD_WFRINGE 381 +#define BSIM3v1A_MOD_WELM 382 +#define BSIM3v1A_MOD_WCGSL 383 +#define BSIM3v1A_MOD_WCGDL 384 +#define BSIM3v1A_MOD_WCKAPPA 385 +#define BSIM3v1A_MOD_WCF 386 +#define BSIM3v1A_MOD_WCLC 387 +#define BSIM3v1A_MOD_WCLE 388 + +/* Cross-term dependence */ +#define BSIM3v1A_MOD_PCDSC 401 +#define BSIM3v1A_MOD_PCDSCB 402 +#define BSIM3v1A_MOD_PCIT 403 +#define BSIM3v1A_MOD_PNFACTOR 404 +#define BSIM3v1A_MOD_PXJ 405 +#define BSIM3v1A_MOD_PVSAT 406 +#define BSIM3v1A_MOD_PAT 407 +#define BSIM3v1A_MOD_PA0 408 +#define BSIM3v1A_MOD_PA1 409 +#define BSIM3v1A_MOD_PA2 410 +#define BSIM3v1A_MOD_PKETA 411 +#define BSIM3v1A_MOD_PNSUB 412 +#define BSIM3v1A_MOD_PNPEAK 413 +#define BSIM3v1A_MOD_PNGATE 415 +#define BSIM3v1A_MOD_PGAMMA1 416 +#define BSIM3v1A_MOD_PGAMMA2 417 +#define BSIM3v1A_MOD_PVBX 418 + +#define BSIM3v1A_MOD_PVBM 420 + +#define BSIM3v1A_MOD_PXT 422 +#define BSIM3v1A_MOD_PK1 425 +#define BSIM3v1A_MOD_PKT1 426 +#define BSIM3v1A_MOD_PKT1L 427 +#define BSIM3v1A_MOD_PK2 428 +#define BSIM3v1A_MOD_PKT2 429 +#define BSIM3v1A_MOD_PK3 430 +#define BSIM3v1A_MOD_PK3B 431 +#define BSIM3v1A_MOD_PW0 432 +#define BSIM3v1A_MOD_PNLX 433 + +#define BSIM3v1A_MOD_PDVT0 434 +#define BSIM3v1A_MOD_PDVT1 435 +#define BSIM3v1A_MOD_PDVT2 436 + +#define BSIM3v1A_MOD_PDVT0W 437 +#define BSIM3v1A_MOD_PDVT1W 438 +#define BSIM3v1A_MOD_PDVT2W 439 + +#define BSIM3v1A_MOD_PDROUT 440 +#define BSIM3v1A_MOD_PDSUB 441 +#define BSIM3v1A_MOD_PVTH0 442 +#define BSIM3v1A_MOD_PUA 443 +#define BSIM3v1A_MOD_PUA1 444 +#define BSIM3v1A_MOD_PUB 445 +#define BSIM3v1A_MOD_PUB1 446 +#define BSIM3v1A_MOD_PUC 447 +#define BSIM3v1A_MOD_PUC1 448 +#define BSIM3v1A_MOD_PU0 449 +#define BSIM3v1A_MOD_PUTE 450 +#define BSIM3v1A_MOD_PVOFF 451 +#define BSIM3v1A_MOD_PDELTA 452 +#define BSIM3v1A_MOD_PRDSW 453 +#define BSIM3v1A_MOD_PPRT 454 +#define BSIM3v1A_MOD_PLDD 455 +#define BSIM3v1A_MOD_PETA 456 +#define BSIM3v1A_MOD_PETA0 457 +#define BSIM3v1A_MOD_PETAB 458 +#define BSIM3v1A_MOD_PPCLM 459 +#define BSIM3v1A_MOD_PPDIBL1 460 +#define BSIM3v1A_MOD_PPDIBL2 461 +#define BSIM3v1A_MOD_PPSCBE1 462 +#define BSIM3v1A_MOD_PPSCBE2 463 +#define BSIM3v1A_MOD_PPVAG 464 +#define BSIM3v1A_MOD_PWR 465 +#define BSIM3v1A_MOD_PDWG 466 +#define BSIM3v1A_MOD_PDWB 467 +#define BSIM3v1A_MOD_PB0 468 +#define BSIM3v1A_MOD_PB1 469 +#define BSIM3v1A_MOD_PALPHA0 470 +#define BSIM3v1A_MOD_PBETA0 471 +#define BSIM3v1A_MOD_PPDIBLB 474 + +#define BSIM3v1A_MOD_PPRWG 475 +#define BSIM3v1A_MOD_PPRWB 476 + +#define BSIM3v1A_MOD_PCDSCD 477 +#define BSIM3v1A_MOD_PAGS 478 + +#define BSIM3v1A_MOD_PFRINGE 481 +#define BSIM3v1A_MOD_PELM 482 +#define BSIM3v1A_MOD_PCGSL 483 +#define BSIM3v1A_MOD_PCGDL 484 +#define BSIM3v1A_MOD_PCKAPPA 485 +#define BSIM3v1A_MOD_PCF 486 +#define BSIM3v1A_MOD_PCLC 487 +#define BSIM3v1A_MOD_PCLE 488 + +#define BSIM3v1A_MOD_TNOM 501 +#define BSIM3v1A_MOD_CGSO 502 +#define BSIM3v1A_MOD_CGDO 503 +#define BSIM3v1A_MOD_CGBO 504 +#define BSIM3v1A_MOD_XPART 505 + +#define BSIM3v1A_MOD_RSH 506 +#define BSIM3v1A_MOD_JS 507 +#define BSIM3v1A_MOD_PB 508 +#define BSIM3v1A_MOD_MJ 509 +#define BSIM3v1A_MOD_PBSW 510 +#define BSIM3v1A_MOD_MJSW 511 +#define BSIM3v1A_MOD_CJ 512 +#define BSIM3v1A_MOD_CJSW 513 +#define BSIM3v1A_MOD_NMOS 514 +#define BSIM3v1A_MOD_PMOS 515 + +#define BSIM3v1A_MOD_NOIA 516 +#define BSIM3v1A_MOD_NOIB 517 +#define BSIM3v1A_MOD_NOIC 518 + +#define BSIM3v1A_MOD_LINT 519 +#define BSIM3v1A_MOD_LL 520 +#define BSIM3v1A_MOD_LLN 521 +#define BSIM3v1A_MOD_LW 522 +#define BSIM3v1A_MOD_LWN 523 +#define BSIM3v1A_MOD_LWL 524 +#define BSIM3v1A_MOD_LMIN 525 +#define BSIM3v1A_MOD_LMAX 526 + +#define BSIM3v1A_MOD_WINT 527 +#define BSIM3v1A_MOD_WL 528 +#define BSIM3v1A_MOD_WLN 529 +#define BSIM3v1A_MOD_WW 530 +#define BSIM3v1A_MOD_WWN 531 +#define BSIM3v1A_MOD_WWL 532 +#define BSIM3v1A_MOD_WMIN 533 +#define BSIM3v1A_MOD_WMAX 534 + +#define BSIM3v1A_MOD_DWC 535 +#define BSIM3v1A_MOD_DLC 536 + +#define BSIM3v1A_MOD_EM 537 +#define BSIM3v1A_MOD_EF 538 +#define BSIM3v1A_MOD_AF 539 +#define BSIM3v1A_MOD_KF 540 + + +/* device questions */ +#define BSIM3v1A_DNODE 601 +#define BSIM3v1A_GNODE 602 +#define BSIM3v1A_SNODE 603 +#define BSIM3v1A_BNODE 604 +#define BSIM3v1A_DNODEPRIME 605 +#define BSIM3v1A_SNODEPRIME 606 +#define BSIM3v1A_VBD 607 +#define BSIM3v1A_VBS 608 +#define BSIM3v1A_VGS 609 +#define BSIM3v1A_VDS 610 +#define BSIM3v1A_CD 611 +#define BSIM3v1A_CBS 612 +#define BSIM3v1A_CBD 613 +#define BSIM3v1A_GM 614 +#define BSIM3v1A_GDS 615 +#define BSIM3v1A_GMBS 616 +#define BSIM3v1A_GBD 617 +#define BSIM3v1A_GBS 618 +#define BSIM3v1A_QB 619 +#define BSIM3v1A_CQB 620 +#define BSIM3v1A_QG 621 +#define BSIM3v1A_CQG 622 +#define BSIM3v1A_QD 623 +#define BSIM3v1A_CQD 624 +#define BSIM3v1A_CGG 625 +#define BSIM3v1A_CGD 626 +#define BSIM3v1A_CGS 627 +#define BSIM3v1A_CBG 628 +#define BSIM3v1A_CAPBD 629 +#define BSIM3v1A_CQBD 630 +#define BSIM3v1A_CAPBS 631 +#define BSIM3v1A_CQBS 632 +#define BSIM3v1A_CDG 633 +#define BSIM3v1A_CDD 634 +#define BSIM3v1A_CDS 635 +#define BSIM3v1A_VON 636 +#define BSIM3v1A_VDSAT 637 +#define BSIM3v1A_QBS 638 +#define BSIM3v1A_QBD 639 +#define BSIM3v1A_SOURCECONDUCT 640 +#define BSIM3v1A_DRAINCONDUCT 641 +#define BSIM3v1A_CBDB 642 +#define BSIM3v1A_CBSB 643 + +#include "bsim3v1aext.h" + +extern void BSIM3v1Aevaluate(double,double,double,BSIM3v1Ainstance*,BSIM3v1Amodel*, + double*,double*,double*, double*, double*, double*, double*, + double*, double*, double*, double*, double*, double*, double*, + double*, double*, double*, double*, CKTcircuit*); +#endif /*BSIM3v1A*/ + + + diff --git a/src/spicelib/devices/bsim3v1a/bsim3v1aext.h b/src/spicelib/devices/bsim3v1a/bsim3v1aext.h new file mode 100644 index 000000000..7eb516d6b --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/bsim3v1aext.h @@ -0,0 +1,30 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1991 JianHui Huang and Min-Chie Jeng. +Modified by Paolo Nenzi 2002 +File: bsim3v1aext.h +**********/ + +extern int BSIM3v1AacLoad(GENmodel *,CKTcircuit*); +extern int BSIM3v1Aask(CKTcircuit *,GENinstance*,int,IFvalue*,IFvalue*); +extern int BSIM3v1AconvTest(GENmodel *,CKTcircuit*); +extern int BSIM3v1Adelete(GENmodel*,IFuid,GENinstance**); +extern void BSIM3v1Adestroy(GENmodel**); +extern int BSIM3v1Agetic(GENmodel*,CKTcircuit*); +extern int BSIM3v1Aload(GENmodel*,CKTcircuit*); +extern int BSIM3v1AmAsk(CKTcircuit*,GENmodel *,int, IFvalue*); +extern int BSIM3v1AmDelete(GENmodel**,IFuid,GENmodel*); +extern int BSIM3v1AmParam(int,IFvalue*,GENmodel*); +extern void BSIM3v1AmosCap(CKTcircuit*, double, double, double, double, + double, double, double, double, double, double, double, + double, double, double, double, double, double, double*, + double*, double*, double*, double*, double*, double*, double*, + double*, double*, double*, double*, double*, double*, double*, + double*); +extern int BSIM3v1Aparam(int,IFvalue*,GENinstance*,IFvalue*); +extern int BSIM3v1ApzLoad(GENmodel*,CKTcircuit*,SPcomplex*); +extern int BSIM3v1Asetup(SMPmatrix*,GENmodel*,CKTcircuit*,int*); +extern int BSIM3v1Atemp(GENmodel*,CKTcircuit*); +extern int BSIM3v1Atrunc(GENmodel*,CKTcircuit*,double*); +extern int BSIM3v1Anoise(int,int,GENmodel*,CKTcircuit*,Ndata*,double*); +extern int BSIM3v1Aunsetup(GENmodel *, CKTcircuit *); diff --git a/src/spicelib/devices/bsim3v1a/bsim3v1ainit.c b/src/spicelib/devices/bsim3v1a/bsim3v1ainit.c new file mode 100644 index 000000000..da2a66bfc --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/bsim3v1ainit.c @@ -0,0 +1,85 @@ +#include + +#include + +#include "bsim3v1aitf.h" +#include "bsim3v1aext.h" +#include "bsim3v1ainit.h" + + +SPICEdev B3v1Ainfo = { + { + "BSIM3v1A", + "Berkeley Short Channel IGFET Model Version-3 (3.1 Alan)", + + &BSIM3v1AnSize, + &BSIM3v1AnSize, + BSIM3v1Anames, + + &BSIM3v1ApTSize, + BSIM3v1ApTable, + + &BSIM3v1AmPTSize, + BSIM3v1AmPTable, + +#ifdef XSPICE +/*---- Fixed by SDB 5.2.2003 to enable XSPICE/tclspice integration -----*/ + NULL, /* This is a SPICE device, it has no MIF info data */ + + 0, /* This is a SPICE device, it has no MIF info data */ + NULL, /* This is a SPICE device, it has no MIF info data */ + + 0, /* This is a SPICE device, it has no MIF info data */ + NULL, /* This is a SPICE device, it has no MIF info data */ + + 0, /* This is a SPICE device, it has no MIF info data */ + NULL, /* This is a SPICE device, it has no MIF info data */ +/*--------------------------- End of SDB fix -------------------------*/ +#endif + + DEV_DEFAULT, + + }, + + DEVparam : BSIM3v1Aparam, + DEVmodParam : BSIM3v1AmParam, + DEVload : BSIM3v1Aload, + DEVsetup : BSIM3v1Asetup, + DEVunsetup : BSIM3v1Aunsetup, + DEVpzSetup : BSIM3v1Asetup, + DEVtemperature: BSIM3v1Atemp, + DEVtrunc : BSIM3v1Atrunc, + DEVfindBranch : NULL, + DEVacLoad : BSIM3v1AacLoad, + DEVaccept : NULL, + DEVdestroy : BSIM3v1Adestroy, + DEVmodDelete : BSIM3v1AmDelete, + DEVdelete : BSIM3v1Adelete, + DEVsetic : BSIM3v1Agetic, + DEVask : BSIM3v1Aask, + DEVmodAsk : BSIM3v1AmAsk, + DEVpzLoad : BSIM3v1ApzLoad, + DEVconvTest : BSIM3v1AconvTest, + DEVsenSetup : NULL, + DEVsenLoad : NULL, + DEVsenUpdate : NULL, + DEVsenAcLoad : NULL, + DEVsenPrint : NULL, + DEVsenTrunc : NULL, + DEVdisto : NULL, + DEVnoise : BSIM3v1Anoise, +#ifdef CIDER + DEVdump : NULL, + DEVacct : NULL, +#endif + DEVinstSize : &BSIM3v1AiSize, + DEVmodSize : &BSIM3v1AmSize + +}; + + +SPICEdev * +get_bsim3v1a_info(void) +{ + return &B3v1Ainfo; +} diff --git a/src/spicelib/devices/bsim3v1a/bsim3v1ainit.h b/src/spicelib/devices/bsim3v1a/bsim3v1ainit.h new file mode 100644 index 000000000..7d89f0dce --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/bsim3v1ainit.h @@ -0,0 +1,13 @@ +#ifndef _BSIM3v1AINIT_H +#define _BSIM3v1AINIT_H + +extern IFparm BSIM3v1ApTable[ ]; +extern IFparm BSIM3v1AmPTable[ ]; +extern char *BSIM3v1Anames[ ]; +extern int BSIM3v1ApTSize; +extern int BSIM3v1AmPTSize; +extern int BSIM3v1AnSize; +extern int BSIM3v1AiSize; +extern int BSIM3v1AmSize; + +#endif diff --git a/src/spicelib/devices/bsim3v1a/bsim3v1aitf.h b/src/spicelib/devices/bsim3v1a/bsim3v1aitf.h new file mode 100644 index 000000000..bd6c79cd6 --- /dev/null +++ b/src/spicelib/devices/bsim3v1a/bsim3v1aitf.h @@ -0,0 +1,14 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1991 JianHui Huang and Min-Chie Jeng. +Modified by Paolo Nenzi 2002 +File: bsim3itf.h +**********/ + +#ifndef DEV_BSIM3v1A +#define DEV_BSIM3v1A + +SPICEdev *get_bsim3v1a_info(void); + +#endif +