electrical tnode `P(info="local temperature rise node");
branch (ci,c) irescx;
branch (ci,c) vrescx;
branch (ei,e) iresex;
branch (ei,e) vresex;
branch (b,bi) irescb;
branch (b,bi) vrescb;
electrical tnode `P(info="local temperature rise node");
//Branch definitions
branch (ci,c) br_cic_i;
branch (ci,c) br_cic_v;
branch (ei,e) br_eie_i;
branch (ei,e) br_eie_v;
branch (bi,ei) br_biei;
branch (bi,ci) br_bici;
branch (ci,ei) br_ciei;
branch (b,bi) br_bbi_i;
branch (b,bi) br_bbi_v;
branch (b,e) br_be;
branch (b,ci) br_bci;
branch (b,s) br_bs;
branch (s,ci) br_sci;
branch (tnode ) br_sht;
//
// Parameter initialization with default values
@ -258,14 +286,16 @@ module hic0_full (c,b,e,s);
parameter real rbi0 = 0.0 from [0:`INF) `P(spice:name="rbi0" info="Internal base resistance at zero-bias" test:value="100" unit="Ohm" m:inverse_factor="yes");
parameter real vr0e = 2.5 from (0:`INF] `P(spice:name="vr0e" info="forward Early voltage (normalization volt.)" unit="V");
parameter real vr0c = `INF from (0:`INF] `P(spice:name="vr0c" info="forward Early voltage (normalization volt.)" unit="V" default="infinity" test:value="25.0");
parameter real fgeo = 0.656 from [0:1] `P(spice:name="fgeo" info="Geometry factor" test:value="0.73");
parameter real fgeo = 0.656 from [0:`INF] `P(spice:name="fgeo" info="Geometry factor" test:value="0.73");
// Series resistances
parameter real rbx = 0.0 from [0:`INF) `P(spice:name="rbx" info="External base series resistance" test:value="8.8" unit="Ohm" m:inverse_factor="yes");
parameter real rcx = 0.0 from [0:`INF) `P(spice:name="rcx" info="Emitter series resistance" test:value="12.5" unit="Ohm" m:inverse_factor="yes");
parameter real re = 0.0 from [0:`INF) `P(spice:name="re" info="External collector series resistance" test:value="9.16" unit="Ohm" m:inverse_factor="yes");
// Substrate diode current and cap
// Substrate transfer current, diode current and cap
parameter real itss = 0.0 from [0:1.0] `P(spice:name="itss" info="Substrate transistor transfer saturation current" unit="A" test:value="1e-17" m:factor="yes");
parameter real msf = 1.0 from (0:10] `P(spice:name="msf" info="Substrate transistor transfer current non-ideality factor");
parameter real iscs = 0.0 from [0:1.0] `P(spice:name="iscs" info="SC saturation current" unit="A" test:value="1e-17" m:factor="yes");
parameter real msc = 1.0 from (0:10] `P(spice:name="msc" info="SC non-ideality factor");
parameter real cjs0 = 1.0e-20 from [0:`INF) `P(spice:name="cjs0" info="Zero-bias SC depletion capacitance" unit="F" test:value="1e-15" m:factor="yes");
@ -307,6 +337,7 @@ module hic0_full (c,b,e,s);
parameter real aleav = 0.0 `P(spice:name="aleav" info="TC of avalanche exponential factor" unit="1/K");
// Self-heating
parameter integer flsh = 0 from [0:2] `P(spice:name="flsh" info="Flag for self-heating calculation" test:value="2");
parameter real rth = 0.0 from [0:`INF) `P(spice:name="rth" info="Thermal resistance" test:value="200.0" unit="K/W" m:inverse_factor="yes");
parameter real cth = 0.0 from [0:`INF) `P(spice:name="cth" info="Thermal capacitance" test:value="0.1" unit="Ws/K" m:factor="yes");
@ -344,21 +375,21 @@ module hic0_full (c,b,e,s);
real VT,Tamb,Tdev,Tnom,dT,qtt0,ln_qtt0;
real vde_t,vdci_t,vdcx_t,vds_t;
real is_t,ires_t,ibes_t,ibcs_t;
real iscs_t,cje0_t,cjci0_t,cjcx0_t;
real itss_t,iscs_t,cje0_t,cjci0_t,cjcx0_t;
real cjs0_t,rci0_t,vlim_t;
real vces_t,thcs_t,tef0_t,rbi0_t;
real rbx_t,rcx_t,re_t,t0_t,eavl_t,kavl_t;
real aje_t,ajci_t,ajcx_t,ajs_t;
real aje_t;
// bc charge and cap
real qjci `P(ask="yes" info="B-C internal junction charge" unit="C");
real qjcx,qjcii,cjcii,qjcxi,qjciii; //cjcx
real cjci0_t_ii,cjcx0_t_ii,cjcx0_t_i;
real cjci0_t_ii,cjcx0_t_ii,cjcx0_t_i,v_j;
// be junction
real qjei `P(ask="yes" info="B-E internal junction charge" unit="C");
real cjei `P(ask="yes" info="B-E internal junction capacitance" unit="F");
real vf,vj,x,y,e1,e2;
real cjei_i `P(ask="yes" info="B-E internal junction capacitance" unit="F"); // dw: adms2.2.7 problem
real cjei,vf,vj,x,y,e1,e2;
// transfer and internal base current
real cc,qj_2,facl;
@ -380,10 +411,10 @@ module hic0_full (c,b,e,s);
real v_bord,a_iavl,lncc;
// base resistance
real rb,ri,eta,fac_ri,rbi,qje;
real rb,eta,rbi,qje,Qz_nom,fQz;
// substrate diode and cap
real qjs;
// substrate transistor, diode and cap
real qjs,HSa,HSb,HSI_Tsu,HSUM;
// self heating
real pterm;
@ -403,7 +434,7 @@ module hic0_full (c,b,e,s);
real IS,IST,UM1,U,Iz,DIOY;
// branch voltages
real Vbci,Vbici,Vbiei,Vciei,Vsci,Veie,Vbbi,Vcic,Vbe,Vrth, Vrth_ext;
real Vbci,Vbici,Vbiei,Vciei,Vsci,Veie,Vbbi,Vcic,Vbe,Vrth;
//Output to be seen
real ijbc `P(ask="yes" info="Base-collector diode current" unit="A");
@ -437,16 +468,16 @@ analog begin
HICUMtype = `NPN;
end
Vbci = HICUMtype*V(b,ci);
Vbici = HICUMtype*V(bi,ci);
Vbiei = HICUMtype*V(bi,ei);
Vciei = HICUMtype*V(ci,ei);
Vsci = HICUMtype*V(s,ci);
Veie = V(vresex);
Vcic = V(vrescx);
Vbbi = V(vrescb);
Vbe = HICUMtype*V(b,e);
Vrth = V(tnode);
Vbci = HICUMtype*V(br_bci);
Vbici = HICUMtype*V(br_bici);
Vbiei = HICUMtype*V(br_biei);
Vciei = HICUMtype*V(br_ciei);
Vsci = HICUMtype*V(br_sci);
Veie = V(br_eie_v);
Vcic = V(br_cic_v);
Vbbi = V(br_bbi_v);
Vbe = HICUMtype*V(br_be);
Vrth = V(br_sht);
@ -456,14 +487,16 @@ analog begin
Tnom = tnom+273.15;
Tamb = $temperature;
Tdev = Tamb+dt+Vrth; // selfheating instead dT later possible