diff --git a/examples/xspice/pll/README b/examples/xspice/pll/README index 9bcabf571..f5c38b393 100644 --- a/examples/xspice/pll/README +++ b/examples/xspice/pll/README @@ -1,11 +1,32 @@ This directory contains a mixed mode pll, combining ngspice and XSPICE circuit blocks. The pll consists of the following blocks: -voltage controlled oscillator: vco_sub.cir -digital divider and frequency reference: pll-xspice.cir -phase frequency detector: f-p-det-d-sub.cir -loop filter: loop-filter.cir -main simulation control: pll-xspice.cir + +** voltage controlled oscillator: +vco_sub.cir + 7 stage ring oscillator with gain cells, CMOS devices +or +vco_sub_new.cir + vco made from code model d_osc, cntl_array/freq_array data + are gained by running test-vco.cir with vco_sub.cir + +** digital divider and frequency reference: +pll-xspice.cir + +** phase frequency detector: +f-p-det-d-sub.cir + +** loop filter: +loop-filter.cir + switched current sources as charge pump, 2nd order + passive RC filter +or +loop-filter-2.cir + transistors as switches for charge pump, 2nd or 3rd + order passive RC filters + +** main simulation control: +pll-xspice.cir Two test files are included: test-vco.cir simulates vco frequency versus control voltage @@ -15,3 +36,4 @@ The main building blocks are organised as subcircuits. main simulation control with three reference frequencies: pll-xspice-fstep.cir + simulates two steps of the reference in one simulation run diff --git a/examples/xspice/pll/loop-filter-2.cir b/examples/xspice/pll/loop-filter-2.cir new file mode 100644 index 000000000..3d0931676 --- /dev/null +++ b/examples/xspice/pll/loop-filter-2.cir @@ -0,0 +1,50 @@ +* loop filter for pll +* in: d_up d_down digital data +* out: vout, vco control voltage +* using transistors to switch current +* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm +* digital input d_Un d_D +* anlog output vout + + +.subckt loopf d_Un d_D vout + +.param initcond=2.5 + +vdd dd 0 dc 'vcc' +vss ss 0 dc 0 + +* "driver" circuit, digital in, analog out +abridge-f1 [d_Un d_D] [u1n d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 'vcc' out_undef = 'vcc/2' ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +* uses BSIM3 model parameters from pll-xspice_2.cir +* transistors as switches +mnd dra d1 ss ss n1 w=12u l=0.35u AS=24p AD=24p PS=28u PD=28u +mpd dra u1n dd dd p1 w=24u l=0.35u AS=48p AD=48p PS=52u PD=52u + +*** passive filter elements *** +*third order filter +*parameters absolutely _not_ optimised +*better check +* http://www.national.com/assets/en/boards/deansbook4.pdf +*to do so +.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(int1)='initcond' v(u1n)='vcc' v(d1)=0 +R1 dra int1 300 +R2 int1 c1 200 +C1 c1 0 10n +C2 int1 0 5n +R3 int1 vout 50 +C3 vout 0 0.5n + +*second order filter +*parameters not optimized +*.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(u1n)='vcc' v(d1)=0 +*R1 dra vout 300 +*R2 vout c1 200 +*C1 c1 0 10n +*C2 vout 0 5n + +.ends loopf diff --git a/examples/xspice/pll/loop-filter.cir b/examples/xspice/pll/loop-filter.cir index ac1ebc00f..a83ebb7ab 100644 --- a/examples/xspice/pll/loop-filter.cir +++ b/examples/xspice/pll/loop-filter.cir @@ -3,7 +3,7 @@ * out: vout, vco control voltage * according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm -.subckt loopf d_U d_D vout +.subckt loopfe d_U d_D vout .param loadcur=5m .param initcond=2.5 diff --git a/examples/xspice/pll/pll-xspice-fstep.cir b/examples/xspice/pll/pll-xspice-fstep.cir index e538753e2..23ebb0141 100644 --- a/examples/xspice/pll/pll-xspice-fstep.cir +++ b/examples/xspice/pll/pll-xspice-fstep.cir @@ -31,11 +31,13 @@ ainv1 d_d0 d_d1 invd1 * vco .include vco_sub.cir +.include vco_sub_new.cir * buf: analog out * d_digout: digital out * cont: analog control voltage * dd: analog supply voltage -xvco buf d_digout cont dd ro_vco +xvco buf d_digout cont dd d_osc_vco +*xvco buf d_digout cont dd ro_vco * digital divider adiv1 d_digout d_divout divider @@ -48,17 +50,23 @@ adiv1 d_digout d_divout divider Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det * loop filter -.include loop-filter.cir -Xlf d_U d_D cont loopf +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe * d to a for plotting -abridge-w1 [d_divout d_ref d_U d_D] [s1 s2 u1 d1] dac1 +abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1 d1] dac1 ; change to d_u or d_Un .model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 1e-10 + t_fall = 1e-10) .control save cont s1 s2 u1 d1 +iplot cont * calculate breakpoint for switching frequency let t1_3 = simtime/3 set ti1_3 ="$&t1_3" @@ -82,7 +90,7 @@ alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw3 $&per3 ] resume rusage plot cont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u -plot cont +*plot cont .endc *model = bsim3v3 diff --git a/examples/xspice/pll/pll-xspice.cir b/examples/xspice/pll/pll-xspice.cir index 575e6af12..adff5c5d2 100644 --- a/examples/xspice/pll/pll-xspice.cir +++ b/examples/xspice/pll/pll-xspice.cir @@ -1,9 +1,11 @@ * pll circuit using xspice code models +* output frequency 400 MHz +* locked to a 1 or 10 MHz reference .param vcc=3.3 .param divisor=40 .param fref=10e6 -.csparam simtime=20u +.csparam simtime=25u .global d_d0 d_d1 @@ -11,7 +13,7 @@ vdd dd 0 dc 'vcc' *vco cont 0 dc 1.9 *PULSE(V1 V2 TD TR TF PW PER) -* 10 MHz reference frequency +* reference frequency selected by param fref * PULSE(V1 V2 TD TR TF PW PER) vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') abridgeref [ref] [d_ref] adc_vbuf @@ -27,11 +29,13 @@ ainv1 d_d0 d_d1 invd1 * vco .include vco_sub.cir +.include vco_sub_new.cir * buf: analog out * d_digout: digital out * cont: analog control voltage * dd: analog supply voltage -xvco buf d_digout cont dd ro_vco +xvco buf d_digout cont dd d_osc_vco +*xvco buf d_digout cont dd ro_vco * digital divider adiv1 d_digout d_divout divider @@ -43,22 +47,29 @@ adiv1 d_digout d_divout divider .include f-p-det-d-sub.cir Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det -* loop filter -.include loop-filter.cir -Xlf d_U d_D cont loopf +* loop filters +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe * d to a for plotting -abridge-w1 [d_divout d_ref d_U d_D] [s1 s2 u1 d1] dac1 +abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un .model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 1e-10 + t_fall = 1e-10) .control -save cont s1 s2 u1 d1 ; to save memory +save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory +iplot cont tran 0.1n $&simtime uic rusage -plot cont s1 s2+1.2 u1+2.4 d1+3.6 -plot cont +plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u +plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m +*plot cont .endc *model = bsim3v3 diff --git a/examples/xspice/pll/test-f-p-det.cir b/examples/xspice/pll/test-f-p-det.cir index fe3d41d25..19b9c867d 100644 --- a/examples/xspice/pll/test-f-p-det.cir +++ b/examples/xspice/pll/test-f-p-det.cir @@ -26,14 +26,19 @@ abridge-w1 [d_sig1 d_sig2 d_U d_D] [s1 s2 u1 d1] dac1 + input_load = 5.0e-12 t_rise = 1e-10 + t_fall = 1e-10) -* loop filter -.include loop-filter.cir -Xlf d_u d_D vco loopf +* loop filters +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe .control set xtrtol=2 tran 0.1n 1000n -plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 100n 200n +plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 140n 200n plot v(vco) .endc diff --git a/examples/xspice/pll/test_vco.cir b/examples/xspice/pll/test_vco.cir index 75b50ba03..414465d5c 100644 --- a/examples/xspice/pll/test_vco.cir +++ b/examples/xspice/pll/test_vco.cir @@ -1,16 +1,19 @@ -VCO: 7 stage Ring-Osc. made of gain cells BSIM3 +* Test of VCO: frequency versus control voltage +* 7 stage Ring-Osc. made of gain cells BSIM3 * P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 -* get frequency versus control voltage +* alternatively use d_osc code model * measure frequency of R.O. by fft .param vcc=3.3 .csparam simtime=500n .include vco_sub.cir +.include vco_sub_new.cir vdd dd 0 dc 'vcc' vco cont 0 dc 2.5 -xvco buf digout cont dd ro_vco +*xvco buf digout cont dd ro_vco ; ring oscillator vco +xvco buf digout cont dd d_osc_vco ; code model d_osc vco .option noacct @@ -75,6 +78,7 @@ setplot $freq_volt settype frequency foscvec settype voltage vcovec plot foscvec vs vcovec +print vcovec foscvec rusage .endc diff --git a/examples/xspice/pll/vco_sub.cir b/examples/xspice/pll/vco_sub.cir index 830a33065..77f873602 100644 --- a/examples/xspice/pll/vco_sub.cir +++ b/examples/xspice/pll/vco_sub.cir @@ -1,7 +1,7 @@ * VCO: 7 stage Ring-Osc. made of gain cells BSIM3 * P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 -* automatically tune Vdd to achive a desired frequency of oscillation -* measure frequency of R.O. either by delay measurement or by fft +* 150 MHz to 900 MHz with control voltage 2.5 to 0.5 V at 3.3 V supply +* BSIM 3 model data for transistors in main file pll-xspice.cir ***** ring oscillator as voltage controlled oscillator *************** * name: ro_vco @@ -64,3 +64,4 @@ abridge1 [aout] [dout] adc_buff .model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') .ends ro_vco ****************************************************************** + diff --git a/examples/xspice/pll/vco_sub_new.cir b/examples/xspice/pll/vco_sub_new.cir new file mode 100644 index 000000000..229ccf84a --- /dev/null +++ b/examples/xspice/pll/vco_sub_new.cir @@ -0,0 +1,30 @@ +***** XSPICE digital controlled oscillator d_osc as vco *************** +* 150 MHz to 900 MHz +* name: d_osc_vco +* aout analog out +* dout digital out +* cont control voltage +* dd supply voltage + +.subckt d_osc_vco aout dout cont dd +* curve fitting to ro_vco 'measured' data +Bfit fitted 0 v = (-58256685.71*v(cont)*v(cont) - 186386142.9*v(cont) + 988722980)/10. + +*a5 fitted dout var_clock +*.model var_clock d_osc(cntl_array = [1.0e7 5.0e7 9.0e7] +*+ freq_array = [1.0e8 5.0e8 9.0e8] + +* linear interpolation, input data from measured ro vco +a5 cont dout var_clock +.model var_clock d_osc(cntl_array = [0.5 1 1.5 2 2.5] ++ freq_array = [8.790820e+008 7.472197e+008 5.799500e+008 3.772727e+008 1.611650e+008] ++ duty_cycle = 0.5 init_phase = 180.0 ++ rise_delay = 1e-10 fall_delay=1e-10) + +*generate an analog output for plotting +abridge-fit [dout] [aout] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.ends d_osc_vco