From 95b7a297fa0d24929e74af27fd66cb900050949c Mon Sep 17 00:00:00 2001
From: h_vogt <h_vogt>
Date: Sun, 21 Nov 2010 00:32:54 +0000
Subject: [PATCH] PULSE: correct timing in case of phase != 0

---
 src/spicelib/devices/vsrc/vsrcacct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/spicelib/devices/vsrc/vsrcacct.c b/src/spicelib/devices/vsrc/vsrcacct.c
index 640b5051c..95034cb4c 100644
--- a/src/spicelib/devices/vsrc/vsrcacct.c
+++ b/src/spicelib/devices/vsrc/vsrcacct.c
@@ -74,7 +74,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
 #endif
                     /* offset time by delay  and limit to zero */
                     time = ckt->CKTtime - TD;
-
+                    tshift = TD;
 #ifdef XSPICE					
 		     /* normalize phase to 0 - 2PI */ 
                     phase = PHASE * M_PI / 180.0;