epilectrik
/
pyNgSpice
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

add examples for PSPICE -> ngspice transfer

pre-master-46
Holger Vogt 8 years ago
parent
09590047fe
commit
949299f2fc
14 changed files with 3006 additions and 0 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 93
      examples/p-to-n-examples/555-timer-2.cir
  2. 170
      examples/p-to-n-examples/MCP6041.txt
  3. 27
      examples/p-to-n-examples/MOS1_out.cir
  4. 376
      examples/p-to-n-examples/OPA171.txt
  5. 36
      examples/p-to-n-examples/OP_MCP6041.cir
  6. 1375
      examples/p-to-n-examples/OptiMOS5_30V_PSpice.lib
  7. 24
      examples/p-to-n-examples/Optimos_out.cir
  8. 438
      examples/p-to-n-examples/TLC555.LIB
  9. 181
      examples/p-to-n-examples/ad22057n.cir
  10. 40
      examples/p-to-n-examples/op-test-adi.cir
  11. 197
      examples/p-to-n-examples/op-test.cir
  12. 32
      examples/p-to-n-examples/relax_osc_st.cir
  13. 13
      examples/p-to-n-examples/remcirc-test.cir
  14. 4
      examples/p-to-n-examples/rtest.lib

93
examples/p-to-n-examples/555-timer-2.cir
View File

@ -0,0 +1,93 @@
TIMER 555
* https://www.electro-tech-online.com/threads/spice-and-555-timer.5806/
.SUBCKT UA555 32 30 19 23 33 1 21
* TR O R F TH D V
*
* Taken from the Fairchild data book (1982) page 9-3
*SYM=UA555
*DWG=C:\SPICE\555\UA555.DWG
Q4 25 2 3 QP
Q5 0 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 0 32 11 QP
Q15 14 18 13 QP
R5 14 0 100K
R6 22 0 100K
R7 17 0 10K
Q16 1 15 0 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 0 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 0 QN
Q21 25 22 0 QN
Q22 27 24 0 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 0 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 0 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
.MODEL QP PNP (BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2)
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
.MODEL QN NPN (IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2
+ BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS
**********
* Sample Test Circuit for the LM555 Timer: Astable Mode
* The LM555 timer model is designed for low frequency
* applications, up to 100Hz.
.INCLUDE TLC555.LIB
.TRAN 10u 100MS
.OPTIONS RELTOL=.0001
.SAVE v(16) v(13) v(17)
.SAVE v(1) v(4) v(3)
V2 2 0 5
VReset res 0 DC 0 PULSE(0 5 1u 1u 1u 30m 50m)
R3 2 3 1k
R4 3 4 5k
C3 4 0 0.5u $ 0.15u
X2 4 1 res 6 4 3 2 ua555
* TR O R F TH D V
RA 2 17 1k $ 5k
RB 17 16 5k $ 3k
C 16 0 0.5u $ 0.15u
RL 2 13 1k
X1 16 15 16 res 13 17 2 0 TLC555
* THRES CONT TRIG RESET OUT DISC VCC GND
.control
if $?batchmode
else
run
plot v(16) v(13) v(17) v(1)+6 v(4)+6 v(3)+6
end
.endc
.END

170
examples/p-to-n-examples/MCP6041.txt
View File

@ -0,0 +1,170 @@
.SUBCKT MCP6041 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
*
********************************************************************************
* Software License Agreement *
* *
* The software supplied herewith by Microchip Technology Incorporated (the *
* 'Company') is intended and supplied to you, the Company's customer, for use *
* soley and exclusively on Microchip products. *
* *
* The software is owned by the Company and/or its supplier, and is protected *
* under applicable copyright laws. All rights are reserved. Any use in *
* violation of the foregoing restrictions may subject the user to criminal *
* sanctions under applicable laws, as well as to civil liability for the *
* breach of the terms and conditions of this license. *
* *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
********************************************************************************
*
* The following op-amps are covered by this model:
* MCP6041,MCP6042,MCP6043,MCP6044
*
* Revision History:
* REV A: 07-Sep-01, Created model
* REV B: 27-Aug-06, Added over temperature, improved output stage,
* fixed overdrive recovery time
* REV C: 09-Apr-07, Adjusted quiescent current to match spec
* REV D: 27-Jul-07, Modified output impedance at expense of comparator operation
* to correct transient response with capacitive load
*
* Recommendations:
* Use PSPICE (other simulators may require translation)
* For a quick, effective design, use a combination of: data sheet
* specs, bench testing, and simulations with this macromodel
* For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
* Typical performance for temperature range (-40 to 125) degrees Celsius
* DC, AC, Transient, and Noise analyses.
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
* open loop gain, voltage ranges, supply current, ... , etc.
* Temperature effects for Ibias, Iquiescent, Iout short circuit
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
* Chip select (MCP6043)
* Some Variation in specs vs. Power Supply Voltage
* Monte Carlo (Vos, Ib), Process variation
* Distortion (detailed non-linear behavior)
* Behavior outside normal operating region
*
* Input Stage
V10 3 10 -500M
R10 10 11 69k
R11 10 12 69k
C12 1 0 6P
C11 11 12 95P
E12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0 2.00M 10 10 29 29 1 1
G12 1 0 62 0 1m
M12 11 14 15 15 NMI
G13 1 2 62 0 20u
M14 12 2 15 15 NMI
G14 2 0 62 0 1m
C14 2 0 6P
I15 15 4 4U
V16 16 4 -300M
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1u)(2m,1m))
V13 3 13 -300M
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1u)(2m,1m))
R71 1 0 20.0E12
R72 2 0 20.0E12
R73 1 2 20.0E12
I80 1 2 500E-15
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20 0 DN1
D21 0 21 DN1
I22 22 23 1N
R22 22 0 1k
R23 0 23 1k
G26 0 26 POLY(2) 3 0 4 0 0.00 -79.4U -39.8U
R26 26 0 1
G27 0 27 POLY(2) 1 0 2 0 0 26u 26u
R27 27 0 1
*
* Open Loop Gain, Slew Rate
G30 0 30 12 11 3.2
R30 30 0 1.00K
I31 0 31 DC 338
R31 31 0 1 TC=2.25M,-15U
GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2))
I32 32 0 DC 535
R32 32 0 1 TC=2.02M,-11U
GD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n))
G33 0 33 30 0 1m
R33 33 0 3K
G34 0 34 33 0 1
R34 34 0 1K
C34 34 0 100M
G37 0 341 34 0 1m
R341 341 0 1k
C341 341 0 1.3N
G371 0 37 341 0 1m
R37 37 0 1K
C37 37 0 3N
G38 0 38 37 0 1m
R38 39 0 1K
L38 38 39 13M
E38 35 0 38 0 1
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(3.4k,1n))(3.5k,1))
G36 33 0 TABLE {V(35,4)} ((-3.5k,-1)((-3.4k,-1n)(0,0)(1,1n))
*
* Output Stage
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57 96 0.50
R57 57 0 101k
C58 5 0 2.00P
G57 0 57 POLY(3) 3 0 4 0 35 0 0 10U 1.49U 9.1U
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
E55 55 0 POLY(2) 3 0 51 0 -0.7M 1 -40M
E56 56 0 POLY(2) 4 0 52 0 0.6M 1 -55M
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G53 3 0 POLY(1) 51 0 -4U 1M
G54 0 4 POLY(1) 52 0 -4U -1M
*
* Current Limit
G99 96 5 99 0 1
R98 0 98 1 TC=-6.9M
G97 0 98 TABLE { V(96,5) } ((-11.0,-3.9M)(-1.00M,-3.87M)(0,0)(1.00M,3.23M)(11.0,3.26M))
E97 99 0 VALUE { V(98)*((V(3)-V(4))*1.39 + -1.5)}
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
R61 0 61 1 TC=2.52M,-4.31U
G61 3 4 61 0 1
G60 0 61 TABLE {V(3, 4)}
+ ((0,0)(700M,5.3N)(770M,10.0N)(1.00,480N)
+ (1.5,500N)(3.5,530N)(7.00,580N))
*
* Temperature Sensistive offset voltage
I73 0 70 DC 1uA
R74 0 70 1 TC=1.5
E75 1 71 70 0 1
*
* Temp Sensistive IBias
I62 0 62 DC 1uA
R62 0 62 REXP 210U
*
* Models
.MODEL NMI NMOS(L=2.00U W=42.0U KP=20.0U LEVEL=1 )
.MODEL DESD D N=1 IS=1.00E-15
.MODEL DN1 D IS=1P KF=0.2F AF=1
.MODEL REXP RES TCE= 9
.ENDS MCP6041

27
examples/p-to-n-examples/MOS1_out.cir
View File

@ -0,0 +1,27 @@
Test MOS1
vb Nvf 0 0
vd Nvd 0 0
vg Nvg 0 0
vs1 Nvs1 0 0
vs2 Nvs2 0 0
vs3 Nvs3 0 0
* W/L = 3
M1 Nvd Nvg Nvs1 Nvf NMOS
* W/L = 2
M2 Nvd Nvg Nvs2 Nvf NMOS W=10u L=5u
* W/L = 1
M3 Nvd Nvg Nvs3 Nvf NMOS3
.MODEL NMOS NMOS (LEVEL = 1 L = 3u W = 9u)
.MODEL NMOS3 NMOS (LEVEL = 1)
.control
dc vd 0 5 0.1 vg 0 5 1
plot vs1#branch vs2#branch vs3#branch
.endc
.end

376
examples/p-to-n-examples/OPA171.txt
View File

@ -0,0 +1,376 @@
* OPA171 - Rev. B
* Created by Ian Williams; January 17, 2017
* Created with Green-Williams-Lis Op Amp Macro-model Architecture
* Copyright 2017 by Texas Instruments Corporation
******************************************************
* MACRO-MODEL SIMULATED PARAMETERS:
******************************************************
* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)
* UNITY GAIN BANDWIDTH (GBW)
* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
* DIFFERENTIAL INPUT IMPEDANCE (Zid)
* COMMON-MODE INPUT IMPEDANCE (Zic)
* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
* QUIESCENT CURRENT (Iq)
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
* SLEW RATE (SR)
* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
* LARGE SIGNAL RESPONSE
* OVERLOAD RECOVERY TIME (tor)
* INPUT BIAS CURRENT (Ib)
* INPUT OFFSET CURRENT (Ios)
* INPUT OFFSET VOLTAGE (Vos)
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
******************************************************
.subckt OPA171 IN+ IN- VCC VEE OUT
******************************************************
* MODEL DEFINITIONS:
.model BB_SW VSWITCH(Ron=50 Roff=1e9 Von=700e-3 Voff=0)
.model ESD_SW VSWITCH(Ron=50 Roff=1e9 Von=500e-3 Voff=100e-3)
.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)
.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
.model R_NOISELESS RES(T_ABS=-273.15)
******************************************************
V_OS N041 en_n 214.023e-6
R1 N043 N042 R_NOISELESS 1e-3
R2 N049 ESDn R_NOISELESS 1e-3
R3 N063 0 R_NOISELESS 1e12
C1 N063 0 1
R4 VCC_B N062 R_NOISELESS 1e-3
C2 N062 0 1e-15
C3 N064 0 1e-15
R5 N064 VEE_B R_NOISELESS 1e-3
G_PSR N043 N044 N005 N014 1e-3
R6 MID N047 R_NOISELESS 1e9
VCM_MIN N048 VEE_B -0.1
R7 N048 MID R_NOISELESS 1e9
VCM_MAX N047 VCC_B -2
XVCM_CLAMP N044 MID N045 MID N047 N048 VCCS_EXT_LIM
R8 N045 MID R_NOISELESS 1
C4 VCM_CLAMP MID 1e-15
R9 N045 VCM_CLAMP R_NOISELESS 1e-3
V4 N061 OUT 0
R10 MID N051 R_NOISELESS 1e9
R11 MID N052 R_NOISELESS 1e9
XIQp VIMON MID VCC MID VCCS_LIM_IQ
XIQn MID VIMON VEE MID VCCS_LIM_IQ
R12 VCC_B N016 R_NOISELESS 1e3
R13 N029 VEE_B R_NOISELESS 1e3
XCLAWp VIMON MID N016 VCC_B VCCS_LIM_CLAWp
XCLAWn MID VIMON VEE_B N029 VCCS_LIM_CLAWn
R14 VEE_CLP MID R_NOISELESS 1e3
R15 MID VCC_CLP R_NOISELESS 1e3
R16 N017 N016 R_NOISELESS 1e-3
R17 N030 N029 R_NOISELESS 1e-3
C5 MID N017 1e-15
C6 N030 MID 1e-15
R18 VOUT_S N052 R_NOISELESS 100
C7 VOUT_S MID 1e-9
G2 MID VCC_CLP N017 MID 1e-3
G3 MID VEE_CLP N030 MID 1e-3
XCL_AMP N013 N039 VIMON MID N020 N027 CLAMP_AMP_LO
V_ISCp N013 MID 25
V_ISCn N039 MID -35
XOL_SENSE MID N068 OLN OLP OL_SENSE
R19 N039 MID R_NOISELESS 1e9
R20 N027 MID R_NOISELESS 1
C8 N028 MID 1e-15
R21 MID N020 R_NOISELESS 1
R22 MID N013 R_NOISELESS 1e9
C9 MID N021 1e-15
XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N018 N025 CLAMP_AMP_LO
R23 VEE_CLP MID R_NOISELESS 1e9
R24 N025 MID R_NOISELESS 1
C10 N026 MID 1e-15
R25 MID N018 R_NOISELESS 1
R26 MID VCC_CLP R_NOISELESS 1e9
C11 MID N019 1e-15
XCL_SRC N021 N028 CL_CLAMP MID VCCS_LIM_4
XCLAW_SRC N019 N026 CLAW_CLAMP MID VCCS_LIM_3
R27 N018 N019 R_NOISELESS 1e-3
R28 N026 N025 R_NOISELESS 1e-3
R29 N020 N021 R_NOISELESS 1e-3
R30 N028 N027 R_NOISELESS 1e-3
R31 N068 MID R_NOISELESS 1
R32 N068 SW_OL R_NOISELESS 100
C12 SW_OL MID 10e-12
R33 VIMON N051 R_NOISELESS 100
C13 VIMON MID 1e-9
C_DIFF en_p ESDn 3e-12
C_CMn ESDn MID 3e-12
C_CMp MID en_p 3e-12
I_Q VCC VEE 475e-6
I_B N044 MID 8e-12
I_OS N049 MID 4e-12
R36 N037 MID R_NOISELESS 1
R37 N040 MID R_NOISELESS 1e9
R38 MID N023 R_NOISELESS 1
R39 MID N015 R_NOISELESS 1e9
XGR_AMP N015 N040 N022 MID N023 N037 CLAMP_AMP_HI
XGR_SRC N024 N038 CLAMP MID VCCS_LIM_GR
C17 MID N024 1e-15
C18 N038 MID 1e-15
V_GRn N040 MID -50
V_GRp N015 MID 50
R40 N023 N024 R_NOISELESS 1e-3
R41 N038 N037 R_NOISELESS 1e-3
R42 VSENSE N022 R_NOISELESS 1e-3
C19 MID N022 1e-15
R43 MID VSENSE R_NOISELESS 1e3
G_CMR N041 N042 N012 MID 1e-3
G8 MID CLAW_CLAMP N050 MID 1e-3
R45 MID CLAW_CLAMP R_NOISELESS 1e3
G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3
R46 MID CL_CLAMP R_NOISELESS 1e3
R47 N059 VCLP R_NOISELESS 100
C24 MID VCLP 100e-12
E4 N059 MID CL_CLAMP MID 1
E5 N052 MID OUT MID 1
H1 N051 MID V4 1e3
S1 N054 N053 SW_OL MID OL_SW
R52 MID en_p R_NOISELESS 1e9
R53 ESDn MID R_NOISELESS 1e9
R_CMR N042 N041 R_NOISELESS 1e3
R59 N062 N063 R_NOISELESS 1e6
R60 N063 N064 R_NOISELESS 1e6
R_PSR N044 N043 R_NOISELESS 1e3
G15 MID VSENSE CLAMP MID 1e-3
V_ORp N036 VCLP 3
V_ORn N031 VCLP -3
V11 N033 N032 0
V12 N034 N035 0
H2 OLN MID V11 -1
H3 OLP MID V12 1
S2 VCC ESDn ESDn VCC ESD_SW
S3 VCC en_p en_p VCC ESD_SW
S4 ESDn VEE VEE ESDn ESD_SW
S5 en_p VEE VEE en_p ESD_SW
S6 VCC OUT OUT VCC ESD_SW
S7 OUT VEE VEE OUT ESD_SW
E1 MID 0 N063 0 1
G16 0 VCC_B VCC 0 1
G17 0 VEE_B VEE 0 1
R88 VCC_B 0 R_NOISELESS 1
R89 VEE_B 0 R_NOISELESS 1
S8 N034 CLAMP CLAMP N034 OR_SW
S9 CLAMP N033 N033 CLAMP OR_SW
Xi_np en_n MID FEMT
Xi_nn ESDn MID FEMT
XVCCS_LIM_1 VCM_CLAMP N049 MID N046 VCCS_LIM_1
XVCCS_LIM_2 N046 MID MID CLAMP VCCS_LIM_2
R44 N046 MID R_NOISELESS 1e6
R58 CLAMP MID R_NOISELESS 1e6
C20 CLAMP MID 1.484e-7
S10 en_p ESDn ESDn en_p BB_SW
S11 ESDn en_p en_p ESDn BB_SW
R34 en_p IN+ R_NOISELESS 10e-3
R35 ESDn IN- R_NOISELESS 10e-3
R48 MID N050 R_NOISELESS 1e6
G1 MID N050 VSENSE MID 1e-6
C14 N050 MID 7.4e-15
Rx N061 N060 R_NOISELESS 1.65e4
Rdummy N061 MID R_NOISELESS 1.65e3
G_Zo MID N053 CL_CLAMP N061 172
Rdc1 N053 MID R_NOISELESS 1
R49 N053 N054 R_NOISELESS 1e5
R50 N054 MID R_NOISELESS 1.266e3
G4 MID N057 N054 MID 80
C15 N054 N053 1.592e-6
R51 N057 MID R_NOISELESS 1
C16 N067 MID 1.929e-10
R54 N067 N058 R_NOISELESS 10e3
R55 N058 N057 R_NOISELESS 1.547e6
C23 N007 N006 1.516e-12
G_adjust1 MID N006 en_p MID 4.75e-4
Rsrc1 N006 MID R_NOISELESS 1
R56 N007 MID R_NOISELESS 2.104e5
R57 N007 N006 R_NOISELESS 1e8
G5 MID N008 N007 MID 1
Rsrc2 N008 MID R_NOISELESS 1
R61 N009 N008 R_NOISELESS 1e4
C25 N009 N008 1.516e-8
R62 N009 MID R_NOISELESS 2.104e1
G6 MID N012 N009 MID 4.762e2
Rsrc3 N012 MID R_NOISELESS 1
C26 N011 N010 3.745e-10
G_adjust2 MID N010 VEE_B MID 1.588e-1
Rsrc4 N010 MID R_NOISELESS 1
R63 N011 MID R_NOISELESS 6.296e2
R64 N011 N010 R_NOISELESS 1e8
G7 MID N014 N011 MID 1
Rsrc5 N014 MID R_NOISELESS 1
C27 N003 N004 2.792e-12
G_adjust3 MID N004 VCC_B MID 3.772e-4
Rsrc6 N004 MID R_NOISELESS 1
R65 N003 MID R_NOISELESS 2.658e5
R66 N003 N004 R_NOISELESS 1e8
G10 MID N002 N003 MID 1
Rsrc7 N002 MID R_NOISELESS 1
R67 N001 N002 R_NOISELESS 1e4
C28 N001 N002 2.792e-8
R68 N001 MID R_NOISELESS 2.658e1
G11 MID N005 N001 MID 3.772e2
Rsrc8 N005 MID R_NOISELESS 1
Xe_n N065 MID VNSE
G12 MID N066 N065 N069 1
R69 N066 N069 R_NOISELESS 1e6
R70 N066 N069 R_NOISELESS 11.786e3
C29 N066 N069 6.75e-12
R71 N069 N070 R_NOISELESS 15e3
C30 N070 MID 106e-12
Rpd N070 MID R_NOISELESS 1e9
E2 en_p en_n N066 MID 1
G13 MID N055 N058 MID 1
R72 N055 MID R_NOISELESS 1
R73 N056 N055 R_NOISELESS 1e4
R74 MID N056 R_NOISELESS 5
C21 N056 N055 3.183e-13
XVCCS_LIM_ZO N056 MID MID N060 VCCS_LIM_ZO
R76 MID N060 R_NOISELESS 1
G14 MID N032 N031 MID 1
G18 MID N035 N036 MID 1
R77 MID N032 R_NOISELESS 1
R78 MID N035 R_NOISELESS 1
.ends OPA171
*
.subckt CLAMP_AMP_HI VC+ VC- VIN COM VO+ VO-
.param G=10
GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ends CLAMP_AMP_HI
*
.subckt OL_SENSE 1 2 3 4
GSW+ 1 2 Value = {IF((V(3,1)>10e-3 | V(4,1)>10e-3),1,0)}
.ends OL_SENSE
*
.subckt FEMT 1 2
.param FLWF=1e-3
.param NLFF=1
.param NVRF=1
.param GLFF={PWR(FLWF,0.25)*NLFF/1164}
.param RNVF={1.184*PWR(NVRF,2)}
.model DVNF D KF={PWR(FLWF,0.5)/1e11} IS=1.0e-16
I1 0 7 10e-3
I2 0 8 10e-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1e9
R2 3 0 1e9
R3 3 6 1e9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1e9
R7 4 0 1e9
G1 1 2 3 4 1e-6
.ends FEMT
*
.subckt VCCS_EXT_LIM VIN+ VIN- IOUT- IOUT+ VP+ VP-
.param Gain = 1
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ends VCCS_EXT_LIM
*
.subckt VCCS_LIM_1 VC+ VC- IOUT+ IOUT-
.param Gain = 1e-4
.param Ipos = .5
.param Ineg = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_1
*
.subckt VCCS_LIM_2 VC+ VC- IOUT+ IOUT-
.param Gain = 3.40e-2
.param Ipos = 0.224
.param Ineg = -0.224
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_2
*
.subckt VCCS_LIM_3 VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 100e-3
.param Ineg = -100e-3
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_3
*
.subckt VCCS_LIM_4 VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 200e-3
.param Ineg = -200e-3
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_4
*
.subckt VCCS_LIM_CLAWn VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} =
+(0, 1e-5)
+(3.38, 3.1e-5)
+(3.66, 3.2e-5)
+(3.87, 7.8e-5)
+(6.67, 5.64e-4)
+(8, 8.48e-4)
+(15, 2.23e-3)
+(35, 6.3e-3)
.ends VCCS_LIM_CLAWn
*
.subckt VCCS_LIM_IQ VC+ VC- IOUT+ IOUT-
.param Gain = 1e-3
G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )}
.ends VCCS_LIM_IQ
*
.subckt VNSE 1 2
.param FLW=20
.param NLF=45
.param NVR=14
.param GLF={PWR(FLW,0.25)*NLF/1164}
.param RNV={1.184*PWR(NVR,2)}
.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ends VNSE
*
.subckt CLAMP_AMP_LO VC+ VC- VIN COM VO+ VO-
.param G=1
GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ends CLAMP_AMP_LO
*
.subckt VCCS_LIM_GR VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 0.5
.param Ineg = -0.5
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_GR
*
.subckt VCCS_LIM_CLAWp VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} =
+(0, 1e-5)
+(7.1, 6.8e-4)
+(14.64, 1.54e-3)
+(25, 2.7e-3)
.ends VCCS_LIM_CLAWp
*
.subckt VCCS_LIM_ZO VC+ VC- IOUT+ IOUT-
.param Gain = 2e3
.param Ipos = 1e3
.param Ineg = -1.5e3
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
.ends VCCS_LIM_ZO
*

36
examples/p-to-n-examples/OP_MCP6041.cir
View File

@ -0,0 +1,36 @@
Test OpAmp
*.OPTIONS RELTOL=.0001
*.include MCP6041ng.lib
.include MCP6041.txt
V1 vdd 0 2.2
V2 vss 0 -2.2
Vin in 0 dc 0 sin(0 100m 500)
Rin in opin 1000k
Rfb opout opin 10000k
*Eop opout 0 opin 0 -10000
Xop 0 opin vdd vss opout MCP6041
* MCP6041 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
*.dc Vin -2.2 2.2 0.1
*.tran 0.1m 10m
.control
dc Vin -0.2 0.2 0.01
plot v(opout) v(opin)
tran 0.1m 10m
plot v(in) v(opin) v(opout)
.endc
.end

1375
examples/p-to-n-examples/OptiMOS5_30V_PSpice.lib
File diff suppressed because it is too large
View File

24
examples/p-to-n-examples/Optimos_out.cir
View File

@ -0,0 +1,24 @@
Test Optimos PSPICE models
*Xopt Nvd Nvg Nvs Tj Tcase SPD50N03S2-07 dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0
*Xopt Nvd Nvg Nvs Tj Tcase SPD30N03S2L-10 dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0
Xopt Nvd Nvg Nvs Tj Tcase BSC0500NSI dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=0.3n Ld=1n Lg=3n
vd 1 0 0
rd 1 Nvd 6m
vg Nvg 0 0
vs Nvs 0 0
vtc tcase 0 25
vjt tj 0 25
.include D:\Spice_general\tests\pspice-to-ngspice\OptiMOS5_30V_PSpice.lib $ OptiMOS_30V.lib
.control
dc vd 0 3 0.1 vg 2.8 3.2 0.2
dc vd 0 3 0.1 vg 3.5 5 0.5
* plot similar to output characteristics in data sheet
plot vs#branch vs v(Nvd) dc1.vs#branch vs dc1.v(Nvd) noretraceplot
.endc
.end

438
examples/p-to-n-examples/TLC555.LIB
View File

@ -0,0 +1,438 @@
* TLC555
*****************************************************************************
* (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Analog eLab Design Center, Texas Instruments Inc.
* Part: TLC555
* Date: 13JUN2011
* Model Type: ALL IN ONE
* Simulator: PSPICE
* Simulator Version: 16.0.0.p001
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SLFS043F - SEPTEMBER 1983 - REVISED FEBRUARY 2005
*
* Model Version: 1.0
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 :
* Release to Web
*
*****************************************************************************
*
* THIS MODEL IS APPLICABLE FOR TLC555 & TLC556
*
*****************************************************************************
.SUBCKT TLC555 THRES CONT TRIG RESET OUT DISC VCC GND
XD8 GND RESI D_Z18V
XD7 GND RESET D_Z18V
XR2 RESET RESI TLC55X_RWELL
+ PARAMS: W=50u L=20u
XD2 GND TRGI D_Z18V
XD1 GND TRIG D_Z18V
XR3 TRIG TRGI TLC55X_RWELL
+ PARAMS: W=50u L=20u
XD4 GND THRI D_Z18V
XD3 GND THRES D_Z18V
XR2_2 THRES THRI TLC55X_RWELL
+ PARAMS: W=50u L=20u
XD6 GND CONTI D_Z18V
XD5 GND CONT D_Z18V
XR2_3 CONT CONTI TLC55X_RWELL
+ PARAMS: W=50u L=20u
XMN15 GOUT GND QFF GND MDSWN
+ PARAMS: W=100U L=10U M=7
XMP15 GOUT VCC QFF GND MDSWP
+ PARAMS: W=195U L=10U M=9
XMN3 GND TRGO 23 IIMIRRN
+ PARAMS: W1=170U L1=18U M1=1 W2=170U L2=18U M2=1 IDIN=1U
XMN5 GND THRS 25 IIMIRRN
+ PARAMS: W1=13U L1=26U M1=1 W2=52U L2=13U M2=2 IDIN=50N
XMp9 VCC RESO 15 GND IMIRRP
+ PARAMS: W=112U L=15U M=2 IO=2U
XMp6 VCC 25 15 GND IMIRRP
+ PARAMS: W=18U L=26U M=1 IO=100n
XMp5 VCC TRGS 15 GND IMIRRP
+ PARAMS: W=112U L=15U M=2 IO=2U
XMp1 VCC THRO 29 IIMIRRP
+ PARAMS: W1=172U L1=15U M1=1 W2=172U L2=15U M2=1 IDIN=1U
XIB VCC GND 15 IBIAS
XRSFF TRGO THRO RESO QFF 30 VCC GND RR1SFF
+ PARAMS: VOUTH=1 VOUTL=0 RIN=1E12 DELAY=30N ROUT=10
XMN9 TRGO RESO GND MSWN
+ PARAMS: W=100U L=10U M=1
XMN17 DISC GOUT GND GND TLC55X_NMOS_HV
+ PARAMS: W=350U L=10U M=20
XMN16 OUT GOUT GND GND TLC55X_NMOS_HV
+ PARAMS: W=175U L=10U M=20
XMP16 OUT GOUT VCC VCC TLC55X_PMOS_HV
+ PARAMS: W=270u L=10u M=7
XMN10 RESO RESI GND GND TLC55X_NMOS_HV_L1
+ PARAMS: W=100u L=10u M=1
XMN2 THRO THRI THRS GND TLC55X_NMOS_MV
+ PARAMS: W=170u L=18u M=2
XMP4 TRGO TRGI TRGS VCC TLC55X_PMOS_MV
+ PARAMS: W=172u L=15u M=2
XMP3 23 TRGC TRGS VCC TLC55X_PMOS_MV
+ PARAMS: W=172u L=15u M=2
XMPR1F GND GND 32 TRGC TLC55X_PMOS_LV
+ PARAMS: W=20U L=15U M=1
XMPR1E 32 32 TRGC TRGC TLC55X_PMOS_LV
+ PARAMS: W=20U L=15U M=1
XMPR1D TRGC TRGC 33 CONTI TLC55X_PMOS_LV
+ PARAMS: W=20U L=15U M=1
XMPR1C 33 33 CONTI CONTI TLC55X_PMOS_LV
+ PARAMS: W=20U L=15U M=1
XMPR1B CONTI CONTI 34 VCC TLC55X_PMOS_LV
+ PARAMS: W=20u L=15u M=1
XMPR1A 34 34 VCC VCC TLC55X_PMOS_LV
+ PARAMS: W=20u L=15u M=1
XMN1 29 CONTI THRS GND TLC55X_NMOS_MV
+ PARAMS: W=170u L=18u M=2
.ENDS TLC555
.SUBCKT TLC55X_NMOS_HV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_NMOSD_HV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.SUBCKT TLC55X_NMOS_HV_L1 D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_NMOSD_HV_L1 W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.SUBCKT TLC55X_NMOS_MV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_NMOSD_MV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.SUBCKT TLC55X_NMOS_LV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_NMOSD_LV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.MODEL TLC55X_NMOSD_HV NMOS LEVEL=3 L=10U W=100U KP={KPN} VTO={VTOHN} LAMBDA=2E-3 THETA=1.8E-01
+ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} RSH= 10 PB=0.65 LD= 70N TOX={TOX}
*$
.MODEL TLC55X_NMOSD_HV_L1 NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTOHN} LAMBDA=2E-3
+ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} RSH= 10 PB=0.65 LD= 70N TOX={TOX}
*$
.MODEL TLC55X_NMOSD_MV NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTOMN} LAMBDA=2E-3
+ CJ={CJNCG} CJSW={CJSWNCG} CGSO={CGSONCG} CGDO={CGDONCG} PB=0.65 LD= 70N TOX={TOXCG}
*+ RSH= 10
*$
.MODEL TLC55X_NMOSD_LV NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTON} LAMBDA=2E-3
+ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} PB=0.65 LD= 300N TOX={TOX}
*+ RSH= 10
*$
.SUBCKT TLC55X_PMOS_HV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_PMOSD_HV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.SUBCKT TLC55X_PMOS_MV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_PMOSD_MV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.SUBCKT TLC55X_PMOS_LV D G S B PARAMS: W = 100U L = 10U M = 1
M1 D G S B TLC55X_PMOSD_LV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS}
+ NRD={LS/W} NRS={LS/W}
.ENDS
*$
.MODEL TLC55X_PMOSD_HV PMOS LEVEL=3 L=10U W=100U KP={KPP} VTO={-VTOHP} LAMBDA=2E-3 THETA=2.2E-01
+ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP} RSH=10 PB=0.65 LD=70N TOX={TOX}
*$
.MODEL TLC55X_PMOSD_MV PMOS LEVEL=1 L=10U W=100U KP={KPP} VTO={-VTOMP} LAMBDA=2E-3
*+ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP} PB=0.65 LD=70N TOX={TOX}
+ CJ={CJNCG} CJSW={CJSWNCG} CGSO={CGSONCG} CGDO={CGDONCG} PB=0.65 LD= 70N TOX={TOXCG}
*+ RSH= 10
*$
.MODEL TLC55X_PMOSD_LV PMOS LEVEL=1 L=10U W=100U KP={KPP} VTO={-VTOP} LAMBDA=2E-3
+ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP} PB=0.65 LD=300N TOX={TOX}
*+ RSH= 10
*$
.SUBCKT TLC55X_RWELL 1 2 PARAMS: W = 10U L = 100U
XR1 1 2 TLC55X_RWELLD PARAMS: W = {W} L = {L}
.ENDS
*$
.SUBCKT TLC55X_RWELLD 1 2 PARAMS: W = 10U L = 100U
R1 1 2 {RSW*L/W}
.ENDS
*$
.SUBCKT TLC55X_RNSD 1 2 PARAMS: W = 10U L = 100U
XR1 1 2 TLC55X_RNSD_D PARAMS: W = {W} L = {L}
.ENDS
*$
.SUBCKT TLC55X_RNSD_D 1 2 PARAMS: W = 10U L = 100U
R1 1 2 {RSN*L/W}
.ENDS
*$
.SUBCKT TLC55X_RC 1 2 PARAMS: WW = 10U LW = 100U WNSD = 10U LNSD = 100U
XR1 1 2 TLC55X_RC_D PARAMS: WW = {WW} LW = {LW} WNSD = {WNSD} LNSD = {LNSD}
.ENDS
*$
.SUBCKT TLC55X_RC_D 1 2 PARAMS: WW = 10U LW = 100U WNSD = 10U LNSD = 100U
R1 1 2 {RSW*LW/WW + RSN*LNSD/WNSD}
.ENDS
*
.SUBCKT IBIAS VCC GND VIB
*
.PARAM M1 = 8
.PARAM M2 = 5
.PARAM MP = 1
.PARAM WP = 13U
.PARAM WN = 130U
.PARAM LPE = {36U - LDP}
.PARAM LNE = {13U - LDN}
.PARAM BP = {MP*(WP/LPE)*(KPP/2)}
.PARAM WW = 13U
.PARAM LW = 213U
.PARAM WNN = 25U
.PARAM LNN = 87U
.PARAM R1 = {(RSW*LW/WW + RSN*LNN/WNN)}
.PARAM K2 = {M2*(WN/LNE)*(KPN/2)}
.PARAM MR = {M2/M1}
*
R1 VIB GND {VBMUL}
GB VCC VIB VALUE = {LIMIT( IF ( V(VCC,GND) > VTOHP, BP*PWR(V(VCC,GND)-VTOHP, 2), 0),
+ (1 + 1*LAMBDA*(V(VCC,GND) - VTOHN))*PWR(( 1 - SQRT(MR/(1+2*LAMBDA*(V(VCC,GND) - VTOHP))) )/R1, 2)/K2, 0)}
R2 VIB VCC {RPAR}
.ENDS
.SUBCKT IMIRRP VCC IO VIB GND PARAMS: W = 100U L = 10U M = 1 IO = 1U
*
.PARAM MP = 1
.PARAM WP = 13U
.PARAM LPE = {36U - LDP}
.PARAM LE = {L - LDP}
.PARAM MR = { M*W/LE/(MP*WP/LPE)/VBMUL }
.PARAM B1 = { (KPP/2*MP*WP/LPE)*VBMUL }
.PARAM IS = 1E-12
.PARAM N = {VTOHP/(VT*Log(1 + IO/IS))}
*
GB VCC IO VIB GND {MR}
R1 VCC IO {RPAR}
C1 VCC IO {M*(CBDJ*CJP*LS*W + CBDS*CJSWP*(2*LS + W))}
V1 VCC 10 {VTOHP}
D1 IO 10 DMOD1
.MODEL DMOD1 D (IS={IS} N={N} )
.ENDS
.SUBCKT IIMIRRP VCC IO II PARAMS: W1 = 100U L1 = 10U M1 = 1 W2 = 100U L2= 10U M2 = 2 IDIN = 1U
*
.PARAM L1E = {L1 - LDP}
.PARAM L2E = {L2 - LDP}
.PARAM B1 = {M1*(W1/L1)*(KPP/2)}
.PARAM MR = {M2*W2/L2E/(M1*W1/L1E)}
.PARAM RDS = {1/(2*SQRT(M2*(W2/L2E)*(KPP/2)*IDIN))}
.PARAM IS = 1E-12
.PARAM NP = {VTOP/(VT*Log(1 + IDIN/IS))}
*
FB VCC IO V1 {MR}
R1 VCC IO {RPAR}
C1 VCC IO {M2*(CBDJ*CJP*LS*W2 + CBDS*CJSWP*(2*LS + W2))}
D1 IO 10 DMODP
V1 VCC 10 {VTOP}
R2 II 10 {RDS}
C2 VCC II {M1*(CBDJ*CJP*LS*W1 + CBDS*CJSWP*(2*LS + W1)) + 2/3*COX*(M1*W1*L1E + M2*W2*L2E) + M1*CGSOP*W1}
C3 II IO {CGDOP*W2}
.MODEL DMODP D (IS={IS} N={NP} )
.ENDS
.SUBCKT IIMIRRN GND IO II PARAMS: W1 = 100U L1 = 10U M1 = 1 W2 = 100U L2= 10U M2 = 2 IDIN = 1U
*
.PARAM L1E = {L1 - LDN}
.PARAM L2E = {L2 - LDN}
.PARAM B1 = {M1*(W1/L1)*(KPN/2)}
.PARAM MR = { M2*W2/L2E/(M1*W1/L1E) }
.PARAM RDS = {1/(2*SQRT(M2*(W2/L2E)*(KPN/2)*IDIN))}
.PARAM IS = 1E-12
.PARAM NN = {VTON/(VT*Log(1 + IDIN/IS))}
*
FB IO GND V1 {MR}
R1 IO GND {RPAR}
C1 IO GND {M2*(CBDJ*CJN*LS*W2 + CBDS*CJSWN*(2*LS + W2))}
D1 10 IO DMODN
V1 10 GND {VTON}
R2 II 10 {RDS}
C2 II GND {M1*(CBDJ*CJN*LS*W1 + CBDS*CJSWN*(2*LS + W1)) + 2/3*COX*(M1*W1*L1E + M2*W2*L2E) + M1*CGSON*W1}
C3 II IO {M2*CGDON*W2}
.MODEL DMODN D (IS={IS} N={NN} )
.ENDS
.SUBCKT MDSWP D S DG GND PARAMS: W = 100U L = 10U M = 1
*
.PARAM LE = {L - LDP}
*
S1 D S DG GND SWN
C1 D S {M*(CBDJ*CJP*LS*W + CBDS*CJSWP*(2*LS + W))}
*D B
.MODEL SWN VSWITCH ( VON = {0.49} VOFF = {0.55} RON={1/(2*M*(W/LE)*(KPP/2)*10)} ROFF={1G} )
.ENDS
.SUBCKT MDSWN D S DG GND PARAMS: W = 100U L = 10U M = 1
*
.PARAM LE = {L - LDN}
*
S1 D S DG GND SWN
C1 D S {M*(CBDJ*CJN*LS*W + CBDS*CJSWN*(2*LS + W))}
*D B
.MODEL SWN VSWITCH ( VON = {0.55} VOFF = {0.49} RON={1/(2*M*(W/LE)*(KPN/2)*10)} ROFF={1G} )
.ENDS
.SUBCKT MSWN D G S PARAMS: W = 100U L = 10U M = 1
*
.PARAM LE = {L - LDN}
*
*C1 D S {M*(CBDJ*CJN*LS*W + CBDS*CJSWN*(2*LS + W))}
*D B
*C2 G S {M*2/3*COX*(W*LE) + CGSON*W}
*C3 G D {CGDON*W}
S1 D S G S SWN
.MODEL SWN VSWITCH ( VON = {VTON+1} VOFF = {VTON} RON={1/(2*M*(W/L)*(KPN/2)*10)} ROFF={1G} )
.ENDS
*
* CONNECTIONS: A
* | C
* | |
.SUBCKT D_Z18V 1 2
D1 1 2 DZ_18V
.ENDS
.PARAM ISZ = 5P
.PARAM NZ = {0.3/(VT*Log(1 + 5.0M/ISZ))}
.MODEL DZ_18V D( IS={ISz} N={Nz} BV=18.0 IBV=5.0M EG={8*Nz*VT})
.SUBCKT RR1SFF S R R1 Q Q_ VCC GND
+ PARAMS: VOUTH=5.0 VOUTL=0 RIN=1E12 DELAY=10N ROUT=10
.PARAM W1 = 100U
.PARAM L1 = 10U
.PARAM W2 = 100U
.PARAM L2= 10U
.PARAM W3 = 10U
.PARAM L3 = 25U
.PARAM W4 = 10U
.PARAM L4= 100U
*
XU1 Q GND S GND Q_ GND COMP2INPNORSD
+ PARAMS: ROUT={ROUT} DELAYLH={1N} DELAYHL={1N} VOUTH={VOUTH} VOUTL={VOUTL}
+ VTHRES1={0.5*(VOUTH-VOUTL)} VTHRES2={VTOCN}
XU2 VCC R R1 GND Q_ GND Q VCC GND COMP3INPNORSD
+ PARAMS: ROUT={ROUT} DELAYLH={15N} DELAYHL={1N} VOUTH={VOUTH} VOUTL={VOUTL}
+ VTHRES1={VTOCP} VTHRES2={VTOCN} VTHRES3={0.49*(VOUTH-VOUTL)}
*C1 S GND {0.5*COX*(W1*L1) + CGSON*W1}
*C2 R VCC {0.5*COX*(W2*L2) + CGSOP*W2}
*C3 R1 GND {0.5*COX*(W3*L3) + CGSON*W3}
*C4 R1 VCC {0.5*COX*(W4*L4) + CGSOP*W4}
.ENDS
.SUBCKT COMP2INPNORSD IN1+ IN1- IN2+ IN2- OUT GND
+ PARAMS: ROUT=0 DELAYLH=0 DELAYHL=0 VOUTH=0 VOUTL=0 VTHRES1=0 VTHRES2=0
*
.PARAM TDELLH = {IF ( (DELAYLH < 1E-9) , 1E-9, DELAYLH ) }
.PARAM TDELHL = {IF ( (DELAYHL < 1E-9) , 1E-9, DELAYHL ) }
.PARAM RO = {IF ( (TDEL > 1E-15) & (ROUT < 1), 1, ROUT ) }
.PARAM TDEL = {(TDELLH+TDELHL)/2}
.PARAM COUT={TDEL/(0.693*(RO+1U))}
.PARAM RDELLH = {TDELLH/(0.693*(COUT+1F))}
.PARAM RDELHL = {TDELHL/(0.693*(COUT+1F))}
EOUT OUT GND VALUE= { IF ( (V(IN1+,IN1-) > {VTHRES1}) | (V(IN2+,IN2-) > {VTHRES2}),
+ VOUTL + RDELLH*I(EOUT), VOUTH + RDELHL*I(EOUT) ) }
COUT OUT GND {COUT}
.ENDS COMP2INPNORSD
.SUBCKT COMP3INPNORSD IN1+ IN1- IN2+ IN2- IN3+ IN3- OUT VCC GND
+ PARAMS: ROUT=0 DELAYLH=0 DELAYHL=0 VOUTH=0 VOUTL=0 VTHRES1=0 VHYST1=0 VTHRES2=0 VHYST2=0 VTHRES3=0 VHYST3=0
*
.PARAM TDELLH = {IF ( (DELAYLH < 1E-9) , 1E-9, DELAYLH ) }
.PARAM TDELHL = {IF ( (DELAYHL < 1E-9) , 1E-9, DELAYHL ) }
.PARAM RO = {IF ( (TDEL > 1E-15) & (ROUT < 1), 1, ROUT ) }
.PARAM TDEL = {(TDELLH+TDELHL)/2}
.PARAM COUT={TDEL/(0.693*(RO+1U))}
.PARAM VREFN = {(15-VTOHN)}
.PARAM VREFP = {(15-VTOHP)}
.PARAM RDELLH = {TDELLH/(0.693*(COUT+1F))*VREFP}
.PARAM RDELHL = {TDELHL/(0.693*(COUT+1F))*VREFN}
*
EOUT OUT GND VALUE= { IF ( (V(IN1+,IN1-) > {VTHRES1}) | (V(IN2+,IN2-) > {VTHRES2}) | (V(IN3+,IN3-) > {VTHRES3}),
+ VOUTL + RDELLH*I(EOUT)*V(1,GND), VOUTH + RDELHL*I(EOUT)*V(1,GND) ) }
E1 1 GND VALUE= { IF ( (V(VCC,GND) > {VTOHP+0.01}), 1/(V(VCC,GND)-VTOHP), 100 ) }
COUT OUT GND {COUT}
.ENDS COMP3INPNORSD
.SUBCKT 1N4148 1 2
D1 1 2 D_1N4148_1
.MODEL D_1N4148_1 D( IS=1N N=1.7 BV=75 IBV=5U RS=2M
+ CJO=4P VJ=750M M=330M FC=500M TT=25.9N
+ EG=1.11 XTI=3 KF=0 AF=1 )
.ENDS
.PARAM LS = 1.0U
.PARAM VTOP_ = 0.31
.PARAM VTOP = 0.14
.PARAM VTON = 0.14
.PARAM VTOMP = 0.6
.PARAM VTOMN = 0.55
.PARAM VTOHP = 0.85
.PARAM VTOHN = 0.80
.PARAM LAMBDA = 2M
.PARAM KPN = 6.0E-05
.PARAM KPP = 3.0E-05
.PARAM LDN = 0.07U
.PARAM LDP = 0.07U
.PARAM RSW = 1810
.PARAM RSN = 1.41
.PARAM VBMUL = 1E6
.PARAM RPAR = 1T
.PARAM CBDJ = 1
.PARAM CBDS = 1
.PARAM CN = 0.8
*0.8U
.PARAM CJN = {CN*180U}
.PARAM CJP = {CN*300U}
.PARAM CJSWN = {CN*1N}
.PARAM CJSWP = {CN*2.2N}
.PARAM XJN = 0.2U
.PARAM CGSON = {CN*0.6 * XJN * COX}
.PARAM CGDON = {CGSON}
.PARAM XJP = 0.3U
.PARAM CGSOP = {CN*0.6 * XJN * COX}
.PARAM CGDOP = {CGSOP}
.PARAM EPSSIO2 = {3.9*8.854214871E-12}
.PARAM TOX = 1000E-10
.PARAM COX = {EPSSIO2/TOX}
.PARAM EC = 1.5E6
.PARAM VTOCP = {VTOHP+0.05}
.PARAM VTOCN = {VTOHN+0.05}
*CG
.PARAM CCG = 0.2
.PARAM CJNCG = {CCG*180U}
.PARAM CJPCG = {CCG*300U}
.PARAM CJSWNCG = {CCG*1N}
.PARAM CJSWPCG = {CCG*2.2N}
.PARAM XJNCG = 0.2U
.PARAM CGSONCG = {CCG*0.6 * XJNCG * COXCG}
.PARAM CGDONCG = {CGSONCG}
.PARAM XJPCG = 0.3U
.PARAM CGSOPCG = {CCG*0.6 * XJNCG * COXCG}
.PARAM CGDOPCG = {CGSOPCG}
.PARAM TOXCG = 1000E-10
.PARAM COXCG = {EPSSIO2/TOXCG}

181
examples/p-to-n-examples/ad22057n.cir
View File

@ -0,0 +1,181 @@
* AD22057N SPICE Macro-model
* Description: Amplifier
* Generic Desc: Bipolar, CSAmp, G=20, BiDir, Auto
* Developed by: ARG / ADSC
* Revision History: 08/10/2012 - Updated to new header style
* 1.0 (11/1995)
* Copyright 1995, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* This version of the AD22057 model simulates the worst-case
* parameters of the 'N' grade. The worst-case parameters
* used correspond to those in the data sheet.
*
* END Notes
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | A1 out
* | | | | | A2 in
* | | | | | | offset
* | | | | | | | output
* | | | | | | | |
.SUBCKT AD22057N 1 2 99 50 30 31 40 49
*
* A1 INPUT ATTENUATORS, GAIN, AND OFFSET RESISTORS
*
R1 1 3 200K
R2 2 4 200K
RS1 3 16 1K
RS2 4 18 1K
R3 3 5 41K
R4 4 6 41K
R5 5 6 2.55919K TC=-600U
R6 5 50 250
R7 6 50 250
R8 5 19 9K
R9 6 7 10K
R10 19 40 2K
R11 19 50 2K
R12 7 30 100K
R16 7 50 10K
C1 16 50 5P
C2 17 50 5P
*
* A1 INPUT STAGE AND POLE AT 1MHZ
*
I1 99 8 7.55U
Q1 11 16 9 QP 1
Q2 12 17 10 QP 1
R21 11 50 6.89671K
R22 12 50 6.89671K
R23 8 9 .335
R24 8 10 .335
C3 11 12 11.5P
EOS 61 17 POLY(1) 33 0 -61.149U 1.2
ETC 18 61 POLY(1) 60 0 -49.665M 1
ITC 0 60 49.665U
RTC 60 0 1E3 TC=-107U
*
* GAIN STAGE AND DOMINANT POLE AT 400HZ
*
EREF 98 50 POLY(2) 99 0 50 0 0 0.5 0.5
G1 98 13 12 11 144.997U
R25 13 98 6.89671E6
C4 13 98 57.6923P
D1 13 99 DX
D2 50 13 DX
*
* COMMON MODE STAGE WITH ZERO AT 1KHZ
*
ECM 32 0 POLY(2) 1 0 2 0 0 0.5 0.5
R28 32 33 1E6
R29 33 0 10
CCM 32 33 159P
*
* NEGATIVE ZERO AT 0.6MHZ
*
E1 23 98 13 98 1E6
R26 23 24 1E3
R27 24 98 1E-3
FNZ 23 24 VNZ -1
ENZ 25 98 23 24 1
VNZ 26 98 DC 0
CNZ 25 26 265P
*
* POLE AT 5MHZ
*
G2 98 20 24 98 1E-6
R30 20 98 1E6
C5 20 98 32F
*
* A1 OUTPUT STAGE
*
EIN1 99 27 POLY(1) 20 98 1.5072 1.124
Q216 50 27 28 QP375 3.444
Q218 7 29 99 QP350 9.913
R31 28 29 27K
I2 99 29 4.75U
*
* A2 INPUT STAGE
*
I3 99 34 2.516667U
Q3 35 31 37 QP 1
Q4 36 39 38 QP 1
R32 35 50 106.103K
R33 36 50 106.103K
R34 34 37 85.414K
R35 34 38 85.414K
R13 40 41 20K
R14 41 50 20K
R15 41 49 10K
R17 39 41 95K
*
* A2 1ST GAIN STAGE AND SLEW RATE
*
G3 98 42 36 35 30.159U
R36 42 98 1E6
E2 99 43 POLY(1) 99 98 -0.473 1
E3 44 50 POLY(1) 98 50 -0.473 1
D3 42 43 DX
D4 44 42 DX
*
* A2 2ND GAIN STAGE AND DOMINANT POLE AT 12HZ
*
G4 98 45 42 98 2.5U
R37 45 98 132.629E6
C7 45 98 100P
D5 45 59 DX
D6 55 45 DX
VC1 59 99 5
VC2 50 55 5
*
* NEGATIVE ZERO AT 1MHZ
*
E4 51 98 45 98 1E6
R38 51 52 1E6
R39 52 98 1
FNZ2 51 52 VNZ2 -1
ENZ2 53 98 51 52 1
VNZ2 54 98 0
CNZ2 53 54 159F
*
* A2 OUTPUT STAGE
*
ISY 99 50 469U
EIN2 99 56 POLY(1) 52 98 1.6901 112.132E-3
RIN 46 56 10K
Q316 50 46 47 QP375 1.778
Q310 50 47 48 QP375 5.925
Q318 49 48 57 50 QP350 9.913
I4 99 47 4.75U
I5 99 48 9.5U
VSC 99 57 0
FSC 58 99 VSC 1
QSC 46 58 99 QP350 1
RSC 99 58 89
*
* MODELS USED
*
.MODEL QP350 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350
+RC=200)
.MODEL QP375 PNP(IS=1.4E-15 CJE=.01P CJC=.05P RE=20 RC=400 RB=100)
.MODEL QP AKO:QP350 PNP(BF=150 VA=100)
.MODEL DX D(CJO=1F RS=.1)
.ENDS
.MODEL QP351 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350
+RC=200)

40
examples/p-to-n-examples/op-test-adi.cir
View File

@ -0,0 +1,40 @@
OpAmp Test
vddp vp 0 15
vddn vn 0 0
voff off 0 -1
*vin in 0 0
.include ad22057n.cir
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | A1 out
* | | | | | A2 in
* | | | | | | offset
* | | | | | | | output
* | | | | | | | |
*SUBCKT AD22057N 1 2 99 50 30 31 40 49
Xopmap in 0 vp vn a1 a1 off outo AD22057N
Rout outo a1 200k
Ca1 a1 0 500p
.dc vin 0.1 0.2 0.01
vin in 0 DC 0 PULSE(0.1 0.2 200uS 200uS 200uS 5m 10m)
.tran 10u 10m
.control
run
plot dc1.v(outo) vs dc1.v(in)
plot v(in) v(a1) v(outo)
.endc
.end

197
examples/p-to-n-examples/op-test.cir
View File

@ -0,0 +1,197 @@
OpAmp Test
vddp vp 0 3
vddn vn 0 -3
*vin in 0 0
* OPA171 IN+ IN- VCC VEE OUT
.include OPA171.txt
Xopmap 0 ino vp vn outo OPA171
*Xopmap 0 ino outo vp vn CLC409
Rin in ino 1k
Rfb ino outo 3k
*.dc vin -1 1 0.1
vin in 0 DC 0 PULSE(-0.5 0.5 2uS 200NS 200NS 5uS 10uS)
.tran 100n 10u
.options vntol=10u
.control
run
plot v(in) v(outo)
.endc
*
* This is a Very Wide band, Low Distortion Monolithic
* Current Feedback Op Amp.
*
* Version 1, Rev. A, Date 04-09-92, By RRS
*
* Connections: Non-Inverting Input
* | Inverting Input
* | | Output
* | | | +Vcc
* | | | | -Vcc
* | | | | |
.SUBCKT CLC409 3 2 6 7 4
*
* DC BIAS MIRROR
*
R1 7 4 28K
R2 7 9 271
R3 10 4 335
*
G1 7 11 POLY(2) 7 9 7 4 0 3.15M 21.5U
C3 11 0 128F
*
G2 14 4 POLY(1) 10 4 0 2.95M
C4 14 0 104F
*
* INPUT VOLTAGE BUFFER
*
E1 3 17 POLY(1) 35 0 1.0M 1.673
C6 17 0 1.00P
*
Q1 10 17 12 QINP
D3 11 12 DY
Q2 9 17 13 QINN
D4 13 14 DY
*
G3 2 0 POLY(1) 36 0 0 9.282M
C10 2 0 2.9P
*
D5 22 2 DY
Q3 21 11 22 QINN
D6 2 23 DY
Q4 24 14 23 QINP
*
* CURRENT MIRROR GAIN BLOCKS
*
R10 7 20 640
V1 20 21 1.9
C8 21 28 294F
G4 7 28 POLY(1) 7 20 0 4.3M
R15 7 28 102K
C13 28 0 641F
D1 28 26 DX
V3 7 26 1.65
G6 7 30 POLY(1) 7 20 0 2.74M
C15 30 0 676F
*
R13 25 4 640
V2 24 25 1.85
C12 24 29 294F
G5 29 4 POLY(1) 25 4 0 4.5M
R16 29 4 761K
C14 29 0 312F
D2 27 29 DX
V4 27 4 1.55
G7 31 4 POLY(1) 25 4 0 6.74M
C16 31 0 330F
*
* OUTPUT STAGE AND COMPENSATION CAPACITORS
*
R14 28 29 45.0
Q5 4 29 30 QOUTP1
Q6 7 28 31 QOUTN1
*
C9 21 33 .935P
C11 24 33 .935P
C17 33 0 4.00P
R19 33 6 10
*
Q7 7 30 33 QOUTN2
Q8 4 31 33 QOUTP2
*
* NOISE BLOCKS
*
R20 35 0 122
R21 35 0 122
*
R22 36 0 122
R23 36 0 122
*
* MODELS
*
.MODEL DX D TT=200N
.MODEL DY D IS=0.166F
*
.MODEL QINN NPN
+ IS =0.166f BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01
+ IKF=2.462E-02 ISE=2.956E-17 NE =1.197E+00 BR =3.719E+01
+ NR =1.000E+00 VAR=1.696E+00 IKR=3.964E-02 ISC=1.835E-19
+ NC =1.700E+00 RB =118 IRB=0.000E+00 RBM=65.1
+ RC =2.645E+01 CJE=1.632E-13 VJE=7.973E-01
+ MJE=4.950E-01 TF =1.948E-11 XTF=1.873E+01 VTF=2.825E+00
+ ITF=5.955E-02 PTF=0.000E+00 CJC=1.720E-13 VJC=8.046E-01
+ MJC=4.931E-01 XCJC=589m TR =4.212E-10 CJS=629f
+ MJS=0 KF =2.000E-12 AF =1.000E+00 FC =9.765E-01
*
.MODEL QOUTN1 NPN
+ IS =3.954E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01
+ IKF=4.590E-02 ISE=5.512E-17 NE =1.197E+00 BR =3.719E+01
+ NR =1.000E+00 VAR=1.696E+00 IKR=7.392E-02 ISC=3.087E-19
+ NC =1.700E+00 RB =3.645E+01 IRB=0.000E+00 RBM=8.077E+00
+ RE =3.010E-01 RC =2.702E+01 CJE=2.962E-13
+ MJE=4.950E-01 TF =1.904E-11 XTF=1.873E+01 VTF=2.825E+00
+ ITF=1.110E-01 PTF=0.000E+00 CJC=2.846E-13 VJC=8.046E-01
+ MJC=4.931E-01 XCJC=1.562E-01 TR =5.832E-10 CJS=5.015E-13
+ VJS=5.723E-01 MJS=4.105E-01 KF =2.000E-12 AF =1.000E+00
+ FC =9.765E-01
*
.MODEL QOUTN2 NPN
+ IS =9.386E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01
+ IKF=1.089E-01 ISE=1.308E-16 NE =1.197E+00 BR =3.956E+01
+ NR =1.000E+00 VAR=1.696E+00 IKR=7.392E-02 ISC=1.378E-18
+ NC =1.700E+00 RB =65.4 IRB=0.000E+00 RBM=1.683E+00
+ RC =1.857E+01 CJE=7.030E-13 VJE=7.973E-01
+ MJE=4.950E-01 TF =1.875E-11 XTF=1.873E+01 VTF=2.825E+00
+ ITF=2.635E-01 PTF=0.000E+00 CJC=6.172E-13 VJC=8.046E-01
+ MJC=4.931E-01 XCJC=860m TR =1.069E-09 CJS=1.028E-12
+ VJS=5.723E-01 MJS=4.105E-01 KF =2.000E-12 AF =1.000E+00
+ FC =9.765E-01
*
.MODEL QINP PNP
+ IS =0.166f BF =7.165E+01 NF =1.000E+00 VAF=2.000E+01
+ IKF=1.882E-02 ISE=6.380E-16 NE =1.366E+00 BR =1.833E+01
+ NR =1.000E+00 VAR=1.805E+00 IKR=1.321E-01 ISC=3.666E-18
+ NC =1.634E+00 RB =78.8 IRB=0.000E+00 RBM=57.6
+ RC =3.739E+01 CJE=1.588E-13 VJE=7.975E-01
+ MJE=5.000E-01 TF =3.156E-11 XTF=5.386E+00 VTF=2.713E+00
+ ITF=5.084E-02 PTF=0.000E+00 CJC=2.725E-13 VJC=7.130E-01
+ MJC=4.200E-01 XCJC=741m TR =7.500E-11 CJS=515f
+ MJS=0 KF =2.000E-12 AF =1.000E+00 FC =8.803E-01
*
.MODEL QOUTP1 PNP
+ IS =2.399E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01
+ IKF=3.509E-02 ISE=1.190E-15 NE =1.366E+00 BR =1.900E+01
+ NR =1.000E+00 VAR=1.805E+00 IKR=2.464E-01 ISC=6.745E-18
+ NC =1.634E+00 RB =1.542E+01 IRB=0.000E+00 RBM=4.059E+00
+ RC =4.174E+01 CJE=2.962E-13 VJE=7.975E-01
+ MJE=5.000E-01 TF =3.107E-11 XTF=5.386E+00 VTF=2.713E+00
+ ITF=9.481E-02 PTF=0.000E+00 CJC=4.508E-13 VJC=7.130E-01
+ MJC=4.200E-01 XCJC=1.562E-01 TR =9.500E-11 CJS=1.045E-12
+ VJS=6.691E-01 MJS=3.950E-01 KF =2.000E-12 AF =1.000E+00
+ FC =8.803E-01
*
.MODEL QOUTP2 PNP
+ IS =5.693E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01
+ IKF=8.328E-02 ISE=5.742E-15 NE =1.366E+00 BR =1.923E+01
+ NR =1.000E+00 VAR=1.805E+00 IKR=5.848E-01 ISC=1.586E-17
+ NC =1.634E+00 RB =56.5 IRB=0.000E+00 RBM=51.7
+ RC =1.767E+00 CJE=7.030E-13 VJE=7.975E-01
+ MJE=5.000E-01 TF =3.073E-11 XTF=5.386E+00 VTF=2.713E+00
+ ITF=2.250E-01 PTF=0.000E+00 CJC=9.776E-13 VJC=7.130E-01
+ MJC=4.200E-01 XCJC=923m TR =1.450E-10 CJS=1.637E-12
+ VJS=6.691E-01 MJS=3.950E-01 KF =2.000E-12 AF =1.000E+00
+ FC =8.803E-01
*
.ENDS CLC409
.end

32
examples/p-to-n-examples/relax_osc_st.cir
View File

@ -0,0 +1,32 @@
Relaxation oscillator
* ST AN4071, Fig. 26
* www.st.com/resource/en/application_note/dm00050759.pdf
.include Opamps_Comparators_ST.lib
XICOMP2 VM1 VP1 VS1 VCCP VCCN TS302X
* http://www.st.com/resource/en/cad_symbol_library/opamps_comparators_st.zip
vdd vccp 0 5
vss vccn 0 0
R1 vs1 vm1 10k
R2 vp1 0 10k
R3 vp1 vccp 10k
R4 vs1 vp1 10k
C1 vm1 0 1n
.tran 100n 500u uic
.option rshunt=1e12
.control
save vs1 vm1 vp1
run
plot vs1 vm1 vp1
linearize vs1
fft vs1
plot mag(vs1) xlimit 1k 100k
.endc
.end

13
examples/p-to-n-examples/remcirc-test.cir
View File

@ -0,0 +1,13 @@
remcirc test
v1 1 0 1
v2 2 0 1
v3 3 0 1
.include rtest.lib
.control
repeat 1000
reset
end
.endc
.end

4
examples/p-to-n-examples/rtest.lib
View File

@ -0,0 +1,4 @@
R1 1 0 res
R2 2 0 res
R3 3 0 res
.model res r r=1
Write Preview
Loading…
Cancel
Save