replace parameter name subthres by subslope

8 years ago · 72e03e7eab
10 changed files with 33 additions and 71 deletions
--- a/src/spicelib/devices/vdmos/vdmos.c
+++ b/src/spicelib/devices/vdmos/vdmos.c
@ -82,7 +82,7 @@ IFparm VDMOSmPTable[] = { /* model parameters */
 IOP("mtriode", VDMOS_MOD_MTRIODE, IF_REAL,   "Conductance multiplier in triode region"),

 /* weak inversion */
- IOP("subthres",  VDMOS_MOD_SUBTHRES,   IF_REAL, "Current(per volt Vds) to switch from square law to exponential subthreshold conduction"),
+ IOP("subslope",  VDMOS_MOD_SUBSLOPE,   IF_REAL, "Slope of weak inversion log current versus vgs - vth"),
 IOP("subshift",  VDMOS_MOD_SUBSHIFT,   IF_REAL, "Shift of weak inversion plot on the vgs axis"),

 /* body diode */
--- a/src/spicelib/devices/vdmos/vdmosdefs.h
+++ b/src/spicelib/devices/vdmos/vdmosdefs.h
@ -331,7 +331,7 @@ typedef struct sVDMOSmodel {       /* model structure for a resistor */
    double VDMOScgdmax;
    double VDMOSa;
    double VDMOScgs;
-    double VDMOSsubth;
+    double VDMOSsubsl;
    double VDMOSsubshift;
    double VDMOSmtr;

@ -377,7 +377,7 @@ typedef struct sVDMOSmodel {       /* model structure for a resistor */
    unsigned VDMOScgdmaxGiven   :1;
    unsigned VDMOScgsGiven   :1;
    unsigned VDMOSaGiven   :1;
-    unsigned VDMOSsubthGiven   :1;
+    unsigned VDMOSsubslGiven   :1;
    unsigned VDMOSsubshiftGiven   :1;
    unsigned VDMOSmtrGiven   :1;

@ -444,7 +444,7 @@ enum {
    VDMOS_MOD_CGS,
    VDMOS_MOD_RB,
    VDMOS_MOD_MTRIODE,
-    VDMOS_MOD_SUBTHRES,
+    VDMOS_MOD_SUBSLOPE,
    VDMOS_MOD_SUBSHIFT,
    VDMOS_MOD_BV,
    VDMOS_MOD_IBV,
--- a/src/spicelib/devices/vdmos/vdmosload.c
+++ b/src/spicelib/devices/vdmos/vdmosload.c
@ -15,7 +15,7 @@ VDMOS: 2018 Holger Vogt
 #include "ngspice/suffix.h"

 static double
-cweakinv(double n, double shift, double vgst, double vds, double lambda, double beta, double vt, double mtr);
+cweakinv(double sl, double shift, double vgst, double vds, double lambda, double beta, double vt, double mtr);


 int
@ -367,24 +367,24 @@ VDMOSload(GENmodel *inModel, CKTcircuit *ckt)
                arg = 0;
                /* drain current including subthreshold current
                 * numerical differentiation for gd and gm with a delta of 2 mV */
-                if (model->VDMOSsubthGiven && (here->VDMOSmode == 1)) {
+                if (model->VDMOSsubslGiven && (here->VDMOSmode == 1)) {
                    double delta = 0.001;
-                    cdrain = cweakinv(model->VDMOSsubth, model->VDMOSsubshift, vgst, vds, model->VDMOSlambda,
+                    cdrain = cweakinv(model->VDMOSsubsl, model->VDMOSsubshift, vgst, vds, model->VDMOSlambda,
                        Beta, vt, model->VDMOSmtr);
                    /* gd */
                    double vds1 = vds + delta;
-                    double cdrp = cweakinv(model->VDMOSsubth, model->VDMOSsubshift, vgst, vds1, model->VDMOSlambda,
+                    double cdrp = cweakinv(model->VDMOSsubsl, model->VDMOSsubshift, vgst, vds1, model->VDMOSlambda,
                        Beta, vt, model->VDMOSmtr);
                    vds1 = vds - delta;
-                    double cdrm = cweakinv(model->VDMOSsubth, model->VDMOSsubshift, vgst, vds1, model->VDMOSlambda,
+                    double cdrm = cweakinv(model->VDMOSsubsl, model->VDMOSsubshift, vgst, vds1, model->VDMOSlambda,
                        Beta, vt, model->VDMOSmtr);
                    here->VDMOSgds = (cdrp - cdrm) / (2. * delta);
                    /* gm */
                    double vgst1 = vgst + delta;
-                    cdrp = cweakinv(model->VDMOSsubth, model->VDMOSsubshift, vgst1, vds, model->VDMOSlambda,
+                    cdrp = cweakinv(model->VDMOSsubsl, model->VDMOSsubshift, vgst1, vds, model->VDMOSlambda,
                        Beta, vt, model->VDMOSmtr);
                    vgst1 = vgst - delta;
-                    cdrm = cweakinv(model->VDMOSsubth, model->VDMOSsubshift, vgst1, vds, model->VDMOSlambda,
+                    cdrm = cweakinv(model->VDMOSsubsl, model->VDMOSsubshift, vgst1, vds, model->VDMOSlambda,
                        Beta, vt, model->VDMOSmtr);
                    here->VDMOSgm = (cdrp - cdrm) / (2. * delta);
                    here->VDMOSgmbs = 0.;
--- a/src/spicelib/devices/vdmos/vdmosmask.c
+++ b/src/spicelib/devices/vdmos/vdmosmask.c
@ -48,8 +48,8 @@ VDMOSmAsk(CKTcircuit *ckt, GENmodel *inst, int which, IFvalue *value)
        case VDMOS_MOD_MTRIODE:
            value->rValue = model->VDMOSmtr;
            return(OK);
-        case VDMOS_MOD_SUBTHRES:
-            value->rValue = model->VDMOSsubth;
+        case VDMOS_MOD_SUBSLOPE:
+            value->rValue = model->VDMOSsubsl;
            return(OK);
        case VDMOS_MOD_SUBSHIFT:
            value->rValue = model->VDMOSsubshift;
--- a/src/spicelib/devices/vdmos/vdmosmpar.c
+++ b/src/spicelib/devices/vdmos/vdmosmpar.c
@ -121,9 +121,9 @@ VDMOSmParam(int param, IFvalue *value, GENmodel *inModel)
            model->VDMOSmtr = value->rValue;
            model->VDMOSmtrGiven = TRUE;
            break;
-        case VDMOS_MOD_SUBTHRES:
-            model->VDMOSsubth = value->rValue;
-            model->VDMOSsubthGiven = TRUE;
+        case VDMOS_MOD_SUBSLOPE:
+            model->VDMOSsubsl = value->rValue;
+            model->VDMOSsubslGiven = TRUE;
            break;
        case VDMOS_MOD_SUBSHIFT:
            model->VDMOSsubshift = value->rValue;
--- a/src/spicelib/devices/vdmos/vdmosset.c
+++ b/src/spicelib/devices/vdmos/vdmosset.c
@ -72,8 +72,8 @@ VDMOSsetup(SMPmatrix *matrix, GENmodel *inModel, CKTcircuit *ckt,
        if (!model->VDMOSaGiven) {
            model->VDMOSa = 1.;
        }
-        if (!model->VDMOSsubthGiven) {
-            model->VDMOSsubth = 0;
+        if (!model->VDMOSsubslGiven) {
+            model->VDMOSsubsl = 0;
        }
        if (!model->VDMOSsubshiftGiven) {
            model->VDMOSsubshift = 0;
--- a/vdmos/IXTP6N100D2-n-weak-inv.cir
+++ b/vdmos/IXTP6N100D2-n-weak-inv.cir
@ -2,63 +2,25 @@ VDMOS output

 m1 d g s s IXTP6N100D2
 m2 d g s2 s2 IXTP6N100D2_2
-m3 d g s3 s3 IXTP6N100D2_3

 *.model dmod d  is=10n rs=0.05

-.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF subthres=250m)
+* LTSPICE model parameters
+*.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 *Vj=0.1 Cjo=3200pF subthres=2.5m)

-.MODEL IXTP6N100D2_2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF subthres=500m)
-
-.MODEL IXTP6N100D2_3 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF)
-
-.model FDB3682 VDMOS(Rg=3 Rd=26.8m Vto=4 subthres=.1 mtriode=1.8 Kp=18 Cgdmax=400p Cgdmin=20p A=.5 Cgs=1.25n Cjo=1n M=.6 Is=1.8p Rb=14.2m mfg=Fairchild Vds=100 Ron=32m Qg=18.5n)
+* equivalent ngspice model parameters
+.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF subslope=43m subshift=-25m)

 vd d 0 -0.6
 vg g 0 -2.3
 vs s 0 0
-vs2 s2 0 0
-vs3 s3 0 0
-
-*.dc  vg -3.1 -2.1 0.01 vd 0.2 1 0.2

 .control
-op
 dc  vg -3.1 -2.1 0.01 vd 0.2 1 0.2
-plot vs#branch vs2#branch vs3#branch
-plot log(vs#branch) log(vs2#branch) log(vs3#branch)
+plot vs#branch
+plot vs#branch ylog
 dc  vd 0 5 0.01 vg -3.2 -2 0.2
-plot vs#branch vs2#branch vs3#branch
+plot vs#branch
 .endc

-* David Zan, (c) 2017/03/02 Preliminary
-.MODEL IXTH80N20L VDMOS Nchan Vds=200
-+ VTO=4 KP=15
-+ Lambda=2m
-+ Mtriode=0.4
-+ Ksubthres=150m
-+ Rs=5m Rd=10m Rds=200e6
-+ Cgdmax=9000p Cgdmin=300p A=0.25
-+ Cgs=5500p Cjo=11000p
-+ Is=10e-6 Rb=8m
-+ BV=200 IBV=250e-6
-+ NBV=4
-+ TT=250e-9
-
-* David Zan, (c) 2017/03/02 Preliminary
-.MODEL IXTH48P20P VDMOS Pchan Vds=200
-+ VTO=-4 KP=10
-+ Lambda=5m
-+ Mtriode=0.3
-+ Ksubthres=120m
-+ Rs=10m Rd=20m Rds=200e6
-+ Cgdmax=6000p Cgdmin=100p A=0.25
-+ Cgs=5000p Cjo=9000p
-+ Is=2e-6 Rb=20m
-+ BV=200 IBV=250e-6
-+ NBV=4
-+ TT=260e-9
-
-
-
 .end
--- a/vdmos/VDMOS-DIO-AC.cir
+++ b/vdmos/VDMOS-DIO-AC.cir
@ -3,17 +3,17 @@ Capacitance and current comparison between models d and bulk diode in vdmos
 D1 ad kd dio
 .model dio d TT=1371n IS=2.13E-08 N=1.564 RS=0.0038 m=0.548 Vj=0.1 Cjo=3200pF

-Va ad 0 DC -2 AC 1 $ DC 0.5
+Va ad 0 DC 0.5 AC 1 $ DC -20
 Vk kd 0 0

 m1 d g s s IXTP6N100D2
-.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF subthres=2.5m)
+.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF subthres=2.5m subslope=43m subshift=-25m)

-Vd d 0 DC 2 AC 1 $ DC -0.5
+Vd d 0 DC -0.5 AC 1 $ DC 20
 Vg g 0 -5  $ transistor is off
 Vs s 0 0

-.ac dec 10 1 10K
+.ac dec 10 1 100K

 .control
 save @d1[id] @m1[id] all
--- a/vdmos/ro_11_vdmos.cir
+++ b/vdmos/ro_11_vdmos.cir
@ -20,8 +20,8 @@ xinv8 10 9 1 0 inv
 xinv9 2 10 1 0 inv


-.model  N1  vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n subthres=0.2
-.model  P1  vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n pchan subthres=0.2
+.model  N1  vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n subslope=0.2
+.model  P1  vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n pchan subslope=0.2

 .tran 0.1n 1u

--- a/vdmos/vdmos-out.cir
+++ b/vdmos/vdmos-out.cir
@ -2,7 +2,7 @@ VDMOS output

 m1 d g s s n1
 *.model n1 vdmos rb=0.05 is=10n kp=2 bv=12 rd=0.1
-.model  N1  vdmos vto=1 cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-4 rb=1e4 is=1e-9 bv=12 cjo=1p subthres=1
+.model  N1  vdmos vto=1 cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-4 rb=1e4 is=1e-9 bv=12 cjo=1p subslope=0.1
 *d1 s d dmod
 *.model dmod d  is=10n rs=0.05

@ -17,7 +17,7 @@ vb b 0 0
 dc vd -2 15 0.05 vg 0 5 1
 plot vs#branch
 dc vg 0 5 0.05 vd 0.5 2.5 0.5
-plot log(vs#branch)
+plot vs#branch ylog
 .endc

 .end